JP2009524932A5 - - Google Patents
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- Publication number
- JP2009524932A5 JP2009524932A5 JP2008552305A JP2008552305A JP2009524932A5 JP 2009524932 A5 JP2009524932 A5 JP 2009524932A5 JP 2008552305 A JP2008552305 A JP 2008552305A JP 2008552305 A JP2008552305 A JP 2008552305A JP 2009524932 A5 JP2009524932 A5 JP 2009524932A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- dielectric layer
- opening
- forming
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 claims 5
- 239000004020 conductor Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 2
- 238000005530 etching Methods 0.000 claims 1
- 230000001590 oxidative effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/339,132 US7579258B2 (en) | 2006-01-25 | 2006-01-25 | Semiconductor interconnect having adjacent reservoir for bonding and method for formation |
| US11/339,132 | 2006-01-25 | ||
| PCT/US2006/061737 WO2007100404A2 (en) | 2006-01-25 | 2006-12-07 | Semiconductor interconnect having adjacent reservoir for bonding and method for formation |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009524932A JP2009524932A (ja) | 2009-07-02 |
| JP2009524932A5 true JP2009524932A5 (OSRAM) | 2010-02-04 |
| JP5138611B2 JP5138611B2 (ja) | 2013-02-06 |
Family
ID=38284743
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008552305A Active JP5138611B2 (ja) | 2006-01-25 | 2006-12-07 | 接合用の隣接収納部を有する半導体相互接続、及び形成方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US7579258B2 (OSRAM) |
| JP (1) | JP5138611B2 (OSRAM) |
| CN (1) | CN101496166B (OSRAM) |
| TW (1) | TWI415216B (OSRAM) |
| WO (1) | WO2007100404A2 (OSRAM) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8134235B2 (en) | 2007-04-23 | 2012-03-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional semiconductor device |
| US8053900B2 (en) * | 2008-10-21 | 2011-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through-substrate vias (TSVs) electrically connected to a bond pad design with reduced dishing effect |
| US8796822B2 (en) * | 2011-10-07 | 2014-08-05 | Freescale Semiconductor, Inc. | Stacked semiconductor devices |
| JP2016018879A (ja) * | 2014-07-08 | 2016-02-01 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
| US10636767B2 (en) * | 2016-02-29 | 2020-04-28 | Invensas Corporation | Correction die for wafer/die stack |
| KR102724620B1 (ko) * | 2019-11-19 | 2024-11-01 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
| GB2589329B (en) * | 2019-11-26 | 2022-02-09 | Plessey Semiconductors Ltd | Substrate bonding |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07112041B2 (ja) * | 1986-12-03 | 1995-11-29 | シャープ株式会社 | 半導体装置の製造方法 |
| JPH04258125A (ja) * | 1991-02-13 | 1992-09-14 | Nec Corp | 半導体装置 |
| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
| US6097096A (en) * | 1997-07-11 | 2000-08-01 | Advanced Micro Devices | Metal attachment method and structure for attaching substrates at low temperatures |
| US6232219B1 (en) * | 1998-05-20 | 2001-05-15 | Micron Technology, Inc. | Self-limiting method of reducing contamination in a contact opening, method of making contacts and semiconductor devices therewith, and resulting structures |
| JP2002026056A (ja) * | 2000-07-12 | 2002-01-25 | Sony Corp | 半田バンプの形成方法及び半導体装置の製造方法 |
| DE10118422B4 (de) * | 2001-04-12 | 2007-07-12 | Infineon Technologies Ag | Verfahren zur Herstellung einer strukturierten metallhaltigen Schicht auf einem Halbleiterwafer |
| JP3735547B2 (ja) * | 2001-08-29 | 2006-01-18 | 株式会社東芝 | 半導体装置及びその製造方法 |
| US6887769B2 (en) * | 2002-02-06 | 2005-05-03 | Intel Corporation | Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same |
| US6962835B2 (en) * | 2003-02-07 | 2005-11-08 | Ziptronix, Inc. | Method for room temperature metal direct bonding |
| US7307005B2 (en) * | 2004-06-30 | 2007-12-11 | Intel Corporation | Wafer bonding with highly compliant plate having filler material enclosed hollow core |
| EP1732116B1 (en) * | 2005-06-08 | 2017-02-01 | Imec | Methods for bonding and micro-electronic devices produced according to such methods |
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2006
- 2006-01-25 US US11/339,132 patent/US7579258B2/en active Active
- 2006-03-06 US US11/368,720 patent/US7514340B2/en active Active
- 2006-12-07 CN CN2006800518156A patent/CN101496166B/zh active Active
- 2006-12-07 WO PCT/US2006/061737 patent/WO2007100404A2/en not_active Ceased
- 2006-12-07 JP JP2008552305A patent/JP5138611B2/ja active Active
- 2006-12-20 TW TW095147984A patent/TWI415216B/zh active