JP2009514114A5 - - Google Patents

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JP2009514114A5
JP2009514114A5 JP2008538127A JP2008538127A JP2009514114A5 JP 2009514114 A5 JP2009514114 A5 JP 2009514114A5 JP 2008538127 A JP2008538127 A JP 2008538127A JP 2008538127 A JP2008538127 A JP 2008538127A JP 2009514114 A5 JP2009514114 A5 JP 2009514114A5
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memory
bit
blocks
specific
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JP5060487B2 (ja
JP2009514114A (ja
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JP2008538127A 2005-12-30 2006-12-11 ダイナミックメモリサイジングのレイテンシを最適化する方法、システムおよびプログラム Expired - Fee Related JP5060487B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/323,259 2005-12-30
US11/323,259 US20070156992A1 (en) 2005-12-30 2005-12-30 Method and system for optimizing latency of dynamic memory sizing
PCT/US2006/047364 WO2007078724A2 (en) 2005-12-30 2006-12-11 Method and system for optimizing latency of dynamic memory sizing

Publications (3)

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JP2009514114A JP2009514114A (ja) 2009-04-02
JP2009514114A5 true JP2009514114A5 (https=) 2011-09-08
JP5060487B2 JP5060487B2 (ja) 2012-10-31

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JP2008538127A Expired - Fee Related JP5060487B2 (ja) 2005-12-30 2006-12-11 ダイナミックメモリサイジングのレイテンシを最適化する方法、システムおよびプログラム

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US (1) US20070156992A1 (https=)
JP (1) JP5060487B2 (https=)
KR (1) KR20080080586A (https=)
CN (1) CN101356508B (https=)
DE (1) DE112006002835B4 (https=)
TW (1) TWI336437B (https=)
WO (1) WO2007078724A2 (https=)

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