JP2009510724A - Photovoltaic device manufacturing system and method - Google Patents

Abstract

Dies for photovoltaic cells can be manufactured using patterned areas that substantially cover the usable surface area of the crystalline workpiece. A plurality of bars can be etched into the workpiece to extend substantially the entire length of the workpiece. These bars can then be diced to form a die having a width substantially equal to the thickness of the workpiece and an edge ratio of about 20: 1 or less. Such a process can maximize the conversion area, thereby extracting more energy from a given amount of photovoltaic conversion material. Contacts can be placed on opposite edges of the die to form photovoltaic cells, and in some embodiments, can function regardless of orientation within the solar panel.

Description

(Cross-reference of related applications)
This application is a priority of US Provisional Patent Application No. 60 / 720,084 filed on September 23, 2005 and US Provisional Patent Application No. 60 / 726,520 filed on October 13, 2005. Claiming the benefits, each of which is incorporated herein by reference.

(Technical field)
The present invention relates to a photovoltaic device and a method for manufacturing and assembling the device.

  Photovoltaic devices are generally semiconductor devices used to convert solar radiation into electrical energy. So far, solar power generation systems have not been widely used for power supply applications, mainly due to the high cost of such systems. This high cost is due in part to the relatively high cost of pure single crystal silicon commonly used in these devices. Much of this silicon is wasted during manufacture, increasing material costs. Furthermore, the cost of the photovoltaic device process itself is not particularly cost effective for many applications. Alternatives to silicon have been studied, but have been found to be less efficient devices and more expensive to manufacture. Prior art solar cell panels are also typically expensive and very time consuming, using machines to accurately assemble and arrange a large number of cells on a substrate. The length of these cells can also cause problems related to in-process jamming, clustering, and corruption.

  Systems and methods according to various embodiments of the present invention are provided for the manufacture and assembly of various photovoltaic devices. In one such embodiment, the photovoltaic cell is formed by depositing a mask layer on a substantially planar piece of crystalline material such as silicon, germanium, or gallium arsenide. The piece of crystalline material is etched to form a plurality of substantially parallel slots. The slots form a plurality of substantially planar bars, each extending along the direction of the bar from one edge to the other edge of the piece of crystalline material. The width of each of the bars is substantially equal to the thickness of the piece of crystalline material. The bar is separated from the piece of crystalline material and diced to form a plurality of substantially rectangular cells.

Each of the bars may have a layer with doping on the opposite side of the bulk doping of the respective bar. The layer can be formed using any suitable process such as POCl ₃ diffusion. Contacts can be formed on the top and bottom of each rectangular cell or on the sides of the cell. In one embodiment, each rectangular cell is formed with a first set of contacts on the first side and a second set of contacts on the second side. At least one of the number and location of each set of contacts is selected to provide an appropriate contact connection to the connection device regardless of the orientation of the respective cell.

  The mask layer may include a non-rectangular pattern region for forming a slot. The mask layer can also include a pattern region for forming the slot, wherein the formed bar is selected to utilize at least 80% of the surface of the piece of crystalline material. In one embodiment, the bar can be diced to have an edge ratio of about 20: 1 or less. Each bar can also have an anti-reflective coating applied thereon and / or texture at least one surface.

  Each diced cell can be placed on a substrate, such as a conductive substrate, a low temperature substrate, and / or a flexible substrate. In one embodiment, additional layers can then be deposited to form a multi-junction device. At least some of the cells on the substrate can be connected using parallel, series, parallel-series, and / or series-parallel connections.

  In one embodiment, the process forms a photovoltaic cell that includes a rectangular crystal die having at least two oppositely doped regions that form a diode. The die can have a width of about 2 mm or less, a length of about 40 mm or less, and a thickness of about 100 μm or less. The cell also includes a pair of contacts disposed on opposite edges of the crystal die, such as on top and bottom edges of the die, or on opposite side edges. The pair of contacts may be part of a first set of contacts on a first edge of the crystal die and a second set of contacts on a second edge of the crystal die, One edge is on the opposite side of the second edge, and the crystal die can be placed in any orientation within a substantially coplanar array of photovoltaic cells.

  In one embodiment, the rectangular die is substantially square. The die can also be formed from a substantially planar piece of <1,1,0> oriented silicon. An anti-reflective coating can be applied on at least one surface of the crystal die and / or at least one surface can be textured.

  The cell can be used, for example, to form a solar module having a substrate including an array of receptacles and a plurality of rectangular photovoltaic cells disposed within the array of receptacles. Each photovoltaic cell can have a width of about 2 mm or less, a length of about 40 mm or less, and a thickness of about 100 μm or less. Each photovoltaic cell can further have a contact on two opposing edges of the photovoltaic cell. The module also includes an interconnect layout that electrically connects the contacts of the plurality of rectangular photovoltaic cells. The contacts can be arranged, for example, at the top and bottom of each photovoltaic cell or at the side edges. The contact may include at least one first contact on a first side edge and at least one second contact on a second edge, wherein the first and second Contacts at different edge positions such that each of the first and second contacts connects to a desired line of the interconnect layout, regardless of the orientation of the photovoltaic cells in the respective receptacles. Is done.

  The interconnect layout can divide the plurality of photovoltaic cells in the array of receptacles into sub-modules. The interconnect layout can also connect the photovoltaic cells in each module in parallel and connect at least some of the submodules in series. The interconnect layout can connect the photovoltaic cells in each module in series and connect at least some of the submodules in parallel. A laminate layer can be used to hold the plurality of photovoltaic cells in the array of receptacles.

  It will be apparent to those skilled in the art that other embodiments are possible in light of the description and drawings contained herein.

  Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

  Systems and methods according to various embodiments of the present invention can overcome the above and other limitations in existing photovoltaic devices and methods of manufacturing devices. The process according to one embodiment utilizes the crystal structure of the material used in the process, which can be converted into photons into electrical energy and various electrical properties, for example, by etching a very thin and small die. It is like a <1,1,0> oriented silicon crystal that incorporates the structure needed to interface to the system. Such oriented silicon crystals are used as described herein to produce strips extending substantially the entire length of the wafer, removing the split bars described below, and then The strips can be diced into square or rectangular cells to produce thin, high aspect cells. In one embodiment, the edge ratio of the rectangular cells is preferably, for example, a length: width of about 20: 1 or less, and in one embodiment, 3: 1 or less. Also, processes according to various embodiments can include quickly assembling these cells on a substrate and incorporating an interconnect layout that allows the die to be assembled in a random orientation. The process is more suitable than existing processes for forming photovoltaic devices, and can be simpler and less expensive.

  Methods of making photovoltaic cells and modules according to various embodiments of the present invention can produce devices with high efficiency per energy conversion area and low cost. In addition, these methods can make maximum use of various materials related to other solar battery manufacturing techniques. Similar methods can be used, including those that focus on simplicity and low cost, and those that can be performed with more complex but low temperature pastes and materials, thereby reducing the number of substrates and materials that can be used. Increase greatly. For example, low temperature substrates can be used with pastes and materials at 300 ° C. or lower.

  In one embodiment, the individual cells are made in a rectangular pattern from <1,1,0> oriented silicon crystals. One embodiment of the photovoltaic cell 102 is shown in the assembly 100 of FIG. The cells formed in this example are symmetrical in front / back and sides / sides so that they are substantially identical when viewed from the front and back. This particular figure shows a bulk material 104 whose thickness is primarily determined by the thickness of the silicon wafer or other material used to form the die. In some embodiments, a thicker than a standard silicon wafer may be desired. The cell 102 has an upper 106 and a lower 108 doped region, as described below. Orientations and directions such as “front”, “back”, “top”, and “bottom” are used merely for convenience and brevity of explanation, and any orientation or orientation requirements It is not intended to imply.

  In a cell according to one embodiment, the top region 106 and the bottom region 108 are phosphorous doped regions, i.e. n-type regions, with a central bulk doped region 104, i.e. p-type region. This figure is not to scale, and each of these regions is generally thin compared to the thickness of bulk silicon 104. In at least some embodiments, the larger the cell, the less efficient and less process it is, so a thicker wafer is preferred, while a thicker wafer also requires a longer etch, which may be desirable. There can be no amount of undercut. In one embodiment, the thickness of the bulk silicon wafer can be on the order of about 1 to 2 mm. Phosphorus doping is only an example, and the apparatus according to various embodiments can be any suitable combination of a first doping type bulk doping layer (or region) and a second doping type emitter doping layer (or region). Can be used. Note that the emitter doping is the opposite of the bulk doping and the emitter doping is present in the shallow emitter layer on the surface of the device.

  As will be described below, a layer of anti-reflective coating 110 is formed around the cell. The antireflective coating can be, for example, a nitride or oxide layer. The lower doped region 108 of this embodiment is an n-type region as formed, but when a layer of aluminum paste 112 having a thickness of 25 to 40 μm is printed on a cell or applied and fired. The paste penetrates the anti-reflective coating 110 and p-type doping, so that the aluminum paste effectively contacts the p-type bulk layer 104 to form a p-type connection, and the n-type doping of the lower layer 108 is effective. Counteract.

  As will be described later, the assembly also includes a lower paste layer 114 such as a silver paste layer having a thickness of 10 to 15 μm and a substrate 116 depending on the situation. On top of the cell 102 is the presence of another layer of paste, such as a 10 to 20 μm thick layer, ie a silver paste with a special anti-reflective coating (ARC) penetration function. The layer penetrates the ARC layer 110 and contacts the upper n-type layer 106. By applying a normal silver paste layer 120 having a thickness of 10 to 20 μm, which does not penetrate ARC, such as a thermoplastic silver paste or solder paste, to the upper part of the assembly, the upper electrode of each cell is applied to the adjacent cell. Can be interconnected. In another embodiment, an insulating paste is applied on the side of the cell and a paste layer 118 is applied on the insulator paste. In another embodiment, the insulating paste is placed at the bottom and periphery of the side of the cell to increase the adhesion between the cell and the substrate assembly. The insulating layer is not designed to have an electrical effect on the cells, but is useful for holding the assemblies more firmly together.

  FIG. 2 shows a portion of the cell array showing the width of the thin silver paste layer 118 with ARC penetration capability (about 300 μm in this example) and the upper silver paste layer or solder paste layer 120 of the cell array. FIG. The reference numbers are carried over between the drawings for ease of understanding and brevity, but are not intended to be construed as limiting the various embodiments.

(First process method)
The process for making such a cell (in this case a rectangular cell) according to one embodiment begins with a <1,1,0> oriented silicon wafer. The silicon can be, for example, high purity, doped with an n-type or p-type dopant, and / or in the form of a wafer having a thickness of 2 mm and a diameter of at least 100 mm (eg, 150 mm). The silicon boule has a wafer plane cut with relatively high precision. According to the specifications of the cutting process, according to various embodiments, it is generally in a range of ± 0.5 °, but can be cut in a range of ± 0.1 °. Since these wafers are aligned and etched with respect to the crystal orientation, a slight bias can result in thinning one side of the cell when the cell is formed, and tight accuracy is desirable. The wafer can be cleaned using a suitable process such as a piranha cleaning process. Further, the wafer can be polished by both surface polishing and edge rounding as required.

  In one embodiment, a silicon nitride mask layer having a thickness of about 2,000 mm is deposited on the entire surface of the wafer. The wafer can then be prepared for photoresist deposition, such as by applying a hexamethyldisilazane (HMDS) primer, so that it functions as an adhesion promoter for the photoresist. The resist can then be applied to the front and back surfaces simultaneously or at different times, and the resist can be rotated on the front and back surfaces of the device. In one embodiment, a jig having a large plate with three pins is used. One of the mask plates is placed on the jig, but the mask plate also has three pins, the wafer plane is aligned on two of the pins, and the wafer edge is on the third pins And thereby align the wafer with the mask. Another mask can then be placed over it, which is located over the pins of the main piece. The jig apparatus has a front mask and a back mask that descend on the front and back surfaces of the wafer so that both surfaces of the wafer can be exposed simultaneously. The front and back surfaces can then be exposed simultaneously so that the wafer can be etched after firing.

  While such a process can be used to form a set of parallel slots on the front and back surfaces of the wafer, in some embodiments, only slots on either the front or back surface of the wafer are used. There is a case. A slot pattern area according to an embodiment is shown in FIG. As can be seen, the slot is not formed from a rectangular region, but from a pattern region 304 formed to utilize substantially all of the material of the workpiece 302 (such as a wafer or ingot). Form. By using a rectangular pattern for a circular workpiece, for example, a considerable amount of workpiece material is wasted. By using a pattern that substantially matches the size and shape of the workpiece, long and narrow slots that extend substantially the entire length of the workpiece are used so that substantially all the material of the workpiece is used. Can be formed. This also significantly increases the surface area generated from the wafer and greatly increases the active surface area that can be obtained for the cell from a single wafer.

  In this embodiment, where the workpiece is a circular silicon wafer, the pattern area for the slot is substantially circular and corresponds to the outer edge of the workpiece. This correspondence allows the majority of the workpiece material to be used for slot formation (and the resulting strip of material). In one embodiment, at least 80% of the workpiece material is used in the patterning region. Since the amount of material used may require enough material to hold the periphery of the wafer in order to provide the framework to hold the workpiece in one piece without breaking, It can depend on the material of the workpiece and the thickness of the workpiece.

  In the pattern region 304, patterns for individual parallel slots can be formed as shown in the enlarged view of a portion of the workpiece 302 in FIG. As shown in the figure, adjacent groups of slots are etched to substantially become the edges of the workpiece. The slots have an opening of 25 μm with a nominal spacing of 120 μm in this example. The resulting bar is then typically about 70 μm or less in thickness after etching through the wafer. In some embodiments, at least one split bar 306, or stabilizer bar, is formed in the wafer during the etching process (such as by changing the mask used to etch the slot). As shown, this split bar 306 can be substantially perpendicular to the individual parallel slots 304. Dividing bars can be formed at regular intervals below the center of the wafer and / or throughout the wafer. These bars divide the wafer into sections so that individual slots do not extend the entire length of the wafer. This not only prevents the individually formed bars from being destroyed, but also reduces the effects of etched slot misalignment. Dividing bars thus reduce the need for accuracy to precisely align long slots to crystal orientation. Further partitioning further reduces the need for tight accuracy.

  In another embodiment, an existing process, such as adding an oxide or nitride layer by using an additional layer of material, followed by etching to create a support for a series of bars, etc. A support structure as in can be formed. It should be noted that forming split bars as part of the slot etching process reduces further steps, materials, and complexity. In addition, the use of a dividing bar formed during the slot etching step helps alleviate difficult accuracy to achieve as described elsewhere herein.

  A potential disadvantage to using a split bar is that a portion of the wafer is not suitable for use in a cell. Etching from one end of the wafer to the other generally tilts somewhat so that a small area (or other spacing) in the center of the wafer is lost. In one embodiment, there are slots that are 25 μm wide. When the formed bar is ultimately cut to form individual cells along the indicated cut line 308, generally the angle of the material formed by etching from the dividing line 306 is the individual cell. The cutting lines 308 are arranged on both sides of the dividing bar so as not to affect any of the final shapes. This further reduces the yield of the wafer.

  Etch the exposed nitride layer to silicon after the front and back surfaces of the device have been patterned for a deep etch process, and the patterned resist has been developed and baked by appropriate development and baking processes Can do. The resist is then removed. The front and back patterns are substantially the same, and the front and back slots are arranged as described above. In another embodiment, a silicon dioxide layer is deposited over the nitride. The oxide layer is etched by wet etching with hydrofluoric acid, and the nitride layer is then wet etched using hot phosphoric acid using the oxide layer as a mask.

  The device can then be deep etched in a wet bath, such as an anisotropic wet etch bath using a solution of 40 wt% potassium hydroxide (KOH) in water. Depending on the situation, isopropyl alcohol can be added to improve the surface quality of the silicon surface. This etch can proceed from one direction to the entire wafer, such as from the wafer front surface, or can be merged in the middle starting from the front and back surfaces of the wafer (using nitride masks on both sides). By starting from both sides, the etching time is shortened and undercutting can be reduced.

  In some embodiments, deep etching is important. Several problems can occur with wet etching when using relatively hot KOH solutions. For example, uneven performance can result in cells with different performance. Furthermore, the front and back surface etches must be arranged to meet narrow tolerances.

  An etching process (which can include any of a plurality of etching processes other than KOH wet etching) can create a plurality of slots through the wafer. The advantage of using substantially square cells instead of elongated strips as in the prior art is that substantially the entire wafer can be used. When using elongated strips that must all be the same size, the usable area of the wafer is substantially square, which means that about half of the circular silicon wafer is wasted in the prior art system. To do. When rectangular cells are used, the strips etched into the wafer can then be diced into individual cells to change their length. The resulting cells can be small, for example, on the order of 40 mm or less in length, in some embodiments 6 mm or less in length, and have an edge ratio of 20: 1 or less. Many existing processes require such a small cell because the pick-and-place tools used to place cells in existing systems require a significant amount of time to assemble the panel of cells. Absent. However, by using a parallel assembly tool as described herein, such a module of cells can be assembled quickly and is economical and practical.

  The formed strip can extend over substantially the entire length of the wafer, leaving only a thin rim around the edge and need only some support structure to hold the strip in parallel. Thereby, the amount of material used can be improved by a factor of two. In one embodiment, over 84,000 square or slightly rectangular cells can be fabricated from a typical 2 mm × 150 mm diameter wafer with an etch pitch of 100 μm.

  FIG. 4 is a diagram illustrating steps of an exemplary method 400 for forming strips used to form photovoltaic cells, including some of the steps described above. In this method, a workpiece of crystalline material is obtained, which material is of high purity and has a selected doping (step 402). The workpiece is oriented based on the known crystal orientation of the material (step 404). At least one mask layer, such as a silicon nitride mask layer, is applied to the front and back surfaces of the workpiece in a pattern that covers substantially the entire workpiece (step 406). A resist material is then applied to the front and back surfaces of the workpiece (step 408). The resist on the front and back surfaces of the workpiece is then exposed and developed to form a set of parallel slots on both the front and back surfaces of the wafer, the slots being substantially from one edge of the workpiece to the other. Extend (step 410). During the etching step, at least one parting line can also be formed as described above. After any necessary development and / or baking, a deep etch can be applied after the mask layer etch to etch the entire workpiece, thereby forming a series of parallel bars in the workpiece. (Step 412). After etching, all remaining resist can be removed (step 414). In a series of further steps for the various embodiments, the narrow area is further processed into a device in which the formation of the photovoltaic device is substantially complete. The bar can then be diced to form strips (step 416).

  Once the strips are formed by deep etching, it may be desirable in at least some embodiments to texture one or both sides of these strips. In one method, a very thin layer of nitride or other masking material is deposited, but this layer is thin enough not to completely cover the underlying silicon and leave many openings. . The isotropic etching of the underlying silicon then creates a cavity in the area under the opening in the mask, thus texturing the silicon surface. Texturing is effective in that it tends to bend incident light, so that the light can take a longer path in the cell and improve the efficiency of the resulting cell. However, texturing can add further costs, which can be commensurate with the amount of improvement obtained.

A POCl ₃ diffusion step or similar process step can be used to form a layer with doping on the opposite side of bulk doping of bulk silicon, thereby building a diode region across the entire surface of the device. This can be found, for example, in the cross-sectional view of FIG. In one embodiment, POCl ₃ and oxygen flow as gases at atmospheric pressure, typically at a temperature of about 800-1150 ° C. By properly mixing this gas for POCl ₃ diffusion, phosphorus can be diffused into the silicon and phosphorous glass (PSG) can be constructed on the surface of the silicon. POCl ₃ diffusion creates different doped regions 106 and 108 in the cell, ie, the front and back surfaces of the cell, or the sidewalls of the strip formed by deep etching. Since POCl ₃ and oxygen can re-grow some oxide (PSG) on the top and bottom surfaces, POCl ₃ diffusion can form glass or glaze on the device, where the contacts It can be removed from the top or bottom of the device being placed. At this point, more diode characteristics can be matched to the device characteristics.

It is important that the original nitride mask be left in place during the POCl ₃ deposition step so that POCl ₃ is not deposited in the narrow area of the cell edge.

To reduce reflection from the surface of the device, it is possible to apply a layer of material designed to be an anti-reflective coating (ie ARC). After KOH or other deep etching, the surface is relatively smooth. When used in applications such as solar cells, some of the light incident on the cell is reflected at the front and back surfaces. These reflections may be undesirable for various applications. One way to reduce the amount of reflection is to deposit an ARC. When using POCl ₃ to form contacts, it is possible to deposit a layer of ARC by appropriate addition of an oxidizing material during or immediately after deposition of POCl ₃ . A typical depth for a dielectric composed essentially of silicon dioxide is 1000A.

  Instead of phosphorous glass (PSG) ARC or silicon dioxide ARC, silicon nitride ARC can be deposited on the surface of the cell. The PSG and remaining nitride can be removed and a 750A layer of silicon nitride can be added at this stage to act as an ARC. Such a nitride ARC can have substantially ideal characteristics, with a reflection loss as low as 1%. Using other reflection-reducing methods, such as flowing different optical index materials into the space between the surface of the cell and other optical interfaces, such as may appear when constructing photovoltaic modules it can.

  The bars or strips can then be diced into individual cells. Since trying to dice the strip into a rectangular cell, or “squibber”, can destroy the strip, a series of additional steps can be taken to prevent damage to the strip. In one embodiment, the structural integrity of the wafer strips can be improved by filling the gaps between the strips with a material such as wax. Waxes such as CrystalBond can be easily removed and “dissolve” at moderate temperatures, and this wax can easily flow into the wafer to fill gaps and cavities. This wax allows the strips to be diced or cut into individual cells without damage. This wax can then be removed in acetone at room temperature, dissolving the CrystalBond and leaving the cell.

  Other waxes can be used but generally require a high temperature heating process in a harmful solvent. Other polymers or flowable materials such as polymers and low melting materials can also be used. Any type of suitable, selectively removable filling can be used to fill the gaps in the deep etched wafer. In other embodiments, the strips can be attached to what is commonly used in the industry to hold wafers, referred to in the industry as “blue tape”. The strips can be diced when they are diced and placed on blue tape, on another adhesive material, or placed between layers of tape. If adhesive material is used on both sides of the strip, it is possible to cut only the material on one side.

(Panel assembly)
Once individual cells are formed, additional process steps can be used to form panels or other photovoltaic devices using the cells. In one embodiment, the assembly fixture has a rectangular grid pattern of raised edges on a flexible substrate. The flexible substrate can be any suitable substrate such as a polyester film, such as Mylar® available from DuPont (Wilmington, DE). The raised edges can be made using epoxy paint, metal, or printed on Mylar. In another embodiment, the fixture is made from a printed circuit board material and the raised areas are plated conductors.

  In another embodiment, a conductive substrate, such as a stainless steel substrate, can be used, such as for a substantially parallel grouping of cells. The conductive substrate can include an insulator that removes the mask in areas where conduction is not desired. Such a substrate can be used when the back surfaces are all connected in parallel.

  In one embodiment, the cell 502 can be placed on the substrate using a dry vibration process. In such a process, the die can be packaged randomly or in strips or lots, as shown in FIG. The top can be dry-flowed. It should be understood that the cells can be flowed to fill the entire grid or a selected section of the grid. The die can be flowed with a small amount of vibration and can flow into the target receptacle in the assembly fixture grid. The surface of the assembly fixing grid can be slightly inclined so that gravity can help the cell flow. Using such a process, large panels of these cells can be assembled quickly and in a relatively inexpensive manner.

  However, conventional dry assembly tools may not be usable for this process. The cells are very thin and have a high surface area to mass ratio and therefore tend to stick to the surface of the assembly jig. The normal rotational movement of the jig is not sufficient to separate the die from the surface. By using an impulse vibration assembly tool that rapidly decelerates the motion at periodic intervals, this adsorption force can be weakened to allow rotational movement of the die, thereby assembling the die into a grid pattern.

  In a process according to one embodiment, individual cells are formed in a panel using sub-modules, but the sub-modules can be of any convenient size, such as from 4 ″ × 4 ″ to about 8 ″ × 9 ″. be able to. The cells can be grouped in parallel and then placed in series to generate any desired voltage. In one embodiment, 4 ″ × 4 ″ cells are formed in parallel to generate approximately 0.5V, or the formed 8 ″ × 9 ″ cells are two 0.5V cells in series. . These are substantially equivalent to two 6 ″ wafers in series as conventionally constructed.

  In an alternative embodiment, multiple cells are connected in series and then a group of these cells are connected in parallel to form a higher voltage array. The advantage of connecting the series groups in parallel is that the loss of the cell usually results in a short circuit connection. If there is a long cell string, such as 20 cells of 0.5V each, the voltage will be 9.5V if one cell is missing from the 10V cell string. However, when the strings are connected in parallel with other strings, the average output of these strings is in the range of 10V to 9.5V. In another embodiment where the large array is 0.5V, a short connection to one cell pulls down the entire array until there is almost no output. Thus, in that sense, a “series-parallel” arrangement has several benefits.

  In this example, borosilicate glass is used as the substrate, although other suitable substrates such as glazed ceramic tiles can be used. Borosilicate has the advantage that its coefficient of thermal expansion is very low (substantially the same as silicon), thereby closely matching the thermal expansion of silicon and glass. The reason for using such glass is to fire some of these pastes and the system must be at a relatively high temperature (such as about 700 ° C.). Other types of glass, such as soda lime glass, begin to flow at low temperatures and have a relatively high coefficient of thermal expansion, so when a cell is attached to conventional glass and the cell is raised to high temperatures, the fixed cell is , Since a considerable force is applied to the cell during cooling, it tends to crack or break.

  Initially, a silver paste layer is deposited on the substrate to form a tabbing paste. When creating the final module, the tabbing conductor can be soldered from one sub-module to the other and interconnected in series by soldering to a silver paste layer. The silver paste layer is placed on the glass and fired at its firing temperature (about 650 to 700 C in one example).

  In one embodiment, a ring of insulating paste is applied in the area under each cell and dried. The pattern of aluminum paste is then applied over the silver paste by printing or the like. While the paste is wet, the substrate is arranged and placed on a die arranged in a grid. The wet paste adheres to the die and removes the die from the assembly jig. This assembly can be dried at low temperatures. The filled dielectric paste that fills the spaces between the cells is then printed primarily in the areas where conductors are printed later. This paste is then dried. A silver paste that can penetrate into the ARC when fired is printed in a thin line at the top of the cell and after drying, the assembly is fired at a high temperature (such as about 700 ° C.).

  At this point, the cell is functioning as an energy conversion device and can be tested.

  In another embodiment, a low temperature silver paste, such as thermoplastic silver or tin-silver solder paste, is printed on the permeable silver paste to connect the top conductor to the adjacent cell and then cured or fired. .

  When diced into individual square or rectangular cells and assembled into sub-modules, cells made from wafers, such as the exemplary wafers described above, are typically 20% efficient, and with full sunshine An output of 67 watts or more can be generated. With substantially the same amount of single crystal silicon material cut into a conventional solar cell wafer, for example, five wafers can provide the same efficiency, generating about 17 watts. This improves the output from the same amount of silicon by a factor of four.

  Another advantage of such a process is that the process steps described above are similar in complexity to the process required for conventional cells, but need only be performed on the wafer. On the other hand, in the conventional method, a similar process must be performed on as many as 20 wafers to obtain a device with the same output. This results in further processing cost savings.

(Second exemplary forming method)
An exemplary process according to another embodiment may produce a photovoltaic cell assembly 600 as shown in FIG. As will be described later, the cell has a bulk layer 602 having an n-type region 606 at the top of the wafer and a p-type region 604 at the bottom. Descriptions such as “upper” and “lower” are used herein for clarity and explanation and should not be construed as limiting the actual orientation of any embodiment. I want you to understand. The cell shown also has a substrate 608 and opposing POCl ₃ layers 610 and 612.

  The process begins with a rectangular wafer, i.e., <1,1,0> oriented silicon. The silicon can be, for example, in the form of a high purity, doped with an n-type or p-type dopant and / or a wafer having a thickness of 2 mm and a diameter of 150 mm. The wafer can be cleaned using a suitable process such as a piranha cleaning process. Spin-on glass (SOG) can be used to create boron-doped SOG contact regions on the wafer. The wafer is placed in a suitable ramp and dwell time, furnace or diffusion oven, as is known in the art, and then SOG is used, such as using a Buffered Oxide Etch (BOE) solution. It can be taken out of a furnace that can be removed by etching. BOE etching is typically initiated within 30 minutes after the hard bake of the wafer is complete. The resistivity of the wafer sheet can then be measured. A similar process can be used to create phosphorous doped SOG contact regions in the bottom region of the wafer by subsequent firing and etching steps. The resistivity of the diffusion layer and the characteristics of the diode (via the wafer) can then be measured. Since there are two oppositely doped regions on the two opposite sides of the bulk silicon, the diode characteristics can be measured through the wafer.

  The SOG phosphorus on the bottom of the wafer can be the antipolar doped region relative to the SOG boron region. In one embodiment, both SOG regions can be spun simultaneously or substantially simultaneously. The furnace can then be driven simultaneously for the two SOG regions. While such a method can save time and cost, it can lead to some contamination problems to be addressed.

  Crystalline silicon has a relatively low base resistivity, but the contact regions formed at the top and bottom of a thin silicon wafer can have a lower resistivity. In one embodiment, the resistivity of the contact region is in the range of a few ohms per unit area, while existing systems can only obtain tens of ohms per unit area. Since a small contact is used that extends over a large area of the substrate device, such as a small metal device connected to a wide doped contact, a lower resistivity contact is required in the doped area.

  A nitride layer can be deposited on each side of the device. The wafer can then be prepared for photoresist deposition, such as by applying a hexamethyldisilazane (HMDS) primer, so that it functions as an adhesion promoter for the photoresist. The resist can then be spun on the surface of the wafer. The pattern creating the via is etched through the top nitride and exposed in the top resist. Although this pattern is transferred to the nitride, the nitride etch extends through the entire nitride, and more typically through 1/2 the thickness of the nitride. A similar via pattern is exposed and etched on the back side of the wafer, but the bias lot 702 is arranged between slots created on the top of the wafer, as shown in the side view 700 of FIG. Also, nitride etching is performed only on portions that extend through the wafer, although a nitride layer is still required. As in the embodiments described above, an oxide layer can be deposited over the nitride layer to allow the wet etching process to transfer the resist pattern to the nitride layer.

  The top of the device can then be patterned for a deep etch procedure, and the patterned resist is baked with a suitable baking pattern. The exposed top nitride layer can be etched down to silicon, followed by removal of the resist. A similar procedure can be used on the bottom of the wafer, where the wafer is prepared for resist deposition using a solvent-based priming procedure, such as the HMDS priming procedure, and then the resist is moved over the surface of the apparatus. Spinned and the bottom of the device is patterned for deep etching. The resist can be baked and the bottom nitride layer is etched down to silicon. The resist can then be removed.

  In a process according to another embodiment, the resist can be applied to the top and bottom of the wafer and the patterning is performed substantially simultaneously. For example, the wafer can be placed in a jig apparatus having a mask that can be processed at the top and bottom so that both sides are exposed simultaneously. The resist can be developed before baking. Such a process can be used for both via etch patterns and deep etch patterns.

  The device can then be deep etched in a wet bath, such as an anisotropic wet etch bath using a solution of 40 wt% potassium hydroxide (KOH) in water. This etching can proceed from one direction, such as the front surface of the wafer, to the entire wafer, or can be merged in the middle starting from the front and back surfaces of the wafer (using nitride masks on both sides). By starting from both sides, the etching time is shortened and undercutting can be reduced.

  In some embodiments, deep etching is important. Several problems can occur with wet etching when using relatively hot KOH solutions. For example, uneven performance can result in cells with different performance. Furthermore, the front and back surface etches must be arranged to meet narrow tolerances.

  An etching process (which can include any of a plurality of etching processes other than KOH wet etching) can create a plurality of slots throughout the wafer. An advantage of using substantially square cells instead of elongated strips as in the prior art is that substantially the entire wafer can be used. When using elongate strips that are all the same size, the usable area of the wafer is substantially square, meaning that about half of the circular silicon wafer is wasted in the prior art. . When rectangular cells are used, the strips etched into the wafer can then be diced into individual cells to change their length. Thus, these strips can extend over substantially the entire length of the wafer, leaving only a thin rim around the edge and need only some support structure to hold the strips in parallel. Thereby, the amount of material used can be improved by a factor of two. In one embodiment, over 84,000 square or slightly rectangular cells can be fabricated from a typical 2 mm × 150 mm diameter wafer with an etch pitch of 100 μm.

As described above, the texturing process can be used to reduce reflections. A POCl ₃ diffusion step or similar process step can be used to form a layer with doping on the opposite side of bulk doping of bulk silicon, thereby building a diode region across the entire surface of the device. POCl ₃ diffusion creates different doped regions within the cell, ie, the front and back surfaces of the cell, or the sidewalls of the strip formed by deep etching. Since POCL can re-grow the top and bottom oxides, POCl ₃ diffusion can form glass or glaze on the device, from the top or bottom of the device where the contacts are located. Can be removed. At this point, more diode characteristics can be matched to the device characteristics.

As mentioned above, PSG with POCl ₃ diffusion can be designed to create an ARC layer. Alternatively, PSG can be removed and an equivalent thickness of thermal oxide or other material can be transferred to form an ARC.

  The nitride remaining in the bias lot can then be etched, such as by using the hot phosphoric acid described above. The nitride is etched down to silicon. This etch can also remove any excess nitride in the nitride deep etch mask.

  In one embodiment, the metal contacts are screen printed on the top and bottom of the wafer and arranged and printed in a bias lot. The p-doped contact region can be printed with aluminum or silver or a silver / aluminum combination paste. The n-doped contact region can be printed with silver paste.

  In another embodiment, the metal contacts are printed as part of the assembly process. In yet another embodiment, the n-doped contact region vias are not patterned and etched. Instead, a silver paste that can be fired through the nitride layer is used to contact the underlying heavily doped contact region.

In yet another embodiment, the p-doped contact region vias are not patterned and etched. Instead, an aluminum or aluminum / silver combination paste that can be fired through the nitride layer is used to contact the underlying heavily doped contact region. When the front / back diode regions are formed using the POCl ₃ step, the device may be short-circuited. In this paste step, care should be taken that the paste does not flow into the region where the POCl ₃ is applied. Must.

  Once the contact areas are formed, the strips can be diced into individual cells as described above. The panel can then be formed as described above. For example, one embodiment of a process that uses contacts with both metal contacts printed on the wafer prior to dicing provides the advantage that a subsequent panel assembly process can be used that requires only low temperatures for processing. It is. This allows more types of substrates, such as plastic, to be used.

  Different classes of substrates can be used to support the cells, such as thin flexible substrates and harder, relatively thick substrates. These hard substrates can be, for example, acrylic sheets from 1/16 "to about 1/4" cut to the size of the finished panel. A thin and flexible material can be placed in a subassembly that can have a front and / or backside to support and protect the assembly. This can be an advantage in certain applications with flexible devices.

  The separated cells are assembled on the assembly fixing grid as described above. Separately, the substrate is first printed with a pattern of insulator lines such as epoxy paint. A pattern of conductor lines is then printed between the slightly thicker insulator lines using, for example, a low temperature thermoplastic silver paste or an epoxy silver paste. The insulator lines prevent the conductor lines from flowing out of each other and also form a stopper when the cell is placed over the conductor. While the conductor paste is still wet, the substrate is placed on an assembly fixture grid with assembled cells. The wet paste can stick to the cell and transfer the cell to the substrate. The paste is then cured or dried.

  In another embodiment, a further step of printing a small spot of thermoplastic or epoxy silver paste is used to print on the cell at the via edge and connect the contact area on the cell to the underlying metal interconnect line. Secure.

(Third exemplary forming method)
In a process for forming a cell according to another embodiment, the cell is fabricated in a symmetrical square or rectangular pattern from a crystalline material, such as a <1,1,0> oriented silicon crystal. An example of the photovoltaic cell 800 is shown in FIG. The front / back and side / side surfaces are symmetrical so that the cells of this example are substantially identical when viewed from the front and back. This particular scene shows a bulk material 802 whose thickness is primarily determined by the thickness of the silicon wafer or other material used to form the die. In some embodiments, a thicker than a standard silicon wafer may be desired. Cell 800 has an upper 804 and lower 806 doped region and a plurality of contact regions 808, 810, and 812, as described below.

  In a cell according to one embodiment, the upper region 804 is a boron doped region and the lower region 806 is a phosphorous doped region. This figure is not to scale, and each of these regions is generally thin compared to the thickness of bulk silicon 802. In at least some embodiments, larger cells are more efficient and require fewer processes, so thicker wafers are preferred, but longer wafers also require longer etching, resulting in undesirable amounts. Can cause undercutting. In one embodiment, the thickness of the bulk silicon can be on the order of about 1 to 2 mm.

  The process for making such a cell (in this case a square or rectangular cell) according to one embodiment begins with a <1,1,0> oriented silicon wafer having the characteristics described above. The wafer can be cleaned using a suitable process such as a piranha cleaning process. Spin-on glass (SOG) can be used to create a boron-doped SOG contact region on the wafer. The wafer is placed in a suitable ramp and dwell time, furnace or diffusion oven, as known in the art, and then the SOG can be etched away, such as by using a buffered oxide etch (BOE) solution. Can be removed from the furnace. BOE etching is typically initiated within 30 minutes after the hard bake of the wafer is complete. The resistivity of the wafer sheet can then be measured. A similar process can be used to create phosphorous doped SOG contact regions in the bottom region of the wafer by subsequent firing and etching steps. The resistivity of the diffusion layer and the characteristics of the diode (via the wafer) can then be measured. Since there are two oppositely doped regions on the two opposite sides of the bulk silicon, the diode characteristics can be measured through the wafer.

  The SOG phosphorus on the bottom of the wafer can be the antipolar doped region relative to the SOG boron region. In one embodiment, both SOG regions can be spun simultaneously or substantially simultaneously. The furnace can then be driven simultaneously for the two SOG regions. While such a method can save time and cost, it can lead to some contamination problems to be addressed.

  Crystalline silicon has a relatively low base resistivity, but the contact regions formed at the top and bottom of a thin silicon wafer can have a lower resistivity. In one embodiment, the resistivity of the contact region is in the range of a few ohms per unit area, while existing systems can only obtain tens of ohms per unit area. Since a small contact is used that extends over a large area of the device, such as a small metal device connected to a wide doped contact, a lower resistivity contact may be required in the doped area.

  A nitride layer can be deposited on each side of the device. The wafer can then be prepared for photoresist deposition, such as by applying a hexamethyldisilazane (HMDS) primer, so that it functions as an adhesion promoter for the photoresist. The resist can then be spun on the surface of the device. The top of the device can be patterned for deep etching procedures, and the patterned resist is baked with a suitable baking pattern. The exposed top nitride layer can be etched down to silicon, followed by removal of the resist. A similar procedure can be used on the bottom of the wafer, where the wafer is prepared for resist deposition using a process such as a HMDS priming procedure, and then the resist is spun on the surface of the apparatus, The bottom of is patterned for deep etching. The resist can be baked and the bottom nitride layer is etched down to silicon. The resist can then be removed.

  In a process according to another embodiment, the resist can be applied to the top and bottom of the wafer and the patterning is performed substantially simultaneously. For example, the wafer can be placed in a jig apparatus having a mask that can be processed at the top and bottom so that both sides are exposed simultaneously. The resist can be developed before baking.

  The apparatus can then perform deep etching in a wet bath, such as an anisotropic wet etch bath using a solution of 40 wt% potassium hydroxide (KOH) in isopropyl alcohol. Tend to slow down. This etching can proceed from one direction, such as the front surface of the wafer, to the entire wafer, or can be merged in the middle starting from the front and back surfaces of the wafer (using nitride masks on both sides). By starting from both sides, the etching time is shortened and undercutting can be reduced.

  In some embodiments, deep etching can be important. Several problems can occur with wet etching when using relatively hot KOH solutions. For example, uneven performance can result in cells with different performance. Furthermore, the front and back surface etches must be arranged to meet narrow tolerances.

  An etching process (which can include any of a plurality of etching processes other than KOH wet etching) can create a plurality of slots throughout the wafer. An advantage of using substantially square cells instead of elongated strips as in the prior art is that substantially the entire wafer can be used. When using elongated strips that must all be the same size, the usable area of the wafer is substantially square, which means that about half of a circular silicon wafer is wasted in the prior art. means. When rectangular cells are used, the strips etched into the wafer can then be diced into individual cells to change their length. Thus, these strips can extend over substantially the entire length of the wafer, leaving only a thin rim around the edge and need only some support structure to hold the strips in parallel. Thereby, the amount of material used can be improved by a factor of two. In one embodiment, over 84,000 square or slightly rectangular cells can be fabricated from a typical 2 mm × 150 mm diameter wafer with an etch pitch of 100 μm.

  Once the strip is formed in the wafer as a result of deep etching, it is desirable in at least some embodiments to texture at least one of the sides of the strip. After KOH or other deep etching, the surface is relatively smooth. When used in applications such as solar cells, some of the light incident on the cell is reflected at the front and back surfaces. These reflections may be undesirable for various applications. One way to reduce the amount of reflection is to texture at least one of the surfaces. In one method, a layer such as a thin layer of nitride or other masking material is deposited and then wet etched away for texturing. However, texturing can add further costs, which can be commensurate with the amount of improvement obtained. Other methods can be used to reduce reflections, such as flowing material into the space between the cell surface and other optical interfaces.

  A POCL diffusion step or similar process step can be used to form a layer with doping on the opposite side of bulk doping of bulk silicon, thereby building a diode region across the entire surface of the device. This can be found, for example, in the cross-sectional view 900 of FIG. POCL diffusion creates different doped regions 902 in the cell, ie, the front and back surfaces of the cell, or the sidewalls of the strip formed by deep etching. Since POCL can re-grow some oxide on the top and bottom surfaces, POCL diffusion can form glass or glaze on the device, which can be on top of the device where the contacts are located or Can be removed from the bottom. At least one redrive step can be used, as is known in the art, to dope to the desired depth and reduce crystal defects. The redrive step can be performed by dipping in a furnace to passivate the exposed areas of the wafer, or can be combined with a dry or wet thermal oxidation step. This can help minimize crystal defects. At this point, more diode characteristics can be matched to the device characteristics.

  A mask, such as a shadow mask, can be used to form the contact area for the device. A shadow mask is a pattern in a material such as silicon or other metal in which openings, trenches, or other patterned features are formed. The shadow mask can be lowered to the top and / or bottom of the device. The shadow mask can be used in conjunction with an etching process such as sputter etching to remove insulators such as thermal oxide under the open area of the mask. A metal such as aluminum can be deposited on the top and bottom of the device to form contact areas 808, 810, and 812 using a shadow mask. In addition, a combination of metals such as aluminum and Cr / Ni can be used on one side of the apparatus.

  Once the contact areas are formed, the strips can be diced into individual cells. Since attempting to dice the strip into a square cell, or “squibber”, can destroy the strip, a series of additional steps can be taken to prevent damage to the strip. In one embodiment, the structural integrity of the wafer strips can be improved by filling the gaps between the strips with a material such as wax. Waxes such as CrystalBond can be easily removed and “melted” at moderate temperatures, and this wax can easily flow into the wafer and fill the cavities. With this wax, the strips can be diced into individual cells without damage. The wax can then be removed in acetone at room temperature. Other waxes can be used but generally require a high temperature heating process in a harmful solvent. Other polymers or flowable materials such as polymers and low melting materials can also be used. Any type of suitable, selectively removable filling can be used to fill the gaps in the deep etched wafer. In other embodiments, the strips can be attached to what is commonly used in the industry to hold wafers, referred to in the industry as “blue tape”. The strips can be diced when they are diced and placed on blue tape, on another adhesive material, or placed between layers of tape. If adhesive material is used on both sides of the strip, it is possible to cut only the material on one side.

  In one embodiment, at least one notch can be cut when dicing the strip. These notches can help ensure the desired alignment of the die in the final panel or device. In other embodiments, orientation is not critical and notches are not required.

(Further assembly process)
Once the cell is formed, additional process steps can be used to form a panel or other photovoltaic device using the cell. In one embodiment, the cell is mixed with a fluid and a slurry of the cell and fluid is flowed over the substrate. The substrate can be any suitable substrate, such as a transparent plastic, with a recess stamped to fit into the cell. Different classes of substrates can be used to support the cells, such as thin flexible substrates and harder, relatively thick substrates. These rigid substrates can be, for example, 1/8 "or 1/4" acrylic sheets cut to the size of the finished panel. A thin and flexible material can be placed in a subassembly that can have a front and / or backside to support and protect the assembly. This can be an advantage in certain applications with flexible devices.

  A substrate ready to receive a cell can have a plurality of features such as slots or recesses formed therein. These slots or recesses can be made by stamping, using frit or thin insulation, or using conductors / interconnects, and can create a frame for the cell. For example, as shown in FIG. 10, a substantially square recess can stamp a ribbon to hold the cells in the array 1000. Also, the slot can be a vertical column or a column perpendicular to the surface of the substrate, and the devices can be stacked on top of each other as the material flows. For example, the slot can be 100 mm long and 2 mm wide, and a die with dimensions of 2 mm × 4 mm can be stacked in this slot. In this case, the die can only be placed so that the long axis of the die matches the long axis of the slot. The dies can be stacked one on top of each other until the slot is full. In another example, the slots can be 100 mm long and 4 mm wide, and the dies can be stacked so that the long axis of the die and the long axis of the slot can be aligned. It is also possible to match the short axis of the die and the long axis of the slot, thereby forming an unnecessary gap. In such situations, additional mechanisms can be used to move the die alignment to a suitable orientation. The substrate can also have a large opening through which cells can be poured and filled by stacking.

  The frame surrounding the die can be made of a material that reflows and flattens when heated. The space between the frame and the die can then be reduced, thereby gripping and securing the die in place. For example, a deformable material can be deposited on the substrate and used as the edge of the slot. After the dies are poured into these slots, the slot edges can be heated to soften the ridge material and the material can reflow around the dies. This ridge can also be expanded, further fixing the cell in place. There are other ways to load multiple dies, which are not described herein, but are known to those skilled in the art or will be apparent in light of the description herein.

  The fluid self-assembly process can then place most, if not all, of the cells in available recesses in the ribbon. The methods and materials used in many fluid assembly systems are known in the art as described in Smith et al., US Pat. No. 6,623,579, entitled “Methods and Apparatus for Fluid Self Assembly”. Yes, which is incorporated herein by reference.

  In another embodiment, the cell can be placed on the substrate using a dry vibration process. In such a process, the dies can be packaged randomly or in strips or lots, and can be dry-flowed over the substrate with a small amount of vibration and flow into a target receptacle in the substrate. The surface of the substrate can be slightly inclined so that gravity can help the cell flow. Using such a process, large panels of these cells can be assembled quickly and in a relatively inexpensive manner.

  In other embodiments, a combination of fluid and vibration processes can be used to place the cell on the substrate. When using fluid assembly, the fluid can be removed and the cell / substrate can be dried, as is known in the art. The fluid can be a simple fluid, such as deionized water, or have any of a number of other desired properties. For example, the fluid may have surfactant properties that enhance fluid and cell flow and improve die flow over each other. Also, the recesses in the substrate can be patterned with a material that provides the die with a specific attraction to the location so that when the die enters its location, the die tends to stay in place. .

  The filling process may be separate, where the substrate is a separate panel or fed in rolls, and the substrate is a continuous ribbon of material fed through the process area that feeds the cells. .

  By covering the substrate with a cover sheet having pre-drilled contact vias, the cells can be held in place. If not previously drilled, the holes can be drilled later with a laser or similar means. In some existing systems, a backing is placed over the cells and the perforated holes, but such a process is difficult for prior art long strips and is not possible with lamination rollers or other processes. Components tend to damage long strips, such as by uneven pressure.

  The cell can then have an interconnect pattern 1100 formed, for example, as shown in FIG. Interconnects flow over and adhere to contact vias, such as silk screen printed, ink jet printed, or using some form of conductive paste such as silver epoxy It can be. Other techniques for depositing interconnects, such as using patterned rollers, can be used as prior art.

  The conductive paste can be fired into a flexible but hard form, connecting the cells to a group having a number of parallel cells, as shown in FIG. Some of these groups can be connected in series to increase the ribbon voltage. The ribbon can be finally cut to form a finished ribbon assembly.

  In another embodiment, the substrate may have interconnects already silkscreen printed on the interconnect substrate, such as FR4 printed circuit material, among many other possibilities. A pattern of square or rectangular recesses can be silk-screened over the interconnect to form areas in which square or rectangular cells can flow. The substrate with the cells can then be placed in a chemical bath in which a conductive material is deposited. This conductive material bridges the contacts on the cell and the underlying interconnect. After deposition, the assembly can be washed and dried.

  In another embodiment, solar cells can be assembled using an interconnect matrix. The open weave matrix (which can be similar to a window screen, for example) can be knitted to precise dimensions that substantially match the size of the squibber, for example. Adjusting the opening in the weave to match the size of the squibber can provide a good fit with the squibber and can hold the squibber substantially in place. The matrix can be any suitable interconnect film made of any suitable material that can fit the squibber without damaging or contaminating the squibber. Such a weave can be used as a conductive interconnect and / or as a support structure. In one example, a conductive wire can be used on one axis of the membrane and an insulated wire can be used on the other axis. By using such a method, a large number of squivers can be easily wired in parallel. In another example, two (or more) different materials can be used to allow the squibber to self-align. These materials can be hydrophobic and hydrophilic, respectively, and can have a single axis of symmetry. In another embodiment, the interconnect weave can be made of up to four different materials to provide multiple interconnects for each squibber. By using an open weave as an interconnect, a simple screen print can be made on the back and / or front surface of the squibber to provide additional interconnects, even if only one interconnect is created. Generally, to construct a solar module from individual solar cells, only two interconnects are required.

  When diced into square or rectangular individual cells and assembled into modules, cells made from wafers, such as the exemplary wafers described above, are typically 20% efficient and 67% by full sunshine. Can produce more than watts of output. With substantially the same amount of single crystal silicon material cut into a conventional solar cell wafer, for example, five wafers can provide the same efficiency, generating about 17 watts. This results in a fourfold improvement in output from the same amount of silicon.

  Another advantage of such a process is that the process steps described above are similar in complexity to those required for conventional cells, but can only be performed on the wafer. However, in conventional methods, a similar process must be performed on five wafers to obtain the same equipment. This results in further processing cost savings.

  The main advantage of embodiments is the use of substantially square cells. By placing two contacts on one of the square cells and another on the other, any orientation of the cell in the recess of the substrate can function successfully. Regardless of which direction the die is rotated or inverted, the die always aligns with the contacts with respect to the proper polarity for contacting the interconnect. It is also possible to use only a single interconnect covering all these devices so that this particular contact layout will work no matter how each cell is rotated or flipped. This can greatly simplify the fluid assembly process, for example, simply guide the die into the recess regardless of the orientation of the die.

  In one embodiment, a first set and a second set of spaced side contacts are used to allow a change in cell orientation while still providing a suitable connection. The first set of side contacts are arranged differently than the second set of side contacts, for example, two side contacts on one side face the gap between the three contacts on the other side. Be placed. If there are five contact lines under the cell when placed in the module, the cell can be flipped in either direction, and the contacts will still contact only the appropriate contact lines.

  In other embodiments, the cells can be made with a slightly rectangular structure. For example, structures having an aspect ratio of 1.5: 1, 2: 1, 3: 1, or 4: 1 have particular advantages in various systems and / or applications. However, in this situation, there is no perfect symmetry. These dies must fit in the orientation of the rectangular recesses in the recesses, not simply in any rotation, so that, for example, the self-assembly process is longer than that for square cells Can be complicated. However, in the self-assembly process, the rectangular shape allows the solar cell die to be oriented at 0 ° 1200 ° or 180 ° as shown in FIG. 12 (or 90 ° or 270 ° based on the orientation of the major axis). ) Etc. so that it can be filled with a suitable orientation. Since the die is symmetric with respect to the Z axis, the die can be inverted upside down. Such a method can simplify the interconnection, reduce the number of times the processed wafer is cut, and substantially eliminate the filling problem.

  In some embodiments, the cell is made into the die itself and / or into a recess in the substrate with one or more key slots or one or more protrusions formed of a conductive material or insulator. be able to. The slots can align the contact protrusions to the top and bottom of the die, as shown in Example 1300 of FIG. In this way, the die can be placed in a recess that fits into the slot. The die can be flipped but always has an orientation that matches the key slot. In this embodiment, when the die cannot be mounted in that orientation, it is not necessary to have an interconnect that can contact the top and bottom of the die. In this embodiment, only three central interconnect lines are used.

  Other embodiments may have a plurality of slots and / or protrusions arranged along the edge of the die and a recess in the substrate. These can be symmetric and the dies can be oriented normally or inverted.

(Other crystal materials)
Many examples provided herein are described with respect to a specific orientation of silicon, but are intended to be used in the light of the teachings and suggestions contained herein, as will be apparent to those skilled in the art. It should be understood that there are a number of other materials and orientations that can be made. For example, the cell can be constructed from a material such as germanium. By using such a cell, it is possible to form much more efficient multi-junction cells by depositing multiple layers of different materials. The advantage of the method can be a significant improvement of the process, such as a 20-fold improvement of the process. For example, a wafer having a large surface area can be loaded into a furnace together with a plurality of other wafers, and various gases can be flowed into the furnace to deposit materials and build an apparatus. Currently this is done for individual wafers, each wafer having only a certain specific surface area. In the same slot where a thin wafer is placed, a thick wafer can be placed such that a wafer on the order of 2 mm becomes a cell with a height or width of 2 mm. Such a process will eventually use more gas to fill a larger surface area, but the tool itself can be a smaller tool, less expensive and less expensive. Can be reduced. This results in higher productivity and higher efficiency cells.

(Light concentrator)
A further advantage is obtained when a photovoltaic cell as described above is configured and configured to work with an optical concentrator as is known in the art. For example, a holographic pattern that functions as multiple lenses can be stamped on the side of a transparent plastic substrate opposite the column of square or rectangular cells 1400 shown in FIG. Such concentrators can focus solar radiation onto an array of cell columns. Instead of using an array that covers the entire area, the device can include only a column or linear array 1402 of cells, as shown in FIG. This can reduce the number of required cells and thus reduce the cost of the device. The embodiment of FIG. 14 uses ¼ cell as many cells as needed for the same area of the system without concentrator cells. This concentrator, unlike conventional concentrators that can use Fresnel lenses, can focus solar radiation over a range of angles that the sun has relative to the module. Although the concentrator itself is detrimental, for the example shown, the concentrator efficiency is 75% and the system has an overall silicon utilization of 1 / 12.

  In some embodiments, a photovoltaic material that exhibits a crystalline structure with an etchant that can be preferentially etched perpendicular to the surface of the material can be used. In some embodiments, a dry etch process such as a Bosch silicon etch process can be used to cut the wafer into segments. In some embodiments, a laser can be used to cut the photovoltaic material into segments. In some embodiments, a high pressure fluid narrow jet may be used to cut the photovoltaic material into segments.

  It should be appreciated by those skilled in the art that in view of the above description, it will be apparent that there are multiple variations of the above-described embodiments. Accordingly, the present invention is not limited to the specific embodiments and methods of the invention described herein with the figures. Rather, the scope of the present invention is limited by the following claims and their equivalents.

FIG. 1 is a diagram illustrating an assembly of photovoltaic cells according to an embodiment of the present invention. FIG. 2 is a diagram illustrating an array of photovoltaic cells according to one embodiment of the present invention. FIGS. 3A and 3B are diagrams illustrating slot patterns that can be used in accordance with one embodiment of the present invention. FIGS. 3A and 3B are diagrams illustrating slot patterns that can be used in accordance with one embodiment of the present invention. FIG. 4 is a diagram illustrating steps of a cell formation method that can be used in accordance with an embodiment of the present invention. FIG. 5 is a diagram illustrating a grid for arranging strips according to an embodiment of the present invention. FIG. 6 is a diagram illustrating an assembly of photovoltaic cells according to an embodiment of the present invention. FIG. 7 illustrates via etching according to one embodiment of the present invention. FIG. 8 is a front view of a photovoltaic cell according to an embodiment of the present invention. FIG. 9 is a side view of two cells incorporated in a substrate with overlaid interconnects, according to one embodiment of the present invention. FIG. 10 is a diagram illustrating an example of an array of 4 × 4 cells with interconnects according to an embodiment of the present invention. FIG. 11 is a front / side view of the cell of FIG. 7 in one possible orientation with a set of overlaid interconnects and potentials for each line, according to one embodiment of the present invention. FIG. 12 is a diagram illustrating a set of three cells in a vertical column with each cell having the same orientation, according to one embodiment of the present invention. FIG. 13 is a diagram illustrating a single cell and a keyed slot into which the cell is inserted, according to one embodiment of the present invention. FIG. 14 is a diagram illustrating a set of four column cells with interconnections between columns of a photovoltaic cell assembly, according to one embodiment of the present invention.

Claims (34)

A method of forming a photovoltaic cell comprising:
Depositing a mask layer on a substantially planar piece of crystalline material;
Etching into a piece of crystalline material to form a plurality of substantially parallel slots in the crystalline material, the slots forming a plurality of substantially planar bars; Each extending along the direction of the bar from one edge of the piece of crystalline material to the other edge of the piece, the width of each of the bars being substantially equal to the thickness of the piece of crystalline material Equal to and including. Separating the bar from the piece of crystalline material;
The method of claim 1, further comprising: dicing the bar to form a plurality of rectangular cells.   The method of claim 1, wherein the crystalline material is selected from the group consisting of silicon, germanium, and gallium arsenide.   The method of claim 1, further comprising forming a layer having a doping on each of the plurality of bars opposite to the bulk doping of the respective bar. The method of claim 4, wherein forming a layer having doping on the opposite side of the bulk doping of the respective bar comprises performing POCl ₃ diffusion on the respective bar.   The method of claim 2, further comprising forming contacts on the top and bottom surfaces of each rectangular cell.   The method of claim 2, further comprising forming contacts on opposing sides of each rectangular cell.   Forming contacts on opposite sides forms a first set of contacts on the first side and a second set of contacts on the second side of each rectangular cell. Wherein at least one of the number and position of each set of contacts is selected to provide a suitable contact connection to the connection device regardless of the orientation of the respective cell. 8. The method according to 7.   The method of claim 1, wherein the mask layer is used to form non-rectangular regions of parallel slots in the crystalline material.   The method of claim 1, wherein depositing the mask layer comprises depositing the mask layer on a substantially planar piece of <1,1,0> oriented silicon.   The method of claim 1, further comprising dicing the plurality of bars to form a rectangular cell having an edge ratio of about 20: 1 or less.   The method of claim 1, wherein the mask layer includes a patterned region for forming the slot, wherein the resulting bar is selected to utilize at least 80% of the surface of the piece of crystalline material. .   The method of claim 1, further comprising applying an anti-reflective coating on the surface of each bar.   The method of claim 1, further comprising texturing at least one surface of each bar.   The method of claim 2, further comprising disposing each rectangular cell on a substrate.   The method of claim 15, wherein the substrate is at least one of a conductive substrate, a low temperature substrate, and a flexible substrate.   16. The method of claim 15, further comprising depositing additional layers to form a multi-junction device.   16. The method of claim 15, further comprising connecting at least a portion of the cells by a method selected from a parallel, series, parallel-series, and series-parallel connection. A rectangular crystal die comprising at least two oppositely doped regions forming a diode, the die having a width of about 2 mm or less, a length of about 40 mm or less, and a thickness of about 100 μm or less; A crystal die,
A photovoltaic cell comprising: a pair of contacts disposed on opposing edges of the crystal die.   20. The photovoltaic cell of claim 19, wherein the pair of contacts are disposed on one of the top and bottom edges of the die or on the opposite side edges of the die.   The pair of contacts is part of a first set of contacts on the first edge of the crystal die and a second set of contacts on the second edge of the crystal die, the first edge 20. Opposite to the second edge, the crystal die can be placed in any orientation within a substantially coplanar array of photovoltaic cells. Photovoltaic cell.   The photovoltaic cell of claim 19, wherein the rectangular crystal die is substantially square.   20. The photovoltaic cell of claim 19, wherein the rectangular crystal die is formed from a substantially planar piece of <1,1,0> oriented silicon.   The photovoltaic cell of claim 19, further comprising an anti-reflective coating on at least one surface of the crystal die.   The photovoltaic cell of claim 19, wherein at least one surface of the crystal die is textured. A substrate including an array of receptacles;
A plurality of rectangular photovoltaic cells disposed within the receptacle array, each photovoltaic cell having a width of about 2 mm or less, a length of about 40 mm or less, and a thickness of about 100 μm or less. Each photovoltaic cell further comprises a photovoltaic cell having contacts on two opposite edges of the photovoltaic cell;
An interconnect layout for electrically connecting the contacts of the plurality of rectangular photovoltaic cells.   27. The solar module of claim 26, wherein the contacts are located at the top and bottom of each photovoltaic cell.   27. The solar module of claim 26, wherein the contacts are disposed on opposing side edges of each photovoltaic cell.   The contacts on the cell include at least one first contact on a first side edge and at least one second contact on a second edge, the first and second Are arranged at different edge positions so that each of the first and second contacts can have a desired line of the interconnect layout regardless of the orientation of the photovoltaic cells in the respective receptacles. The solar module according to claim 28, which is connected to the solar module.   27. The solar module of claim 26, wherein the substrate is at least one of a conductive substrate, a low temperature substrate, and a flexible substrate.   27. The solar module of claim 26, wherein the interconnect layout divides the plurality of photovoltaic cells in the array of receptacles into submodules.   32. The solar module of claim 31, wherein the interconnect layout connects the photovoltaic cells in each module in parallel and connects at least some of the submodules in series.   32. The solar module of claim 31, wherein the interconnect layout connects the photovoltaic cells in each module in series and connects at least some of the submodules in parallel.   27. The solar module of claim 26, further comprising a laminate layer that can be used to hold the plurality of photovoltaic cells in the array of receptacles.

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