KR20140041602A - Ion implantation and annealing for high efficiency back-contact back-junction solar cells - Google Patents

Abstract

Rear-contact rear junction thin-film solar cells are formed on thin-film semiconductor solar cells. Preferably, the thin film semiconductor material comprises crystalline silicon. The emitter region, the selective emitter region, and the back field are formed through an ion implantation and annealing process.

Description

[0001] ION IMPLANTATION AND ANNEALING FOR HIGH EFFICIENCY BACK-CONTACT BACK-JUNCTION SOLAR CELLS [0002] BACKGROUND OF THE INVENTION [0003]

Cross reference of related application

This application claims the benefit of U.S. Provisional Application No. 61 / 490,859, filed on May 27, 2011, the entire contents of which are incorporated herein by reference.

This application is also a continuation-in-part of U.S. Patent Application No. 12 / 774,713, filed May 5, 2010, the entire content of which is incorporated herein by reference.

The present invention relates generally to the field of photovoltaic and solar cells, and more particularly to methods of making thin film solar cells (TFSCs). More specifically, the present invention provides an ion implantation application for fabricating thin film crystalline silicon solar cells (TFSC).

Ion implantation involves implanting ions of a predetermined element into a solid, and is a standard technique used in the fabrication of semiconductor devices. Although implantation of dopant atoms such as phosphorus (P), arsenic (As), boron (B) may be used to form semiconductor junctions, the implantation of oxygen may be performed by a silicon-on-oxide Lt; / RTI > In addition, it is known that crystalline silicon (c-Si) oxide cells have been fabricated using ion implantation to form pn junctions. However, these efforts are directed toward a planar crystalline silicon wafer. In current methods of making thin film crystalline silicon solar cells (TFSC), which are planar or three-dimensional cells, pn junctions are often formed by POCl3-based doping, or phosphorus compound deposition or post-spray- .

After ion implantation of P and B for emitter formation in a p-type or n-type silicon substrate, a suitable annealing treatment is shown to obtain a high efficiency solar cell. However, current ion implantation efforts are limited to flat, thick c-Si wafers (typically > 200 um).

High efficiency c-Si solar cells have been fabricated on ultra-thin wafers up to 45 um by thinning conventional c-Si wafers from bulk silicon ingots or bricks using integrated circuit (IC) packaging techniques. However, this approach is often impractical because of the high cost. C-Si thin film solar cells (TFSC) can be fabricated by depositing a thin layer of c-Si on a suitable substrate or by using other known techniques such as annealing after hydrogen implantation to cause advanced wire sawing or thin wafer separation Can be advantageously manufactured by slicing a c-Si ingot with a thin wafer.

Often, a high performance thin film silicon substrate (TFSS) is fabricated by depositing an epitaxial silicon layer according to a chemical vapor deposition (CVD) process. The solar cell produced in this epitaxial silicon deposition process may be planar or a well-defined structure. In principle, any three-dimensional surface structure is possible for a 3-D cell, but various performance limitations can make a given 3-D structure more advantageous - for example a pyramid or prism-based three dimensional surface aspect.

Current standard techniques for the formation of selective emitters involve several steps. Typically, the entire front side of the p-type wafer is lightly doped using a process that includes a POCl3 based process or post phosphorous spraying anneal. The passivation of the dielectric material is then deposited on the front surface of the silicon substrate. The preferred regions for metallization contact are then selectively opened in these dielectrics, usually by laser ablation or etching gel processes. A second doping process is then performed to selectively dope the localized region with a high concentration of phosphorus. However, such processes are often too long, expensive, and inefficient.

In the case of forming a uniform emitter layer on the TFSS, controlling the dopant profile can provide higher efficiency. In order to maximize current collection from the solar cell, a good 'blue response' is required. This requires that the maximum phosphorus content near the surface be less than 1E21 cm-3 from the surface and the depth of the emitter is preferably in the range of 0.3 to 0.5 um thickness. This has increased the need for solar cells in the solar industry. However, current industrial emitter formation processes, such as POCl3-based doping, phosphosilicate (PSG) deposition, or phosphoric acid spray-on followed by in-line anneal, Phosphorus concentration and depth. Thus, the emitter characteristics are determined solely by the temperature and time used in doping annealing.

In addition, the lifetime of the hydrophobic charge carriers was greatly reduced at a concentration of 1E18 cm < -3 > For maximum blue response, it will appear to be the upper limit of the dopant concentration in the emitter. However, this results in a high emitter sheet resistance, a high series resistance, a low charge rate (FF) and a low current density (Jsc). Thus, a thin, higher doped region near the surface near the surface is desirable. However, the current dopant profile control method is limited.

Therefore, a need for a simplified manufacturing method of forming thin film solar cells is increasing. This method should include an improved method for forming the emitter region, the base region, and the back / front field in the surface region of the thin film solar cell.

Depending on the disclosed subject matter, the application of ion implantation and subsequent annealing activation in the fabrication of thin film crystalline silicon (c-Si) solar cells is then provided to reduce the disadvantages of the prior art methods.

A technical advantage of the disclosed method includes using a combination of passivation and implant annealing processes such as oxidation to obtain high quality surface passivation simultaneously. Another technical advantage includes the use of a field effect to enhance passivation - this can be done by appropriately charging the overlying dielectric with ion implantation.

These and other advantages of the disclosed subject matter, as well as additional novel features, will become apparent from the detailed description provided herein. The intention of the present invention is not to provide a comprehensive description of the subject matter but to provide a brief overview of some of the function of the subject matter. Other systems, methods, features and advantages provided herein will become apparent to those skilled in the art upon review of the following drawings and detailed description. All additional systems, methods, features, and advantages contained within this description are intended to be within the scope of the claims of subsequent applications based on their application.

The features, characteristics and advantages of the disclosed subject matter will become more apparent from the detailed description set forth below when taken in conjunction with the accompanying drawings, in which:
Figures 1A and 1B show a top view and a cross-sectional view, respectively, of an example of a pyramidal three-dimensional thin film silicon substrate (TFSS);
Figures 2A and 2B show top and cross-sectional views, respectively, of an example of a three-dimensional thin-film silicon substrate (TFSS) having prism surface properties;
Figure 3 shows a pyramidal three dimensional thin film solar cell having a standard arrangement of front side and back side contacts;
Figure 4 shows a prism three dimensional thin film solar cell having a standard arrangement of front side and back side contacts;
Figure 5 is a graph showing the optimized dopant profile of a uniform emitter;
Figure 6 shows an ion implantation process for various doping on pyramid three-dimensional TFSS;
Figure 7 shows a slant ion implantation process on a pyramidal three-dimensional TFSS;
Figure 8 shows a pyramidal three dimensional thin film solar cell having an optional front side emitter;
Figure 9 shows a pyramidal three dimensional thin film solar cell having all the back side contacts;
Figure 10 shows a planar thin film solar cell having all the back side contacts;
11A to 11B: [0031] FIG. 11A shows a process flow for forming a reusable template for forming a crystalline thin-film silicon solar cell;
Figures 12A-13D illustrate a process flow for the formation of a front contact crystalline thin film silicon solar cell according to the disclosed subject matter;
Figures 14A-15D illustrate a process flow for forming a back contact crystalline thin film silicon solar cell according to the disclosed subject matter;
Figures 16A-16H illustrate a process flow for forming a back contact flat crystalline silicon solar cell according to the disclosed subject matter;
Figure 17 is a process flow for commercially fabricating all rear contact back junction solar cells using a planar film;
18 is a cross-sectional view of the rear contact / rear junction solar cell structure;
Figure 19 is a modified process flow for the formation of islands (individual) of separate base contacts;
Figures 20-24 are diagrams of the solar cells after the main manufacturing steps of Figure 19;
Figure 25 is a process flow embodiment for forming an optional emitter;
Figure 26 shows a battery pattern with separate isolated bases and emitters;
Figure 27 shows another embodiment of a battery pattern;
28 is a graph showing simulation results of the FSF dopant concentration;
29A-C are cross-sectional views of a solar cell after the FSF formation process step;
30 is a process flow for forming a solar cell having an FSF layer;
Figure 31 is a combined process flow according to the disclosed subject matter;
32 is a process flow according to the disclosed subject matter; And
33 is a diagram of a cross-sectional view of a solar cell formed according to the disclosed subject matter.

The following description is not intended to limit the scope of the present invention, but is for the purpose of illustrating the general principles of the present invention. The scope of the invention should be determined with reference to the claims. In addition, although reference is made to the fabrication of a planar thin film solar cell and a three dimensional thin film solar cell having pyramid and prism surface characteristics, those skilled in the art can apply the principles discussed herein to the manufacture of all structural types of thin film solar cells.

While a particular embodiment is described herein with reference to a particular embodiment, those skilled in the art will be able to apply the principles discussed herein to other regions and / or embodiments. Although other semiconductor materials may be used, the preferred semiconductor material of 3-D TFSS is crystalline silicon (c-Si). Another embodiment uses monocrystalline silicon as the thin film semiconductor material. Other embodiments use multicrystalline silicon, polycrystalline silicon, microcrystalline silicon, amorphous silicon, porous silicon, and / or combinations thereof. Also, the design is applicable to other semiconductor materials that are not limited to germanium, silicon germanium, silicon carbide, crystalline compound semiconductors, or combinations thereof. Additional applications include copper indium gallium selenide (CIGS) and cadmium telluride semiconductor thin films.

Further, in the present application, the terms "front" and "back" are used to denote the position of the metal contact on the solar cell. A front contact solar cell or a frontside contact is located on the side of the solar cell facing the light side. A back contact solar cell or a backside contact is located on the side of the solar cell deviating from light.

Although the present invention describes boron implantation to form phosphorus ion implantation and BSFs of p-type TFSCs to form an emitter, the same principle is applied to P implantation to form B emitter and BSFs of n-type TFSCs to form an emitter .

Although the present invention describes generally P and B implants, respectively, for n and p doping, other elements such as As and Sb may be used for n doping and Al, Ga, In may be used for p doping.

Those skilled in the art will recognize that the disclosed embodiments relate to a wide range of areas other than the specific embodiments described below.

The present invention describes the use of ion implantation techniques in the manufacture of three-dimensional thin film crystalline silicon solar cells (TFSC), including those having pyramidal and prismatic unit cell structures. The present invention also describes the use of ion implantation techniques in the fabrication of planar thin film crystalline silicon (c-Si) solar cells (TFSC). The present invention describes the use of ion implantation to form the emitter region, the selective emitter region, the base region, the selective base region, the back electric field and the front electric field in the TFSC and the application of the ion implantation method to form the pn junction of TFSC.

The present invention also allows the use of ion implantation to independently control the dopant concentration and the depth of the emitter. Dopant profile control, sometimes called emitter profile engineering, is used to maximize solar cell performance, not limited to blue responses, Voc, and current sinking.

1A and 1B illustrate top and cross-sectional views, respectively, of an example of a pyramidal three-dimensional thin-film silicon substrate (TFSS), which may be referred to as a wafer. 1A is a top view of an embodiment of a pyramidal TFSS consisting of a large pyramidal cavity 10 and a small pyramidal cavity 12 on a silicon substrate. 1A is a cross-sectional view of the substrate shown in FIG. 1A, and the substrate 14 shows a small pyramidal cavity 16 and a large pyramidal cavity 18. FIG. It should be noted that the pyramid structure may be flat top and bottom regions or may be angled apex / tips (as shown in FIG. 1B).

Figures 2A and 2B show top and cross-sectional views, respectively, of an example of a three-dimensional thin-film silicon substrate (TFSS) having prism surface properties. 2A is a top view of an embodiment of a prism TFSS comprised of a hexagonal prism structure 20 on a silicon substrate. FIG. 2B is a cross-sectional view of the substrate shown in FIG. 2A, and the substrate 22 shows a hexagonal prism cavity 24. FIG.

One method for forming planar or 3D TFSSs involves using the original thick wafer as the substrate. The substrate may be single crystalline or polycrystalline. In order to obtain a 3-D structure, the substrate surface may be patterned using techniques such as lithography. A porous silicon structure is then formed on the surface. This is followed by epitaxial deposition of silicon of a desired thickness using techniques such as chemical vapor deposition (CVD). The epitaxial silicon layer is then removed from the porous silicon layer by mechanical or chemical methods. This results in a wafer having a desired thickness and a planar or 3-D structure. The exemplary thin film silicon substrate shown in Figures 1 and 2 can be formed using this method.

In one embodiment, the present invention employs a thin film solar cell having a three-dimensional structure in which a preferred structural pattern is formed using a process in the form of a MEMS.

Fig. 3 shows a pyramidal three-dimensional thin-film solar cell having a standard arrangement of the front side (the solar cell side facing the light) and the rear side side located on the surface of the cell. A P-type (P +) base 30, which is often an epitaxial silicon layer, is doped according to an ion implantation process to form an N-type (N +) emitter layer 32 and a p-type (P ++) The emitter metal 38 and base metal 40 are electroplated or electroless plated single or multi-layer high conductivity metallized regions (silver, aluminum, nickel, titanium, cobalt or tantalum) The metal 38 is silver and the base metal 40 is aluminum. Alternatively, the metal layer may be inkjet-dispensed. In addition, the antireflective coating 36 may act as a front side passivation layer provided with a controlled thickness. In this embodiment, the emitter metal contacts are formed as fingers and busbars on a continuous metal line, i. E., 3-D TFSC top surface. However, since the base metal contact is formed on the inverted pyramid top region on the back side of the 3-D TFSS, the base metal contact is the isolated region.

The following describes the formation of an N + emitter of a p-type base c-Si TFSC material. The same procedure can be used to produce a P + emitter of an n-type base c-Si TFSC material. The dopant species may be P, As, and Sb to form the N + emitter of the p-type silicon TFSC, and B, Al, Ga, and In may be used to form the P + emitter of the n- have.

After ion implantation of P and B to form respective emitters in the p-type and n-type silicon, a suitable annealing process is shown to obtain a high efficiency solar cell. The present invention provides similar ion implantation of P and B in combination with a suitable annealing process to form emitters of thin film planar and three dimensional solar cells in p-type and n-type silicon, respectively.

In one embodiment, the ion implantation process for forming a uniform emitter layer 32 and back surface electric field 34 is performed by forming a 3-D thin film c-Si p-type wafer, Doped < / RTI > emitter. The back electric field is formed by implantation of a P-type dopant such as boron. The cell is then completed using standard passivation and metallization techniques.

Figure 4 shows a prism three dimensional thin film solar cell having a standard arrangement of front side (light side) and back side side contact placed on the surface of the cell. A P-type (P +) base 50, often an epitaxial silicon layer, was doped according to an ion implantation process to form an N-type (N +) emitter layer 52. A back surface dielectric 54 serves as a passivation layer. As shown, the emitter metal 58 is silver and the base metal 60 is aluminum. The antireflective coating 56 is an optical coating optical coating applied to the side of the TFSC to reduce reflection.

3, the emitter layer 52 may be formed using phosphorous implantation and the backside dielectric 54 may be formed using boron implantation. The TFSC shown in Figure 4 shows the metal for contacting the backside through a number of localized contacts open to the backside dielectric. The contact resistance of such a contact can be lowered using boron implantation. Further, instead of this localized contact, the back electric field can be formed using boron implantation.

For a uniform emitter layer, higher efficiency can be provided using blanket implant control of the dopant profile. In order to maximize current collection from solar cells, a good 'blue response' is required. This requires that the maximum phosphorus content near the surface be less than 1E21 cm < -3 >, and the depth of the emitter is preferably in the range of 0.3 to 0.5 um. The solar industry then moves to the Shelley Emitter. However, current industrial emitter formation processes, such as POCl3-based doping or PSG deposition or in-line annealing after phosphoric acid spray-on, do not provide control of phosphorus concentration and depth, respectively. The emitter characteristics are determined solely by the temperature and time used for doping annealing. On the other hand, ion implantation provides the ability to fabricate a shelllow junction of desired dopant concentration by controlling the amount of ions and energy. Thus, the use of the disclosed ion implantation process makes it possible to obtain an emitter having a desired surface dopant concentration, profile and depth. In addition, the implanted emitter eliminates the dead layer and other complications that are commonly associated with POCl ₃ -doped emitters.

5 is a graph showing the optimized dopant profile of a uniform emitter at the dopant concentration (atoms / cm < ³ &gt;) over the junction depth. Precise control of these dopant profiles, sometimes referred to as profile engineering, can be enabled using precision techniques such as ion implantation. As shown, the superfine layer (<0.1 um) near the wafer surface has a high dopant concentration (up to 1e21 / cm3) and the remainder of the emitter has a dopant concentration close to 1E18 atoms / cm3.

Alternatively, high efficiency solar cells can be obtained using the 'selective emitter' approach. Current standard techniques for selective emitter formation include several steps. First, the entire front surface of the p-type wafer is lightly doped using a process that includes POCl3-based processes or annealing after spraying phosphorous compounds. The passivation of the dielectric is then deposited on the front surface. Thereafter, the preferred area to be contacted by the metal is selectively opened in such a dielectric, usually using a laser ablation or etching gel. A second doping process is then performed to selectively dope the localized region with a high concentration of phosphorus. However, such processes are often too long and expensive.

FIG. 6 shows an ion implantation process for various doping on a pyramid three-dimensional TFSS 62. FIG. As shown, the pyramid three-dimensional TFSS 62 has an inverted pyramidal cavity wall aligned along the (111) crystallographic plane - hence, theta is about 54.7 degrees. The relative angular orientation of the implanted surface relative to the incoming ion beam is desirable by using an ion implantation process to dope the pyramid three-dimensional TFSS 62, making it possible to obtain various dopings. The region on the 3-D TFSS with the surface perpendicular to the incident ion beam is heavily doped as in region A, forming a lower sheet resistance junction. However, as indicated by region B, the area on the 3-D TFSS that receives ions at the same angle as the (111) inverted pyramidal cavity wall surface is effectively doped with a lighter amount, resulting in a higher sheet resistance junction. (Which is shown to be arranged along the (100) crystallographic plane so that this plane (or any oblique orientation plane) is at an angle? (Angle to the flat horizontal plane - this flat plane is about 54.7 degrees) The concentration is reduced to cos? Of the horizontal plane. After depositing a passivating dielectric such as SiN: H, only selectively heavily doped ledges of region A on top of the 3D TFSS (or fraction thereof) are contacted by metal for emitter contact metallization do. This is an Ag paste that is etched through a passivating dielectric; Creating an opening using laser ablation of the passivating dielectric; Or by using some techniques such as plating-based and / or PVD metal deposition after removal with an etch paste. Thus, an ion implantation process for various doping to form selective emitters on the 3-D structure shown may be used to form a dual-doped emitter junction without the need for a more complex process flow using lithography or screen printing patterning And one-step selective doping.

FIG. 7 illustrates a slant ion implantation process on a pyramid three-dimensional TFSS 64. FIG. This ion implantation process can be used to selectively dope the region surrounding the end / ledge of the three-dimensional surface properties of TFSS 64 (represented by region A). The low doped emitter is first formed uniformly by standard industry techniques or by using a normal implantation direction in the plane of the TFSS 64. [ The slant ion implantation is then used to selectively heavily dope the ends of the structure (region A of FIG. 7), and is then selectively contacted by the metal.

The present invention also begins the implantation of B and P ions to produce a suitable backside field (BSF) of thin film planar and three-dimensional solar cells, respectively, on p-type or n-type silicon.

Current industrial practice to fabricate a backside field (BSF) using Al-paste firing to provide P + layers and to form Al-Si alloys has severe limitations. The p / p + interface is not sharp, but instead scattered - causing low reflectivity to the minority carrier electrons. In addition, the Si / Al-Si interface is scattered, resulting in low optical reflectivity of long wavelength photons. In addition, there are manufacturing problems such as wafer bow resulting from the low conductivity of the Al paste and intimate mixing of the silicon wafer and the thick paste. These problems are eliminated by implanting B ions (and n-type P) of the p-type substrate. As described above for the emitter, the sharp BSF of the desired profile can easily be obtained using the ion implantation method of the present invention.

In order to obtain a uniform doping of the end of the 3-D TFSC or the ledge, the wafer can be rotated during implantation, so that all sides or surfaces of the structure are uniformly doped.

As with the profile engineering described for the emitter, a desired profile of the BSF can be obtained. The structure of 3-D TFSC can be used to obtain selective doping of BSF. The heavily doped tip is then selectively contacted by a back metal such as aluminum.

As in the case of the emitter formation discussed above, slant ion implantation of 3-D TFSC can also be used to obtain selective doping of BSF. The heavily doped end is then selectively contacted by a back metal.

After the formation of the uniformly or alternatively doped BSF and emitter, the implant annealing process can be combined with oxidation to produce a high quality front and back passivation of the cell.

It is known that, if the passivating dielectric has extra positive charge, the passivation on the N + surface can be enhanced. SiN: H, which is commonly used in the solar industry, has a surplus positive charge that can help provide good passivation of the N + surface when properly controlled. Likewise, the dielectric layer passivating the back surface field can be implanted with negatively charged ions to further reduce surface recombination due to field effect.

Further, the ion implantation method of the present invention can be used to obtain a localized opening in the dielectric layer of the metal contact. To this end, the tip or the ledge of the 3-D TFSC is selectively implanted with an ionic species, such as nitrogen, which later delays / slows the growth of the oxide during the thermal oxidation process. During oxidation, passivating oxides grow everywhere except these high, end regions that are selectively implanted. Due to the injection of N a small amount of SiN formation is easily removed in the cleaning sequence comprising HF dilution followed by phosphoric acid etching. This region is then selectively contacted by the metal. At the front, the selectively open area can be selectively in contact with the metal using plating, inkjet or other techniques. This enables optimization of the front metal pattern to improve battery performance. On the back side, this region can be selectively plated or contacted during blanket deposition of aluminum using PVD or evaporation schemes. These localized contact scams allow well-known PERL types and well-known advantages of the cell structure (leads to the well known PERL type of cell structure and with well known performance benefits).

Figure 8 shows a pyramidal three dimensional thin film solar cell having an optional front side emitter. A P-type base 70 and an epitaxial silicon layer are doped according to an ion implantation process to form an N-type (N +) emitter layer 72 and a p-type (P ++) The selective emitter 82 is formed through an oblique ion implantation process. The cell is then completed using standard passivation and metallization techniques to form the emitter metal contact 78 (silver) and the base metal contact 80 (aluminum). Antireflective coating 76 is an optical coating optical coating applied to the surface of the TFSC to reduce reflection. 12A-13D depict a detailed process flow illustrating the formation of the 3D thin film solar cell shown in FIG.

Figure 9 shows a pyramidal three dimensional thin film solar cell having all the back side contacts. An N-type (N +) base 90 and an epitaxial silicon layer are doped according to an ion implantation process to form an N-type (N +) front electric field 92 and a p-type (P +) emitter layer 94. The selective emitter 104 and the selective base 102 are formed through a slant ion implantation process. The cell is then completed using standard passivation and metallization techniques to form the emitter metal 98 (which may be cobalt, copper, or nickel) and the passivation dielectric layer 100. Antireflective coating 96 is an optical coating optical coating applied to the surface of the TFSC to reduce reflection.

Selective emitters 104 are conveniently obtained during blanket implantation of emitter layer 94. An n-type wafer having a pyramid 3-D structure is implanted with boron to form an emitter layer 94 that is lower doped on the sidewalls but is highly doped on a flat surface. The front electric field 92 is obtained by blanket implantation of phosphorus. Figures 14A-15D depict a detailed process flow illustrating the formation of the three dimensional thin film solar cell shown in Figure 9.

Fig. 10 shows a planar thin film solar cell having all the rear side contacts. An N-type (N +) base 110 and an epitaxial silicon layer are doped according to an ion implantation process to form an N-type (N +) front electric field 112 and a P-type (P +) emitter layer 114. Selective emitter 124 and base 122 are formed through an oblique ion implantation process and use a plating metal such as nickel and copper as the contacts. The cell is then completed using standard passivation and metallization techniques to form the base and emitter contact metal and backside passivation dielectric layer 118. The anti-reflective coating 116 and the reflective insulator 120 help increase the light trapping capability of the planar TFSC.

In FIG. 10, a planar backside contact TFSC can be fabricated from planar, thin film c-Si wafers. The N-type material is advantageous in the case of forming a planar back side TFSC by the method of the present invention. The P-type (P +) emitter layer 114 is first fabricated using blanket implantation of the back side of the wafer with boron. The backside passivation dielectric layer 118 is then grown or deposited. The base 122 is fabricated by opening contacts in these dielectrics and then injecting phosphorus. Selective emitter 124 is fabricated by passivating to a dielectric layer, opening the contact and injecting boron. The front field 112 is then obtained using blanket implantation of phosphorus. 16A-16H depict a detailed process flow illustrating the formation of the planar thin film solar cell shown in Fig.

11A is a process flow illustrating the formation of a reusable template for forming a crystalline thin film silicon solar cell (as shown in FIGS. 8 and 9). Figure 11B is a corresponding illustration of the process steps of Figure 11A. 11A is an embodiment of a process flow illustrating the main manufacturing process steps for fabricating an inverted pyramidal silicon template and a three dimensional thin film silicon substrate used in the formation of a thin film silicon solar cell according to the ion implantation method of the present invention. In this embodiment, a template for fabricating an inverted pyramidal solar cell is formed.

The silicon template manufacturing process begins with a single crystal (100) silicon wafer 142. The starting wafer may be circular or rectangular. Step 160 includes forming a thin hard masking layer 144 on the exposed wafer surface. The hard masking layer is used to mask the surface area to be the top surface of the silicon surface area-template, which need not be etched in a later step. Suitable hard masking layers include, but are not limited to, thermally grown silicon oxide and low pressure vapor phase deposited (LPCVD) silicon nitride. Steps 162 and 164 include a photolithography step consisting of photoresist coating, baking, UV light exposure on a photomask, post bake, photoresist development, wafer cleaning and drying. After this step, an array of inverted pyramidal base openings or a pattern on the photomast 146 representing the staggered pattern will be transferred to the photoresist layer. The patterned photoresist layer is used as a soft masking layer for the hard masking layer etch of step 166. [ Step 166 includes further transferring the photoresist pattern to the hard masking layer underneath by chemical etching, such as etching a thin silicon oxide layer with a buffered HF solution. Other wet and dry etching methods known in semiconductor and MEMS wafer processing may also be used. At step 168, the remaining soft masking layer, photoresist layer 150, is removed and the wafer 148 is cleaned. Examples of the photoresist removal process include a wet process such as using an acetone or pyruvate solution (a mixture of sulfuric acid and hydrogen peroxide), and a dry process such as oxygen plasma ashing. Also, at step 168, the wafer is batch loaded into an anisotropic silicon wet etchant such as a KOH solution. Typical etching temperatures range from 50 캜 to 80 캜, and the etching rate ranges from about 0.2 袖 m / min to 1 袖 m / min. TMAH (tetramethylammonium hydroxide) is another anisotropic silicon etching chemical. The KOH or TMAH silicon etch rate depends on the orientation to the crystalline silicon plane. The (111) family of crystallographic planes is a "stop" plane for anisotropic etching of (100) silicon wafers that are etched at a very slow rate and patterned with a hard mask. Thus, the intersection of two (111) or (111) and lower (100) planes produces an anisotropic etch structure of (100) silicon wafers after time-controlled etching. Examples of such structures include V-grooves having a sharp tip cavity bottom (where the (111) face meets) or a small flat cavity bottom (the remaining (100) side) and a pyramid And a cavity. At step 170, the silicon template 154 is ready to be machined.

12A is a process flow showing the formation of an epitaxial silicon cell used for forming a crystal thin film front contact silicon solar cell (as shown in FIG. 8). 12B is an explanatory diagram corresponding to the process flow of FIG. 12A.

In step 180, if the hard masking layer is silicon dioxide, the remaining hard masking layer is removed by the HF solution. The wafer is then cleaned with SC1 (mixture of NH ₄ OH and H ₂ O ₂ ) and SC2 (mixture of HCL and H ₂ O ₂ ) wafer wet cleaning solution and then rinsed through a deionized wafer and hot N _2. Can be dried. The disclosed process produces a silicon template with an inverted pyramidal cavity.

Step 180 marks the beginning of the silicon template reuse cycle. In step 182, a porous silicon layer 192 is formed by electrochemical HF etching on the entire surface of the silicon template. The porous silicon layer will be used as a sacrificial layer for epitaxial silicon layer separation. The porous silicon layer preferably consists of two thin layers with various porosities. The first thin porous silicon layer is an upper layer and is formed first from bulk silicon wafers. The first thin layer preferably has a lower porosity of 10% to 35%. The second thin porous silicon layer is grown directly from the bulk silicon and is below the first thin layer of porous silicon. The second thin porous silicon layer preferably has a higher porosity in the range of 40% to 80%. The upper porous silicon layer is used as a crystalline seed layer for high quality epitaxial silicon growth and the bottom underneath higher porosity porous silicon layer is used as a seed layer for high quality epitaxial silicon growth with a low density between the epitaxial and bulk silicon interfaces Is used to enable TFSS separation due to its less dense physical connections and weak mechanical strength. Alternatively, a single porous silicon layer having a porosity that is gradually increased or gapped from top to bottom may also be used. In this case, the upper portion of the porous silicon layer has a low porosity of 10% to 35%, and the lower portion of the porous silicon layer has a high porosity of 40% to 80%. Prior to epitaxial silicon growth, step 184, the wafer may be grown to form a continuous-seeded seed layer of crystalline silicon on the lower-porosity porous silicon layer (or a portion of the single layer) (At 950 캜 to 1150 캜) within the epitaxial silicon deposition reactor to form a merged structure with relatively large voids in the higher-porosity porous silicon layer (or a portion of the single layer) It can be baked in a hydrogen atmosphere. At step 184, a single crystal silicon epitaxial layer with an n-type base 194 is deposited only on the front side. The bulk base of the epitaxial layer is doped with P-type boron (B ₂ H ₆ ). The thickness of the epitaxial layer is preferably in the range of 5 um to 60 um. Prior to isolation of the epitaxial silicon layer, an enclosing border trench may be fabricated around the active wafer region to enable isolation of the TFSS. The surrounding trenches can be formed by controlled laser cutting, and their depth is preferably in the range of 5 um to 100 um. The trench defines the boundary of the 3-D TFSS to be isolated and initiates separation from the trenched area. The remaining epitaxial silicon layer can be removed by mechanical grinding or polishing of the template edges. At step 186, the epitaxial layer of silicon 200 is separated and divided from the silicon template. The separated epitaxial silicon layer is also referred to as a 3-D thin film silicon substrate (3-D TFSS). The epitaxial layer separation method disclosed in U. S. Patent Application No. 12 / 473,811, titled &quot; substrate release methods and apparatus &quot; is incorporated herein by reference. The 3-D TFSS can be separated from the ultrasonic DI-water bath. Alternatively, in another separation method, the 3-D TFSS can be separated by directly pulling the wafer backside and top epitaxial vacuum chucks (may be released by direct back pulling with wafer backside and top epitaxial vacuum chucked). In another separation method, the epitaxial layer can be separated by directly pulling the wafer back side and upper epitaxial vacuum chucks. Using this method, the porous silicon layer can be completely or partially ruptured. Chucks can use electrostatic or vacuum chucks to protect the wafer. The wafer is first placed on a lower wafer chuck with an upwardly facing TFSS substrate. The lower chuck protects the template side of the wafer, the upper wafer chuck is gently lowered and protects the TFSS substrate side of the wafer. The activated pulling mechanism lifts the upper chuck upwards and the movement can be evenly guided by the slider rails.

In step 188, the separated 3-D TFSS posterior side is removed by a short silicon etch using a KOH or TMAH solution to remove silicon debris and completely or partially remove the quasi-monocrystalline silicon (QMS) layer Lt; / RTI &gt; After removal of the epitaxial silicon layer from the template, the template is cleaned in step 175 by using a dilute wet silicon etching solution such as TMAH and / or KOH and dilute HF to remove the remaining porous silicon layer and silicon particles . The template is then further cleaned by conventional silicon wafer cleaning methods such as SC1 and SC2 wet cleaning to remove possible organic and metallic contaminants. Finally, after proper rinsing with DI water and N ₂ drying, the template was ready for another reuse cycle.

13A is a process flow showing the formation of a front contact crystalline thin film silicon solar cell (as shown in FIG. 8). Fig. 13B is an explanatory diagram corresponding to the process step of Fig. 13A.

13C is a continuation of the process flow of FIG. 13A, which illustrates the formation of a front contact crystalline thin film silicon solar cell (as shown in FIG. 8). Fig. 13D is an explanatory diagram corresponding to the process step of Fig. 13C. Fig.

14A is a process flow illustrating the formation of an epitaxial silicon cell used in forming a back contact crystalline thin film silicon solar cell (as shown in FIG. 9). Fig. 14B is an explanatory diagram corresponding to the process step of Fig. 14A. Fig.

14C is a continuation of the process flow of FIG. 14A showing the formation of an epitaxial silicon cell used in forming a back contact crystalline thin film silicon solar cell (as shown in FIG. 9). Fig. 14D is an explanatory diagram corresponding to the process step of Fig. 14C. Fig.

15A is a process flow illustrating formation of a rear contact crystalline thin film silicon solar cell (as shown in FIG. 9). 15B is an explanatory view corresponding to the process step of Fig. 15A.

Fig. 15C is a continuation of the process flow of Fig. 15A, which illustrates the formation of a rear contact crystalline thin film silicon solar cell (as shown in Fig. 9). 15D is an explanatory diagram corresponding to the process step of Fig. 15C.

16A is a process flow illustrating the formation of a planar back contact crystalline silicon solar cell (as shown in FIG. 10). Fig. 16B is an explanatory diagram corresponding to the process step of Fig. 16A. Fig.

16C is a continuation of the process flow of FIG. 16A showing the formation of a planar back contact crystalline thin film silicon solar cell (as shown in FIG. 10). Fig. 16D is an explanatory diagram corresponding to the process step of Fig. 16C. Fig.

16E is a continuation of the process flow of FIG. 16A showing the formation of a planar back contact crystalline thin film silicon solar cell (as shown in FIG. 10). 16F is an explanatory diagram corresponding to the process step of Fig. 16E.

Fig. 16G is a continuation of the process flow of Fig. 16A showing the formation of a planar back contact crystalline thin film silicon solar cell (as shown in Fig. 10). FIG. 16F is an explanatory diagram corresponding to the process steps of FIG. 16G.

In operation, the disclosed subject matter provides an ion implantation process that forms an emitter region, an optional emitter region, a front electric field, a back electric field, and a base region for the formation of a crystalline thin film silicon solar cell.

The invention further more directly relates to the present application, comprising all back contact, back junction crystal (preferably single crystal) semiconductor (not limited to silicon) solar cells, utilizing laser annealing with characteristic structures and ion implantation. The manufacturing method is further explained. Significantly, the disclosed scope is for illustrative purposes only. In addition, the use of laser and ion implantation techniques has made it possible to form a low temperature passivation layer, minimize electrical shading, increase open circuit voltage (Voc), short circuit current (Jsc) Thereby providing a simpler battery manufacturing process flow. Here, the formation of a separated base region for localization of the p / n junction and the front electric field (FSF) to improve the minority carrier lifetime using laser annealing after ion implantation is disclosed. This technique is well suited for epitaxial silicon deposition or other thin film deposition techniques, such as those obtained using epitaxial silicon deposition or other techniques known in the art, which may have any thickness in the silicon thickness range of a few microns to 100 microns (and more preferably about 5 microns to 50 microns) It is well suited for forming high efficiency rear contact back junctions using crystalline silicon films. In addition, this technique is also useful as a reinforcement plate for a variety of reasons, including but not limited to thin-film battery lamination, during which part of the manufacturing process, particularly solar cells that can not be heated to high temperatures during formation of the surface passivation and anti- .

Herein, the process for the meshing metallization back contact cell, referred to herein as NBLAC cell, is described in PCT Application No. PCT / US10 / 59783, PCT / US10 / 59759 and PCT / US10 / 59748, filed December 9, 2010 and by Mehrdad Moslehi et al. Are described in the same PCT application.

Figure 17 illustrates a process for commercially fabricating all rear contact back junction solar cells using a planar film of crystalline silicon epitaxially deposited on a reusable crystalline silicon template (e.g., a single crystal silicon film thickness from a few microns to about 100 microns) Flow. After the formation of the battery, the thin silicon film is supported on the back plate connecting the interconnections of the modules with the solar cells.

18 is a cross-sectional view of a back contact / rear junction solar cell structure such as that formed by the process described in FIG. 17, and the back plate is not shown for clarity. As shown, all of the rear-contact back-junction solar cells are fabricated on the same side of the silicon substrate (that is, in contact with the interdigitated metal lines that are in contact with each other) using a dielectric contact opening on the underlying metal and silicon substrate The other side or the back side). The efficiency of such a cell is, inevitably, dependent on the dimensions of the base region with smaller dimensions leading to higher efficiency. In all conventional rear contact / rear junction solar cells, the n and p regions form a different stripe. The hydrophobic charge carriers, which are holes in the case of n-type bases, must cross the base region, which can be heavy recombined, as shown in FIG. 18, which represents the hole, hydrophobic charge carriers. This phenomenon is called electrical shading. Thus, reducing the width of the base region reduces electrical shading, which reduces recombination of such minority charge carriers and increases solar cell efficiency. If the area of the base region is reduced to the bare minimum needed, the electrical shading will be reduced to the bare minimum and the efficiency of the solar cell will be maximized. The use of pulsed laser ablation allows the formation of small features, thus forming a very small width base strip. The laser ablation technique can be further extended to form isolated islands of the base region that minimize electrical shading. The application of laser processing of solar cell fabrication is filed on May 27, 2011 and is disclosed in U. S. Patent Application No. 2012/0028399 to Virendra V. Rana, the entire contents of which are incorporated herein by reference.

The ion implantation process involves the implantation of ions of a dopant element in a silicon substrate. Ions of phosphorus (P), arsenic (As), and antimony (Sb) are implanted to form an n-type silicon substrate and boron (B), aluminum, gallium Is used to form the region. The most commonly used ions are P and As for n-type and B for p-type doping of silicon. The advantage of using ion implantation is the ability to control the concentration and depth of the implanted ions by controlling the implant dose and energy. In addition, implanted ions can be placed in silicon with any desired concentration profile (e.g., by combining multiple implants at varying amounts and energy levels). This technology is non-contact, drying technology. Because ion implantation is essentially performed at room temperature, the technique is suitable for solar cells that can not be heated to high temperatures after the ion implantation process step for various reasons.

For ions implanted to produce the desired doping of crystalline silicon, they need to be activated. A common technique used in the industry is furnace heating or rapid thermal heating, but this technique is not suitable when the solar cell or assembly can not be heated to a high temperature (e.g., much higher than 200 ° C) after the ion implantation process. On the other hand, the pulsed laser annealing can be very localized (spatially selective on the laser-irradiated surface), while keeping the backside of the cell relatively cool (e.g., limiting the backside temperature to only 200 ° C) The surface may be heated to a relatively high temperature (high enough to electrically activate the implanted dopant atoms, e.g., the irradiated surface temperature is selectively increased to a temperature in the range of from 750 캜 to the silicon melting temperature). Also, because of the very fast heating and cooling rates and the degree to which thermal diffusion from the irradiated surface to the substrate is negligible, pulsed laser annealing using fast pulses can be performed electronically, The bulk substrate is not significantly heated) and is ideally suited for producing sharp dopant gradients. Application of laser annealing to improve the passivation of SiN, alpha-SI / SiN or other suitable dielectric coated surfaces has been disclosed (Mehrdad Moslehi, U.S. Patent Application No. 13/303488, filed November 23, 2011, U.S. Patent Application No. 13/477088 to Virendra V. Rana filed on May 21, 2012, all of which are incorporated herein by reference in their entirety).

For weak thin crystalline silicon films, suitable thin substrate supports and non-contact substrate processing techniques may be desirable to maintain high manufacturing yields. Ion implantation and pulsed laser annealing meet this need. Also, due to corresponding recent improvements, this technique provides high output and can be tailored to larger cell sizes of any geometry.

19 is a modified process flow for forming a base region using ion implantation followed by laser annealing. Here, we describe the formation of isolated islands of the base region using the process shown in Fig. The various process steps of FIG. 19 are illustrated by the solar cell structure depicted in FIGS. 20-24. 20 is a diagram of a solar cell after the base isolation region is opened by a laser. 21 is a diagram of a solar cell after the base contact is opened by a laser. 22 is a diagram of a solar cell after base contact is implanted and laser annealed. 23 is a diagram of a solar cell after the emitter contact is opened by a laser. 24 is a diagram of a solar cell after the meshed metal pattern is contacted with the emitter and the base.

After deposition of boron doped oxide (BSG), preferably by an atmospheric pressure chemical vapor deposition (APCVD) system, the opening of dimension 'a' is preferably made in the oxide layer using a pulse picosecon or femtosecond laser (Fig. 20), which is sufficiently large for the isolation required from the emitter as well as the base contact of size 'b', minus 'b' (Fig. 21). The use of a pulse picosecond or femtosecond laser reduces the risk of silicon damage by preventing / stopping the underlying silicon melting and removing the heat-entrained area (HAZ). The high temperature oxidation (or high temperature annealing) is then performed at a temperature of 950 ° C to 1100 ° C to dope the n-type silicon surface with boron to form an emitter over the wafer surface, except for the region where the boron- Lt; 0 &gt; C. In addition, oxidation (or oxidation annealing) forms a thin layer of thermal oxidation (from a few nanometers to a few tens of nanometers) in the laser openings as well as at the interface of the silicon substrate and the intrinsically-doped oxide layer. A thin layer of undoped oxide (USG) is then deposited (again, preferably using an APCVD process) and the opening of the base contact is exposed to a thermal oxide underneath using a pulsed picosecond or femtosecond laser, Lt; / RTI &gt; The openings of dimension 'b' are first fabricated and are in openings 'a' that are center-to-center aligned. For example, the base contact diameter may be in the range of 10 to 100 mu m or more, and the preferable range is 20 to 50 mu m. For example, the width of the isolation region is 15 占 퐉 or more based on the laser beam alignment capability. For example, the percentage of base opening (base contact area ratio) may range from about 0.5% to 10% or greater, with a preferred range being about 1-3%.

Blanking ion implantation of phosphorus (P) is then performed (Figure 22). Since the thermal oxide / deposited oxide stack acts as a mask to prevent the implantation of emitter regions, the base contact is selectively implanted with P. The concentration (amount) and depth of the P implant are suitable for obtaining the desired doping of the base contact as well as the angle required for the back field (BSF). The surface concentration of the dopant can be from 1 x 10 ¹⁹ to 1 x 10 ²¹ cm 3, and the preferred range is from 5 x 10 ¹⁹ to 1 x 10 ²⁰ cm 3. The depth of the injected dopant may be 0.1 to 5 占 퐉, and the preferable range is 0.3 to 0.5 占 퐉.

This implant is electrically activated using pulsed laser annealing (Figure 22). Pulsed lasers with nanosecond pulse widths and blue, green or infrared (IR) wavelengths are suitable for such operations. The pulse width is in the range of about several nanoseconds to several microseconds, and preferably in the range of about 100 to 1,000 nanoseconds. However, in the case of a thicker silicon film, it may be possible to use a laser with a microsecond pulse width.

After doping and activation of the base contact is completed, contact to the emitter is opened using a pulse picosecond or femtosecond laser (Fig. 23). The metal layer (preferably a metal stack layer comprising at least another layer and an aluminum layer in contact with the cell on top of the aluminum containing metal from the group of NiV, Ni, or Ag) contacts the base and emitter openings (Or a combination of a pulse nano-second and a pulsed pico-second laser) to form a photovoltaic circuit by separating the p and n contacts to form a photovoltaic circuit, which is typically deposited using physical vapor deposition (PVD) And patterned (FIG. 24). The remainder of the process may be as described in FIG.

Alternatively, instead of a PVD metal stack, an aluminum-containing paste can be screen printed and annealed to form an engaged metal pattern while making contact with the emitter and base contacts. The remainder of the process may be as described in FIG.

The use of ion implantation also provides a simple way to achieve the so-called "selective emitter" feature. In selective emitter schematics, under metal contact, the emitter is highly doped to reduce contact resistance, but the doping concentration of the emitter is kept low anywhere to reduce absorption, improving solar cell efficiency. Figure 25 is an embodiment of a process flow for forming selective emitters. In this scheme, before the base isolation region is opened, the BSG layer is removed using a laser so that the exposed silicon is implanted with a high concentration of boron. In others, the oxide film prevents boron implantation from reaching the silicon. The surface concentration of the boron dopant is 1 x 10 ¹⁹ to 1 x 10 ²¹ cm 3, with a preferred range of 5 x 10 ¹⁹ to 1 x 10 ²⁰ cm 3. The depth of the injected dopant may be 0.1 to 5 占 퐉, and the preferable range is 0.3 to 0.5 占 퐉. The silicon surface is annealed or laser annealed using a laser. Figure 26 shows a cell pattern with separate islands of base and emitter contact with selective emitters, Figure 27 shows a cell pattern with base isolation and optional emitter openings made using laser ablation, Respectively.

For the back contact / back side junction cell, the minority charge carriers generated near the top surface of the silicon must travel all the way down from the back contact. Most photo-generated charge carriers (electron-hole pairs) are closer to the front with greater potential for recombining them at this surface. Therefore, the passivation on the front side (or on the side where the battery light is reflected) should be excellent in order to obtain high cell efficiency. The front passivation is characterized by a front recombination speed (FSRV) with a lower FSRV value (generally referred to as the cm / sec unit) indicating better surface passivation. FSRV is generally reduced to very low values using PECVD SiN deposition followed by annealing at relatively high temperatures (e.g., from 300 ° C to 850 ° C), or PECVD amorphous silicon deposition (typically deposited at temperatures below 200 ° C) . However, all of these processes have limitations. Good surface passivation requires annealing to temperatures as high as 8500 占 폚, but passivation to amorphous silicon requires high-quality surface cleaning and optimized PECVD amorphous-silicon deposition at temperatures above about 180 占 폚, Post-deposition annealing is required in a range of temperatures as high as 450 ° C. Both of these processes are suitable for solar cell assemblies that can not be heated to above 200 占 폚 during or after a front passivation process (e.g., for thin film monocrystalline solar cells having layers or sheets that can not withstand a heat treatment that is much higher than about 200 占 폚) I can not.

The other scram that further lowers the charge carrier recombination is to form the 'high-low' field at the front. This field can electrically repel carriers of opposite charge, reach the front and can not recombine. For an n-type substrate or n-type base (e.g. n-type base back contact / rear junction solar cell) n-type dopant). &lt; / RTI &gt; At the front, this high-low field is called the front field (FSF). The results of the simulation based on PC1D are shown in the graph of Fig. 28, and the increase in the concentration of the front surface doped with P increases Voc and Jsc, thereby increasing the solar cell efficiency. Even thinner FSF layers at the top of the FSF or semiconductor layer as thin as 100 A (or 10 nm) can lead to an increase in Voc (open circuit voltage) and short circuit current density (Jsc) as much as the nearly thicker FSF layer . As shown in Figure 25 where the FSF thickness is 0.5 [mu] m, Voc and Jsc are observed to decrease at higher doping concentrations associated with blue response degradation by thicker and heavily doped FSF layers, It is necessary to reduce the thickness of the film. (Pulse width is preferably in the range of about 100 nanoseconds to several microseconds) after ion implantation of phosphorus (or arsenic or antimony or indium) laser annealing (laser wavelength is preferably blue, green, red or red For a back contact / back junction thin film monocrystalline silicon solar cell having an n-type base using a high temperature (around the region of the substrate), the formation of the FSF is preferably carried out by heating the substrate to an effective surface temperature And the temperature rise of the back side and the bulk of the semiconductor layer is substantially stopped, and in particular, the assembly component on the back side (for example, the reinforcing or back plate layer on the battery rear side) (For example, 200 DEG C or more).

The FSF layer can be performed using pulse laser annealing after the formation of the front passivation layer after an ion implantation process (preferably by a PECVD process step) before and after the formation of the front passivation layer.

Pulsed laser annealing after formation of the FSF on the front surface of the silicon substrate using ion implantation of phosphorus (P) or another n-type dopant (for a solar cell having an n-type base) is schematically shown in Fig. 29A is a cross-sectional view of a solar cell having a textured front surface. 29B is a cross-sectional view of a solar cell after ion implantation of an n-type dopant such as phosphorus. 29C is a cross-sectional view of the solar cell after laser annealing to activate the implanted phosphorous (for the n-type base).

Formation of the electrically active FSF layer may be achieved by depositing a passivation and anti-reflective coating (ARC) layer on the front side of the silicon substrate, preferably after the surface texture, such as a hydrogen containing silicon nitride and / or a hydrogen containing amorphous silicon layer (E.g., by PECVD formation of a single layer or multilayer passivation / ARC coating that includes a). At this stage, the thin film monocrystalline silicon substrate has a thermal expansion coefficient (CTE) mismatch with the silicon (generally this limit can be in the range of about 150 DEG C to 300 DEG C, more preferably 250 DEG C or less, Or back plate (permanently attached / laminated backing plate or temporary support carrier) that can not be heated to high temperature due to the back plate material temperature limit.

The combination of ion implantation and pulsed laser annealing for the formation of the FSF field as described herein has several major possible advantages. In addition to maintaining the backside of the solar cell assembly below the temperature limit of the solar cell backplane laminate (e.g., below about 200 degrees Celsius), the ion implantation process may be performed using dopant species implanted at uniformly constant depths with the surface texture random pyramid For example, phosphorous) to form a dopant profile on the textured solar cell surface and silicon at a right angle. The ion implantation process may be performed before or preferably after formation of the front passivation / ARC coating using a relatively low energy ion implantation process. If the ion implantation process is performed after the formation of the front passivation / ARC coating, the ion implantation energy is determined by the location of the peak concentration of the implanted profile in the passivation / ARC coating layer or at the interface between the silicon substrate and the passivation / . The amount of ion implantation process can be adjusted so that the resulting peak doped dopant concentration is preferably in the range of about 5 x 10 ¹⁶ to 1 x 10 ¹⁹ cm -3. The front passivation may be performed using SiN (consisting of single or at least two different refractive index) or amorphous silicon / SiN stacks, or oxide / SIN stacks, or other layers and stacks such as silicon oxynitrides with or without oxides in the underlying layers, And so on. The ion implantation process is adjusted to provide dopant implantation, such as phosphorus (P) implantation of the n-type base, such that the concentration peak is preferably at or near the silicon substrate / passivation layer interface. The surface concentration of the P-dopant in the n-type base may be from 1E16 to 1E20 cm-3, but the preferred range is from 5E16 to 1E19 cm-3. The dopant atoms may be implanted and laser annealed to form an FSF layer to a depth below the silicon surface, which may range from about 10 A to about 1 micron, but a FSF layer with a thickness in the range of about 50 A to about 0.1 [ It is preferable to prevent deterioration.

Because of the very fast heating and cooling times and limited thermal diffusion depth, pulsed laser annealing can electrically activate dopant atoms implanted without movement. As a preferred process, pulsed laser annealing is performed under conditions that prevent overheating and melting of silicon in order to prevent deterioration of the passivation characteristics and damage of the silicon. This allows the formation of a relatively sharp step function profile of the dopant atoms which helps the FSF field to amplify, which helps to improve the repulsion field and front passivation properties. Nanosecond (or microsecond) pulsed lasers with blue or green or red or infrared (IR) wavelengths are partially suitable for selective annealing. Preferred pulse cords are in the range of about 100 to 1,000 nanoseconds. However, in the case of a thicker silicon film, it may be possible to use a laser with a microsecond pulse width. In addition, other pulsed laser sources having pulse widths of from about 1 nanosecond to 100 nanoseconds or even several microseconds may be used.

The process flow for forming the FSF layer-based solar cell is shown in Fig. FIG. 31 shows a combined process flow wherein a high efficiency solar cell is fabricated to have a front FSF, followed by ion implantation and an annealed base contact, based on an embodiment of the present invention. Figure 32 illustrates a process flow that also includes selective emitter formation. 33 is a diagram of a cross-sectional view of a solar cell formed according to the disclosed subject matter (the back plate is not shown for clarity).

Although process flows and techniques describe n-type base-based cells, the same considerations apply to p-type (n-type) Based battery.

For simplicity, the process is described for a planar silicon film, but the same is valid for a 3-D silicon substrate formed using a pre-structured template having various pyramidal or prismatic 3D patterns.

Two additional methods for laser annealing are further described below, in which the light-emitting side of the solar cell is annealed without necessarily affecting the side or back of the solar cell's unshielded side.

Conventional back-contacting solar cells are n-type substrates and use PECVD-based SiN-based passivation on the exposed side. This passivation also acts as an antireflective coating and has a positive fixed charge that helps to generate a field effect by reflecting a minority carrier (in this case a hole) from the surface. A generally good quality passivation deposition temperature for PECVD SIN is about 400 ° C. In some cases, the maximum acceptable temperature may be less than 400 占 폚, as indicated by the integration scanner. For example, in the case of an ultra-thin crystalline silicon solar cell, it is supported by a carrier that can not rise above a maximum temperature of less than 400 ° C.

In certain instances, this temperature may be as low as 200 占 폚. With a maximum temperature limit of 200 ° C, the problem is to achieve a passivation quality as good as a typical passivation of 400 ° C. A possible solution is to deposit a range of ultra-thin amorphous silicon (which may be 30A to 100A) so as to be non-absorbing. This idea is that amorphous silicon contains enough hydrogen to passivate the dangling bonds, thereby improving the passivation quality. However, the problem is that at a temperature of 200 캜, hydrogen atoms can not have sufficient fluidity to migrate from the microcrystalline silicon to the silicon interface.

To aid in the flowability of hydrogen atoms, laser annealing is used which keeps the pulsed form for a very short period of time. This should be sufficient to cause H2 atoms to travel for a short distance without interfering with the integrity of other parts of the structure. The laser process must ensure that the front surface is selectively heated, while ensuring that the backing plate, which can be made of a thermosensitive metal structure, is not affected.

In one embodiment, this may be done using a short wavelength laser that is absorbed near the side of the side of the solar cell where the light is reflected. A short wavelength laser (e.g., green) can be easily absorbed within a distance of less than 1 um, minimizing the opportunity to price the thermally sensitive rear structure of the rear contact cell.

In other embodiments, longer wavelengths in the same range as 1 占 퐉 may be used. Longer wavelengths will travel longer distances to the silicon and reach the backside without being absorbed into the bulk. Thus, the process must be designed so that the front side, the light side, is heated, but the laser is prevented from pricing the back side. This can be done by absorbing the laser power in silicon or by reflection before reaching the back side. Absorption can be done in the bulk after the laser has already passed through the critical front side. This can be done using the above-described technique, which relies on the plasma scattering effect to get absorbed, and floats the bulk with a carrier that is excited by a laser of potentially different wavelengths in the CW mode. Of the several methods of reflecting an annealing laser, two characteristic embodiments are described below.

As an example, the fact that the annealing laser is monochromatic is used. The mirror is formed on the rear side using various refractive indexes. The thickness is adjusted according to the refractive index so that the laser is selectively reflected by the dielectric mirror stack at 1 um (or at the appropriate wavelength in use). In one embodiment, the dielectric mirror stack may be fabricated using SiO2 and SIN. SiO2 can be deposited by deposition or APCVD using many techniques such as thermal oxidation. The SiN can be deposited using PECVD. In many instances, at least a portion of the dielectric stack may be part of the back passivation in advance. Since the metal is formed behind the dielectric mirror, the laser is reflected back toward the front before it comes into contact with the back metal. (Since the metal is behind the dielectric mirror, the laser is reflected back toward the front surface before it touches the back metal).

In another example of reflecting an annealing long wavelength laser, the tilt angle of the laser can be changed with the terrain of the generally textured surface of the front surface. In most rear-facing solar cells, the front side is passivated on top of the silicon. Thus, light generally enters from a higher reflectivity to a lower reflectivity. Thus, the angle of incidence of the annealing laser can be altered in such a way that when the light enters the backside silicon / dielectric (typically SiO2), the angle of incidence at that surface is greater than the critical angle for total internal reflection (hereinafter TIR) . Thus, before the TIR has the opportunity to contact the back side metal stack, it causes the laser beam to be reflected back toward the front side (TIR causes the laser beam to be reflected back toward the front side well before a chance to touch the backside metal stack).

In operation, the following process and process embodiments are provided herein: the process for forming the isolated islands and / or the front field (FSF) of the base using ion-implanted pulsed laser annealing is performed using all of the thin- Lt; / RTI &gt; is disclosed for a rear-contact back-junction solar cell; The process for forming the base isolation islands and the front electric field (FSF) using pulse laser annealing after ion implantation is performed using a back plate laminate or assembly such as a cell reinforcing plate that can not be heated to a temperature in the range of approximately the maximum temperature of 150 [deg.] C to 3500 [ Lt; RTI ID = 0.0 &gt; a &lt; / RTI &gt; thin-film crystalline silicon substrate.

In another embodiment, a process for forming isolated islands and a front electric field of a base using pulse laser annealing after ion implantation for a 3-D back contact back junction solar cell using a thin film crystalline silicon substrate; A process for forming selective emitters using ion implantation furnace or laser annealing is disclosed. In the selective emitter region, the surface concentration of the boron dopant can be from 1 x 10 19 to 1 x 10 21 cm 3, with a preferred range from 5 x 10 19 to 1 x 10 20 cm 3. The depth of the implanted dopant may be from 0.1 to 5 탆, and the preferred range is from 0.3 to 0.5 탆; A front surface using pulse laser annealing after ion implantation for all rear contact back junction solar cells using a thin film crystalline silicon substrate with a peak concentration of implantation in the range of 1E16 to 1E20 cm-3 and a preferred range of 5E16 to 5E18 cm-3 A process for forming an electric field (FSF) is disclosed.

In another embodiment, the depth of the resulting FSF layer formed by the combination of ion implantation and pulsed laser annealing is in the range of about 10A to 0.5 mu m, and the preferred range is about 50 to 1000 A, A process for forming a front electric field (FSF) using laser annealing after ion implantation for a contact back junction solar cell is disclosed.

In other embodiments, the FSF formation may be accomplished by depositing a SiN or amorphous silicon / SiN stack, or an oxide / SIN stack, or other layers deposited at a temperature of less than 200 DEG C and silicon oxynitride with and without oxide, Is performed on a textured thin film silicon substrate that can be passivated into the same stack.

In another embodiment, the process for forming the front electric field (FSF) using pulse laser annealing after ion implantation may be performed at all of the backside surfaces using a thin film crystalline silicon substrate when the concentration peak for the dopant is approximately at the silicon / Contact back-junction solar cell.

In another embodiment, a process for forming a front electric field (FSF) using laser annealing after ion implantation is disclosed for all back contact back junction solar cells using a thin film crystalline silicon substrate, and pulse laser annealing is performed with a pulse width of nanosecond And preferably a blue or green or red or IR wavelength, and the preferred pulse width is in the range of about 100 to 1000 nanoseconds.

In another embodiment, a process is disclosed for forming isolated islands of a base for all back contact back junctions using a thin film crystalline silicon substrate, wherein the separated base contact islands are formed of a picocecon having a UV, green or IR wavelength, or And is formed using an aligned laser removal using a femtosecond pulse laser. The base contact diameter is in the range of 10 to 100 mu m, and the preferable range is 20 to 50 mu m. The width of the isolation region is preferably > 15 [mu] m based on the laser beam alignment capability. The percentage of the base opening may range from about 0.5% to 10%, and the preferred range is from 1% to 3%.

In another embodiment, a process for forming isolated islands of a base for all rear contact backside junctions using a thin film crystalline silicon substrate is disclosed, wherein the base doping is performed by pulse laser annealing after ion implantation. The surface concentration of the dopant may be from 1E19 to 1E21 cm-3, and the preferred range is from 5E19 to 1E20 cm-3. The depth of the implanted and annealed dopants can be from about 0.1 to about 5 mu m, with a preferred range from about 0.3 to about 0.5 mu m.

In another embodiment, a process for annealing a wafer using a laser is disclosed, wherein the laser beam is prevented from being heated since the laser beam is reflected from the SiO2 / SiN bilayer on the back surface of the silicon film.

In another embodiment, a process for annealing a wafer with a laser is disclosed, wherein the laser beam is prevented from being heated since the laser beam undergoes total internal reflection due to the angle at which the slope is made on the backplane. This can be done by adjusting the tilt angle of the laser burden depending on the dielectric stack on the front side of the wafer.

The foregoing description of the embodiments is provided to enable those skilled in the art to make or use the subject matter. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without the use of innovative capabilities. Accordingly, the subject matter claimed in a subsequently filed application is not limited to the embodiments shown herein but is to be accorded the widest scope consistent with the novel features and principles described herein.

Claims (37)

BACKGROUND OF THE INVENTION [0002] As a method of forming a base region of a back-side junction thin-film crystalline silicon solar cell,
The method comprises:
Forming openings in the dielectric layer for base contact on the thin film crystalline silicon substrate, the openings forming a patterned dielectric agent layer;
Implanting ions of a dopant element into the thin film crystalline silicon substrate in the patterned dielectric layer to selectively introduce a dopant element at the base contact, wherein the patterned dielectric is used as an ion implantation mask;
Activating the implanted dopant element to form an electrically active doping base contact;
Forming an emitter contact on the thin film semiconductor substrate; And
And forming a metallized contact on the emitter contact and the base contact.
The method of claim 1,
Wherein the dopant element comprises at least one element from the group of phosphorous, arsenic, antimony, and indium in combination with an n-doped epitaxial silicon substrate.
The method of claim 1,
A method comprising: forming a crystalline thin-film silicon substrate;
Wherein the step
Forming a porous sacrificial layer on the surface of the silicon template and at a substantially right angle;
Depositing an epitaxial silicon layer on the sacrificial layer;
Performing a plurality of solar cell processing steps including the ion implantation step;
Defining a lift-off substrate separation boundary within a predetermined size and pattern associated with the size and pattern of the resulting solar cell;
Separating the epitaxial silicon layer from the silicon template through an epitaxial lift-off process or mechanical separation.
The method of claim 1,
Wherein the silicon substrate is an n-type silicon substrate and the base contact doping element is phosphorous (P), arsenic (As), or antimony (Sb).
The method of claim 1,
Wherein the silicon substrate is a p-type silicon substrate and the base contact doping element is boron, gallium or aluminum.
The method of claim 1,
Wherein the opening for the base contact is performed using laser ablation.
The method according to claim 6,
Wherein said laser ablation is pulsed picosecond laser ablation.
The method according to claim 6,
The laser ablation is pulse femtosecond laser ablation.
The method of claim 1,
Wherein activating the injected dopant element is performed using furnace annealing.
The method of claim 1,
Activating the implanted dopant element is performed using laser annealing.
11. The method of claim 10,
Wherein said laser annealing is pulsed nanosecond laser annealing.
The method of claim 1,
Wherein the base and emitter contacts are patterned into parallel regions.
The method of claim 1,
And the base and emitter contacts are formed of separate islands.
The method of claim 1,
The percentage of the base opening may range from about 0.5% to 10%.
The method of claim 1,
The laser ablation is a method wherein the wavelength is carried out using a laser of IR, green or UV or any wavelength therebetween, preferably UV.
The method of claim 1,
Wherein the surface concentration of the dopant in the base may be 1 × 10 ¹⁹ to 1 × 10 ²¹ / cm 3 and injected at a depth of 0.1 to 5 μm.
Rear-contact Rear-junction thin-film crystalline silicon solar cell A method for forming the front electric field region:
The method comprises:
Implanting dopant atoms onto the front side of the thin film crystalline silicon substrate; And
And activating the implanted ions using laser annealing to form a doped front layer.
18. The method of claim 17,
Wherein the dopant element comprises at least one element selected from the group of phosphorous, arsenic, antimony and indium, together with an n-doped epitaxial silicon substrate.
18. The method of claim 17,
Wherein the dopant element has a peak concentration in the range of 1E16 to 1E20 cm &lt;&quot; ³ &gt;, wherein activating the implantation forms a front electric field on the thin film crystalline silicon substrate.
18. The method of claim 17,
Wherein the front electric field has a depth in the range of 10A to about 1 micron on the front side of the thin crystalline silicon substrate.
18. The method of claim 17,
Wherein the thin film crystalline silicon substrate is passivated into a passivation layer deposited at less than 250 &lt; 0 &gt; C.
21. The method of claim 20,
Wherein the passivation layer is selected from the group consisting of SiN, an amorphous silicon / SiN stack, an oxide / SiN stack, or silicon oxynitride with or without an oxide underlayer, and silicon carbide.
21. The method of claim 20,
Wherein the passivation layer is deposited after ion implantation and laser annealing.
21. The method of claim 20,
Wherein the ion implantation and annealing is performed after the passivation layer is deposited.
18. The method of claim 17,
Wherein the peak concentration of the dopant element is at the interface of the silicon film and at the passivation layer.
18. The method of claim 17,
Wherein the angle of incidence of the laser beam is adjusted based on a dielectric stack on the front side of the substrate to prevent the back side from heating while undergoing full internal reflection.
18. The method of claim 17,
Wherein the laser is a continuous wave (CW) or pulsed laser.
18. The method of claim 17,
The laser having a wavelength of 1064 nanometers or less.
A method for forming a selective emitter region of a rear contact back junction thin film crystalline silicon solar cell comprising:
The method comprises:
Forming a first opening for emitter contact on the thin film crystalline silicon substrate;
Selectively implanting ions of a dopant element of the thin film crystalline silicon substrate at the emitter contact;
Activating the implanted ions to form a doped emitter contact; And
And forming a metallized contact on the emitter contact and the base contact.
29. The method of claim 28,
Wherein said silicon substrate is an n-type silicon substrate and said base contact doping element is boron, gallium or aluminum.
29. The method of claim 28,
Wherein said silicon substrate is a p-type silicon substrate and said base contact doping element is phosphorus (P), arsenic (As), indium (In), or antimony (Sb).
29. The method of claim 28,
Wherein the silicon substrate is a p-type silicon substrate and the base contact doping element is boron, gallium or aluminum.
29. The method of claim 28, wherein
Wherein the opening of the base is performed using pulsed laser ablation.
29. The method of claim 28,
Wherein the implant activation is performed using furnace annealing.
29. The method of claim 28,
Wherein the implant activation is performed using laser annealing.
29. The method of claim 28,
Wherein the base and emitter contacts are patterned into parallel regions.
29. The method of claim 28,
And the base and emitter contacts are formed of separate islands.

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