CA2623382A1

CA2623382A1 - Systems and methods for manufacturing photovoltaic devices

Info

Publication number: CA2623382A1
Application number: CA002623382A
Authority: CA
Inventors: Tom Rust
Original assignee: Individual
Current assignee: Individual
Priority date: 2005-09-23
Filing date: 2006-09-21
Publication date: 2007-04-05
Also published as: JP2009510724A; WO2007038297A2; EP1938388A2; WO2007038297A3

Abstract

Die for photovoltaic cells can be manufactured using a pattern region that substantially covers the usable surface area of a crystalline workpiece. Bars can be etched into the workpiece that extend substantially the entire length of the workpiece. These bars then can be diced to form die having a width substantially equal to the thickness of the workpiece, and having an edge ratio of ab out 20:1 or less. Such a process can maximize conversion area, thereby extracting more energy from a given volume of photovoltaic conversion material. Contacts can be placed on opposing edges of the die to form photovoltaic cells, which in some embodiments can function regardless of orientation in a solar panel.

Description

SYSTEMS AND METHODS FOR MANUFACTURING
PHOTOVOLTAIC DEVICES

CLAIM OF PRIORITY
[0001] This application claims priority to U.S. Provisional Patent Application No.
60/720,084, filed September 23, 2005, and U.S. Provisional Patent Application No.
60/726,520, filed October 13, 2005, each of which is incorporated herein by reference.

TECHNICAL FIELD OF INVENTION

[0002] The present invention relates to photovoltaic devices and methods for producing and assembling those devices.

BACKGROUND OF THE INVENTION

[0003] A photovoltaic device is a seiniconductor device typically used for converting solar radiation into electrical energy. Solar photovoltaic systems to this point have not been used extensively in power supplying applications due primarily the high cost of these systems.
The high cost is due in part to the relatively high cost of the pure single crystal silicon that typically is used in these devices. Much of this silicon is wasted in the manufacturing of these devices, thereby increasing the material cost. Further, the cost of the photovoltaic processing itself is not particularly cost effective for many applications.
Alternatives to silicon have been studied, but have been found to either produce less efficient devices or to cost more to manufacture. Prior art solar panels also typically are assembled using machinery to precisely position a large number of cells on a substrate, which can be expensive and very time intensive. The length of these cells also can cause problems with jamming, clustering, and breaking during processing.

BRIEF SUMMARY OF THE INVENTION

[0004] Systems and methods in accordance with various embodiments of the present invention provide for the production and assembly of various photovoltaic devices. In one such embodiinent, a photovoltaic cell is formed by depositing a mask layer on a substantially planar piece of crystalline material, such as silicon, germanium, or gallium arsenide. The piece of crystalline material is etched to form a plurality ot substantially parallel slots. The slots fonn a plurality of substantially planar bars each extending substantially from one edge of the piece of crystalline material to the other edge of the piece along the direction of the bar. The width of each bar is substantially equal to a thickness of the piece of crystalline material. The bars can be separated from the piece of crystalline material, and diced to form a plurality of substantially rectangular cells.

[0005] Each of the bars can have a layer with a doping opposite a bulk doping of the respective bar. The layer can be formed using any appropriate process, such as diffusion. Contacts can be fonned on the top and bottom of each rectangular cell, or on the sides of the cells. In one embodiment, a first set of contacts is formed on a first side and a second set of contacts is formed on a second side of each rectangular cell. At least one of the number and positions of each set of contacts is selected to provide for proper contact connections regardless of the orientation of the respective cell with respect to a connecting device.

[0006] The mask layer can include a non-rectangular pattern region'for forming the slots.
The mask layer also can include a pattern region for forming the slots that is selected so the formed bars utilize at least 80% of the surface of the piece of crystalline material. The bars then can be diced in one embodiment to have an edge ratio of about 20:1 or less. Each bar also can have an anti-reflective coating deposited thereon, and/or texturing of at least one surface.

[0007] Each diced cell can be placed on a substrate, such as a conductive substrate, a low temperature substrate, and/or a flexible substrate. Additional layers then can be deposited in one embodiment to form a multi-junction device. At least a portion of the cells on a substrate can be connected using parallel, serial, parallel-serial, and/or serial-parallel connections.

[0008] In one embodiment, such a process formed a photovoltaic cell including a rectangular crystalline die having at least two oppositely doped regions forming a diode. The die can have a widtli of about 2mm or less, a length of about 40 inin or less, and a thickness -of about 100 m or less. The cell also includes a pair of contacts placed on opposite edges of the crystalline die, such as on the top and bottom edges or opposing side edges of the die.
The pair of contacts can be part of a first set of contacts on a first edge of the crystalline die and a second set of contacts on a second edge of the crystalline die, the first edge being opposite the second edge, that allows the crystalline aie to be piaced in an array ot substantially coplanar photovoltaic cells in any orientation.

[0009] The rectangular die is substantially square in one embodiment. The die also can be formed from a substantially planar piece of <1,1,0> oriented silicon. An anti-reflective coating can be deposited on at least one surface of the crystalline die, and/or at least one surface may be textured.

[0010] Such cells can be used to fonn a solar module, for exainple, which has a substrate including an array of receptacles, and a plurality of rectangular photovoltaic cells positioned in the array of receptacles. Eacli photovoltaic cell can have a width of about 2mm or less, a length of about 40 inm or less, and a thickness of about 100~un or less. Each photovoltaic cell can further have contacts on two opposing edges of the photovoltaic cell.
The module also includes an interconnect layout electrically connecting contacts of the plurality of rectangular photovoltaic cells. The contacts can be placed on a top and a bottom or opposing side edges of each photovoltaic cell, for example. The contacts also can include at least one first contact on a first side edge and at least one second contact on a second edge, the first and second contacts being positioned at different edge locations so that each of the first and second contacts connects with a desired line of the interconnect layout regardless of the orientation of the photovoltaic cell in the respective receptacle.

[0011] The interconnect layout can divide the plurality of photovoltaic cells in the array of receptacles into sub-modules. The interconnect layout also can connect the photovoltaic cells in each module in parallel, and at least a portion of the sub-modules in series. The interconnect layout also can connect the photovoltaic cells in each module in series, and at least a portion of the sub-modules in parallel. A laminate layer can be used to hold the plurality of photovoltaic cells in the array of receptacles.

[0012] Other embodiments will be obvious to one of ordinary skill in the art in light of the description and figures contained herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Various embodiments in accordance with the present invention will be described with reference to the drawings, in which:

[0014] FIG.1 illustrates a photovoltaic cell asseinbly in accordance with one embodiment of the present invention;

[0015] FIG. 2 illustrates an array of photovoltaic cells in accordance with one einbodiinent of the present invention;

[0016] FIGS. 3(a) and 3(b) illustrate a slot pattern that can be used in accordance with one einbodiment of the present invention;

[0017] FIG. 4 illustrates steps of a cell-fonning method that can be used in accordance with one embodiment of the present invention; -[0018] FIG. 5 illustrates a grid for arranging slivers in accordance with one embodiment of the present invention;

[0019] FIG. 6 illustrates a photovoltaic cell assembly in accordance with one embodiment of the present invention;

[0020] FIG. 7 illustrates the etching of vias in accordance with one einbodiinent'of the present invention;

[0021] FIG. 8 illustrates a front view of a photovoltaic cell in accordance with one embodiment of the present invention;

[0022] FIG. 9 illustrates a side view of two cells embedded in a substrate with overlaid interconnect in accordance with one embodiment of the present invention;

[0023] FIG. 10 shows an example array of 4x4 of the cells with interconnection in accordance with one embodiment of the present invention;

[0024] FIG. 11 illustrates a front/rear view of the cell of FIG. 7 in one possible orientation, with a set of intercoruiect lines overlaid and 'with potentials for each line in accordance with one embodiment of the present invention;

[0025] FIG. 12 illustrates a set of three cells in a vertical column, with each cell at the same orientation, in accordance with one embodiment of the present invention;

[0026] FIG. 13 illustrates a single cell and a keyed slot into which the cell inserts, in accordance with one embodiment of the present invention; and [0027] FIG. 14 illustrates a set of four columns of cells with interconnect between columns a photovoltaic cell assembly in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0028] Systems and methods in accordance with various embodiinents of the present invention can overcome the aforementioned and other limitations in exiting photovoltaic devices and device manufacturing approaches. A process in accordance witli one einbodiinent takes advantage of the crystalline structure of the inaterials used in the process, such as <1,1,0> oriented silicon crystals, by etching very thin, small die which incorporate the structures needed to convert photons to electrical energy, as well as to interface to various electrical systeins. Silicon crystals in such an orientation can be used as described herein to create narrow, high aspect cells by generating slivers that run substantially the length of the wafer, minus any dividing bars as discussed below, then dicing these slivers into square or rectangular cells. Rectangular cells in one einbodiment have an edge ratio, sucli as length:width, of about 20:1 or less, and preferably 3:1 or less in one embodiment. Processes in accordance with various embodiments also can include steps for assembling these cells rapidly onto substrates, and incorporating interconnect layouts that allow the die to be assembled in random orientations. Such processes can be advantageous, as well as simpler and cheaper than existing processes for forming photovoltaic devices.

[0029] Metliods of fabricating photovoltaic cells and modules in accordance with various embodiments of the present invention can produce devices with high efficiency and low cost per energy conversion area. These methods also can maximize the utilization of various materials relative to other solar cell fabrication techniques. Similar approaches can be used, including one which concentrates on simplicity and low cost, and one that is more complicated but can be done with low temperature pastes and materials, thereby greatly expanding the number of substrates and materials that can be used. For example, low temperature substrates can be used with pastes and materials at 300 C or less.

[0030] In one embodiment, the individual cells are fabricated in a rectangular pattern out of <1,1,0> silicon crystal. An example of such a photovoltaic cell 102 is shown in the assembly 100 of FIG. 1. The cell formed in this exainple is front/back and side/side symmetric, such that the front and rear views are substantially identical. This particular view shows the bulk materia1104, with a thickness that is determined primarily by the thickness of the silicon wafer or other material used to form the die. It can be desired for some embodiments that the thickness be greater than that of a standard silicon wafer. This cell 102 has upper 106 and lower 108 doped regions, as will be discussed below. Orientations and directions such as "front," "back," "upper," and "lower" are merely used for convenience and simplicity of explanation, and are not meant to infer any requireinents of directionality or orientation.

[0031] In a cell in accordance with one einbodiment, the top region 106 and the bottom region 108 are phosphorus doped regions, or n-type regions, with a central bulk doped boron region 104, or a p-type region. This figure is not to scale, as each of these regions would typically be thinner relative to the thicluiess of the bulk silicon 104. While in at least some embodiinents it is preferred that the wafer be thicker, as having larger cells can be more efficient and require less processing, thicker wafers also can require longer etches, which can result in an undesirable ainount of undercutting. In one embodiment the thickness of the bulk silicon wafer can be on the order of about 1-2mm. It should also be understood that phosphorus doping is merely exemplary, and that devices in accordance with various einbodiinents can use any appropriate coinbination of a bulk doping layer (or region) of a first doping type and an emitter doping layer (or region) of a second doping type, where the emitter doping is of opposite doping relative to the bulk doping, and wherein the emitter doping is in a shallow emitter layer at the surface of the device [0032] As will be discussed below, a layer of anti-reflective coating 110 is formed about the cell. The antireflective coating can be a nitride or oxide layer, for example. The bottom doped region 108 in this example is an n-type region as it is forined, but when a 25-40 m thick layer of aluminum paste 112 is printed or otherwise applied to the cell and fired, the paste penetrates through the antireflective coating 110 and the p-doping, so that the aluminum paste effectively contacts the p-body bulk layer 104, becoming a p-connection, and effectively negates the n-type doping of the lower layer 108.

[0033] As is discussed below, the assembly also includes an optional lower paste layer 114, such as a 10-15 m layer of silver paste, and a substrate 116. On top of the cell 102 is another paste layer 118, such as a 10-20 m layer or silver paste with a special anti-reflective coating (ARC) penetration capability, such that the layer penetrates into the ARC
layer 110 and contacts the top n-type layer 106. A 10-20 m layer of regular silver paste 120 that does not penetrate the ARC, such as a thermoplastic silver paste or solder paste, can be'applied on top of the asseinbly to interconnect the top electrodes of each cell to adjacent cells. In an alternate embodiment, an insulator paste is applied over the sides of the cells, and the paste layer 118 is applied over the insulator paste. In another embodiment, an insulator paste is placed under and around the sides of the cell, for the purpose of increasing the adhesion between the cell and the substrate assembly. The insulator layer is not designed to affect the cell electrically, but to help in holding the assembly together more rigidly.

[0034] FIG. 2 shows a top view 200 of portion of an array of cells, showing the width (about 300~Lin in this exainple) of the thin silver paste layer 118 with ARC
penetration capability, as well as the top silver paste or solder paste layer 120 of an array of cells.
Reference nuinbers are carried over between figures for convenience and siinplicity of understanding, and are not meant to be construed as limitations on the various embodiinents.
First PNocessing Approach [0035] A process for making such a cell, in this case a rectangular cell, in accordance with one embodiment starts with a wafer, of <1,1,0> oriented silicon. The silicon can be of high purity, doped with an N- or P-type dopant, and/or in the fonn of a wafer that is 2mm thick and at least 100mm (e.g., 150mm) in diameter, for example. The silicon boule has a wafer flat, cut with a relatively high degree of precision. The specification for the cutting is typically within ~L0.5 , but can be cut to within 0.1 in accordance with the various embodiments. Since these wafers are going to be aligned and etched with respect to the crystal orientation, small amounts of deviation can end up thinning one side of the cell as the cell is being formed, such that a tight tolerance is desirable. The wafer can be cleaned using an appropriate process, such as a piranha cleaning process. The wafer also can be polished, such as by double polishing the surfaces and rounding the edges if desired.

[0036] A silicon nitride mask layer about 2,000A thick in one embodiment is deposited on all sides of the wafer. The wafer then can be prepared for photoresist deposition, such as by applying a Hexamethyldisilazane (HMDS) primer to serve as an adhesion promoter for photoresist. The resist then can be spun on the front and back side of the device, applying the resist to the front and back simultaneously or at different times. In one embodiment, a jig is used that has a large plate with three pins. One of the mask plates is put on the jig, with the mask plate also having three pins which align the wafer flat on two of the pins and the wafer edge on the third pin, thereby aligning the wafer to the mask. Anotlier mask then can be placed on top of that, which sits on the pins of the main piece. The jig device then has a front mask and a back mask that come down on the top and bottom of the wafer such that both sides can be exposed simultaneously. The front and back then can be exposed at the same time, so that after baking the wafer is ready to etch.

[0037] Such a process can be used to form a set of parallel slots on the front and baclc of the wafer, although some einbodiments might utilize only slots on the front or back of the wafer.
A pattern region for the slots in accordance with one einbodiinent is shown in FIG. 3(a). As can be seen in the figure, the slots are not fonned from a rectangular region, but from a pattern region 304 shaped to utilize substantially all of the material of the workpiece 302 (such as a wafer or an ingot). Using a rectangular pattern with a round worlcpiece, for example, results in a substantial amount of the material of the worlcpiece being wasted.
Using a pattern that substantially matclies the size and the shape of the workpiece allows for long, thin slots to be formed that run approximately the width of the worlcpiece, so that almost all the material of the workpiece is used. This also results in a substantial increase in the surface area generated from a wafer, drastically increasing the active surface area that can be obtained for cells from a single wafer.

[0038] In this example, where the worlcpiece is a silicon wafer having a circular shape, the pattern region for the slots is substantially circular, corresponding to an outer edge of the workpiece. This correspondence allows a majority of the material of the workpiece to be used in fonning the slots (and the resultant strips of material). In one embodiment, at least 80% of the material of the workpiece is used in the patterning region. The amount of material used can depend on the material of the workpiece and the thickness of the workpiece, as enough material may need to be kept around the edge of the wafer, unetched, in order to provide a framework to hold the workpiece in one piece without breaking.

[0039] In the pattern region 304, the pattern for the individual parallel slots can be formed as shown in the enlarged view of a portion of the workpiece 302 in FIG. 3(b).
As can be seen, groups of adjacent slots are etched to go substantially to the edge of the workpiece. The slots in this example have 120 m nominal spacing, with 25 m openings. The resulting bars then typically are on the order of about 70 m or less in thickness after etching through the wafer. In some embodiments, at least one dividing bar 306, or stabilizer bar, is formed in the wafer during the etch process (such as by altering the mask used to etch the slots). As shown, this dividing bar 306 can be substantially peipendicular to the individual parallel slots 304.
Dividing bars can be formed down a center of the wafer, and/or at regular intervals across the wafer. These bars divide the wafer up into sections, so that the individual slots do not run the entire length of the wafer. This not only helps prevent the individually formed bars from breaking, but also reduces the effects of misalignment of the etched slots.
The dividing bars therefore reduce the need for the tolerance of the long slots to be accurately aligned to the crystal orientation. Additional sectioning further reduces the need for tight tolerances.

[0040] In other einbodiments, additional layers of materials can be used to fonn support structures as in existing processes, such as by adding a layer of oxide or nitride then etching to create a support device for a series of bars. Fonning the dividing bars as part of the slot etching process, however, saves the extra step, material, and complexity.
Further, the use of dividing bars formed during the slot etch step helps to reduce tolerances that are tough to obtain as discussed elsewhere herein.

[0041] A potential disadvantage to utilizing a dividing bar is that some of the wafer then becomes unusable for cells. The etch down through the wafer typically will be somewhat slanted, so that a small region down the middle (or at other intervals) of the wafer is lost.
There are 25 in wide slots in one example. When .the formed bars are eventually cut, such as along the shown cutting lines 308, to forin the individual cells, cutting lines 308 typically are placed on either side of the divider bar to ensure that the angle of material formed by the etch from the dividing line 306 does not affect the final shape of any of the individual cells.
This further reduces the yield of the wafer.

[0042] After the front and back of the device are patterned for a deep etch procedure, and the patterned resist is developed and baked by an appropriate developing and baking procedure, the exposed nitride layer can be etched down to the silicon. The resist is then removed. The front and back patterns are substantially identical and aligned such that the front and back slots line up as discussed above. In an alternate embodiment, a silicon dioxide layer is deposited over the nitride. The oxide layer is etched with a hydrofluoric acid wet etch, then the nitride layer uses the oxide layer as a mask and is then wet etched using a hot phosphoric acid.

[0043] The device then can undergo a deep etch in a wet bath, such as an anisotropic wet etching bath using a solution of 40% in weight of potassium hydroxide (KOH) in water.
Optionally isopropyl alcohol may be added to improve the surface quality of the silicon surfaces. This etch can go from one direction, such as the front of the wafer, all the way through the wafer, or can start at the front and the back (using the nitride mask on both sides) of the wafer and meet in the middle. By starting at both sides, the etch can take less time and there can be less undercutting.

[0044] The deep etching can be critical in soine embodiinents. When using a solution such as a relatively hot KOH solution, there can be a number of issues with a wet etch. For exainple, uneven etcliing can produce cells of varying perforinance. Further, the front and back etches inust be aligned to meet within a small tolerance.

[0045] The etching process (which can include any of a number of otller etching processes than a KOH wet etch) can create a number of slots through the wafer. An advantage to using substantially square cells, instead of elongated strips as in the prior art, is that virtually the entire wafer can be used. When using long strips that inust all be of the same size, the useable area of the wafer is effectively a square, which means that about half of a round silicon wafer is wasted in prior art systems. When using rectangular cells, the slivers etched into the wafer that subsequently are diced into individual cells can be of varying length. The resulting cells can be small, such as on the order of about 40mm or less, and in some embodiments on the order of 6mm or less in length, and can have an edge ratio of 20:1 or less. Many existing processes would not desire such small cells, as the pick and place tools used to place cells in existing systems would require too much time to assemble a panel of cells. Using a parallel assembly tool as described herein, however, a rapid asseinbly of modules of such cells can be obtained that is both economical and practical.

[0046] The slivers formed can extend over almost the entire length of the wafer, leaving only a thin rim around the edge, as well as any supporting structures needed to hold the slivers parallel. This can provide almost a 2X improvement in material usage.
In one embodiment, a typical 2mm x 150mm diaineter wafer, with a 100 m etch pitch, can produce over 84,000 square or slightly rectangular cells.

[0047] FIG. 4 shows steps of an exemplary method 400 for forming a sliver to be used in forining photovoltaic cells including some of the steps discussed above. In this method, a workpiece of a crystalline material is obtained, the material being of a high purity and having a selected doping 402. The workpiece is oriented according to a known crystal orientation of the material 404. At least one mask layer, such as a silicon nitride mask layer, is deposited on the front and back of the workpiece with a pattern that covers substantially all sides of the workpiece 406. A resist material is then applied to the front and the back of the workpiece 408. The resist on the front and back of the workpiece then is exposed and developed, such that a set of parallel slots is formed in both the front and back of the wafer, with the slots extending substantially from one edge of the workpiece to the other 410.
During the etch step, at least one dividing line also can be formed as aiscussect anove. Atter any necessary developing and/or baking, the workpiece can undergo an etch of the mask layer(s) then a deep etch in order to etch through the worlcpiece, thereby fonning a series of parallel bars in the workpiece 412. After the etching, any remaining resist can be reinoved 414. A series of additional steps for various einbodiments further process the narrow regions into devices that are substantially completed in forining photovoltaic devices. Then the bars can be diced to form slivers 416.

[0048] Once the slivers have been formed in the wafer as a result of the deep etch, it can be desirable in at least some einbodiments to texture one or both of the sides of the slivers. In one approach, a layer such as a very thin layer of nitride or other masking material is deposited, which is thin enough that coverage of the underlying silicon is not coinplete, and many small openings are left. An isotropic etch of the underlying silicon then creates cavities in the areas under the openings in the mask, thus texturing the silicon surface. Texturing can be beneficial in that texturing tends to bend the incident light rays so the rays take a longer path through the cell, which can improve the efficiencies of the resultant cells. Texturing can add an additional cost, however, which can be balanced with the amount of improvement obtained.

[0049] A POC13 diffusion step, or similar process step, can be used to form a layer having a doping opposite to the bulk doping of the bulk silicon, thereby establishing the diode region across the whole surface of the device. This can be seen, for example, in the cross section of FIG. 1. In one embodiment, POC13 and oxygen are flowed in as a gas at atmospheric pressure, norinally at high temperature anywhere from approximately 800- 1150 C. By properly mixing the gases for the POCl3 diffusion, the phosphorous can be diffused into the silicon and a phosphorus glass (PSG) can be built up on the surface of the silicon. The POCl3 diffusion creates different doped regions 106 and 108 in the cells, namely the front and back of the cells or the sidewalls of the slivers formed by the deep etch. The POC13 diffusion can form a glass or glaze on the device that can be removed from the top and bottom of the device where the contacts are to be placed, as the POC13 and oxygen can regrow some oxide on the top and bottom surfaces - the PSG. At this point, more measurements of the diode properties can be made to measure properties of device.

[0050] During the POC13 deposition step, it is important to leave the original nitride mask in place to prevent the POC13 from depositing on the narrow regions of the edge of the cells.

[0051] To reduce reflections from the surface or Lne aevlce, a iayer oi inatenai aesignea to be an anti-reflection coating, or ARC, may be deposited. After a KOH or other deep etch, the surface can be relatively smooth. When used in an application such as a solar cell, some of the liglit incident on the cell will be reflected from the front and back surfaces. These reflections can be uildesirable for various applications. One way to reduce the amount of reflection is to deposit an ARC. In the case of using POC13 to fonn the junction, by appropriate additions of oxidizing materials during or inunediately after the deposition, a layer of ARC may be deposited. A typical depth is 1000A for a dielectric substantially consisting of silicon dioxide.

[0052] In place of a phosphorus glass (PSG) ARC or silicon dioxide ARC, a silicon nitride ARC can be deposited on the cell surfaces. The PSG and remaining nitride is stripped and a layer of 750A silicon nitride can be added at this stage to act as an ARC.
Such a nitride ARC
can have near ideal properties, with reflection losses as low as 1%. Other approaches to reducing reflection can be used, such as flowing a material of different optical indices into the space between the cell surface and any other optical interface such as may appear in the construction of the photovoltaic module.

[0053] The bars, or slivers, then can be diced into the individual cells.
Since attempting to dice the sliver into rectangular cells, or "squivers," can destroy the slivers, an additional set of steps can be used to prevent dainage to the slivers. In one embodiment, the structural integrity of the wafer slivers can be improved by filling the gaps between the slivers with a material such as a wax. A wax such as CrystalBond can be easily removed and "melts" at a moderate teinperature, such that the wax can easily be flowed into the wafer to fill the gaps or cavities. The wax allows the slivers to be diced or sawed into individual cells without damage. The wax then can be removed in acetone at room temperature, which dissolves the CrystalBond and leaves the cells.

[0054] Other waxes, can be used, but typically require a high temperature heating process in a noxious solvent. Otlier polymers or flowable materials can be used as well, such as polymers and low-melting-point materials. Any type of appropriate, selectively removable filler can be used to fill the gaps in the deep-etched wafer. In other embodiments, the slivers can be adhered to what is referred to in the industry as "blue tape,"
typically used to hold wafers. The slivers can be diced while mounted on blue tape, or another adhesive material, or when positioned between layers of tape. If an acinesive inatenai is used on both sides of the sliver, only the inaterial on one side may be cut.

Pccnel Assenably [0055] Once the individual cells are fonned, additional process steps can be used to form a panel or other photovoltaic device using the cells. In one embodiinent, an assembly fixture with a rectangular grid pattern consisting of raised edges on a flexible substrate. The flexible substrate can be any appropriate substrate, such as a polyester film such as Mylarg available from DuPont of Wilinington, DE. The raised edges inay be inade of epoxy paint, metal, or stamped into the MylarV. In another embodiment, the fixture is made from printed circuit board material and the raised areas are plated conductors.

[0056] In another embodiment, such as for substantially parallel groupings of cells, a conductive substrate can be used, such as a substrate of stainless steel. The conductive substrate can include insulators that mask off the regions that are not desired to be conductive. Such a substrate can be used in a case where the backside will all be connected in parallel.

[0057] In one embodiment, cells 502 can be loaded onto the substrate using a dry vibratory process. In such a process, the die can be packaged randomly, or in strips or lots, and can be dry flowed over the assembly fixture grid 500, such as is shown to fill in a small section of the grid in FIG. 5, although it should be understood that the cells can be flowed to fill in the entire grid or selected sections of the grid. The die can be flowed with a small amount of vibration, and flowed into the target receptacles in the assembly fixture grid. There can be a slight inclination to the surface of the assembly fixture grid in order to allow gravity to assist the flow of cells. Such a process can be used to assemble large panels of these cells in a quick and relatively inexpensive manner.

[0058] However, conventional dry asseinbly tools may not work for this process. As the cells are very thin, and the ratio of surface area to mass is high, the cells have a tendency to stick to the surface of the assembly jig. Normal rotational motions of the jig are insufficient to detach the die from the surface. The use of an impulse vibratory assembly tool, which imparts a sudden deceleration in the motion at periodic intervals, can break this stiction force and enable rotational motion of the die such that they can then assemble into the grid pattern.

[0059] In a process in accordance with one eiricoaiment, tne individual cells are fortned into a panel using sub-modules, which can be any appropriate size for convenience such as 4"x4" to 8"x9" sub-modules. The cells can be placed in a parallel grouping, then placed in series to create any desired voltage. In one example, 4"x4" cells are formed in parallel, producing roughly 0.5V, or 8"x9" cells formed that are two 0.5V cells in series. These are roughly equivalent to two 6" wafers in series that are conventionally built.

[0060] In an alternate einbodiment, a nuinber of cells can be connected in series, then groups of these cells connected in parallel to form higher voltage arrays. An advantage to connecting serial groups in parallel is that the loss of a cell normally results in a shorted connection. If there is a long string of cells, such as twenty cells at 0.5V
each, a cell missing from a I OV string of cells would result in the voltage dropping to 9.5V. If, however, that string is connected in parallel with another string, then the average output of those strings will be somewhere between 10V and 9.5V. In another example where a large array is 0.5V, a shorted connection for one cell can result in pulling the entire array down to almost no output. "Serial-parallel" arrays thus have some advantages in that sense.

[0061] In this exainple, borosilicate glass is used as a substrate, although other appropriate substrates could be used, such as glazed ceramic tile, etc. Borosilicate has an advantage that its thermal expansion coefficient is very low, almost the same as silicon, thereby closely matching the thermal expansion of silicon and glass. A reason for using that kind of glass is that to fire some of these pastes, the system has to be elevated to a relatively high temperature, such as about 700 C. Other types of glass such as soda lime glass will start to flow at lower temperatures, and has a relatively high thermal expansion coefficient, so when attaching the cells to conventional glass and raising the cells up to those high temps, any cells that are locked will tend to crack or break upon cooling down due to the tremendous force applied on the cells.

[0062] Initially, a silver paste layer is deposited on the substrate, which becomes a tabbing paste. When making the final modules, tabbing conductors can be soldered from one sub-module to another and interconnected in series by soldering to the silver paste layer. The silver paste is places on the glass and fired at its firing temp, which is about 650-700 C in one example.

[0063] In one embodiment, a ring of insulator paste is applied in the areas under each cell and dried. A pattern of aluminum paste is then applied over the silver paste, such as by printing. While still wet, this substrate is aligned ana piacea over ine gna alignea ctie. '1 ne wet paste sticks to the die and removes it from the asseinbly jig. This asseinbly is allowed to dry at low teinperature. A filler dielectric paste is then printed that fills the space between the cells, primarily in the area which will later have conductors printed over it.
This paste is then dried. A silver paste, which is capable of penetrating the ARC when fired, is printed in a thin line over the top of the cells, dried, then the asseinbly fired at high temperature such as 700C.

[0064] At this point the cells become functional as energy conversion devices and can be tested.

[0065] In an alternate embodiment, a low teinperature silver paste, such as a thennoplastic silver or tin-silver solder paste, is printed over the penetrating silver paste, to connect the top conductors to adjacent cells, then cured or fired.

[0066] Once diced into individual square or rectangular cells and assembled into a sub-module, cells made from a wafer such as the exainple wafer presented above, with a typical 20% efficiency, can produce over 67 watts of power from full solar irradiation. A similar volume of single crystal silicon material cut into conventional solar cell wafers with the saine efficiency from 5 wafers, for example, would produce about 17 watts. This results in almost a 4X improvement in power from the same amount of silicon.

[0067] Another advantage of such a process is that the above described process steps, although similar in complexity to the processing needed for conventional cells, need only be performed on one wafer, whereas a similar processing inust be performed on as many as twenty wafers to obtain devices of the same output power. This results in additional savings in the processing costs.

Second Exemplcafy Formation Approach [0068] An exemplary process in accordance with another embodiment can produce a photovoltaic cell assembly 600 as shown in FIG. 6. As discussed below, such a cell has a bulk layer 602 with an n-type region 606 on the top and a p-type region 604 on the bottom of the wafer. It should be understood that descriptions such as "top" and "bottom" as used herein are used for purposes of clarity and explanation, and should not be construed as a limitation on an actual orientation of any embodiment. The cell also is shown to have a substrate 608 and opposing POC13 layers 610, 612.

[00691 The process starts with a rectangular warer ot <l,i,u> onentect silicon. '1'he silicon can be of high purity, doped with an n- or p-type dopant, and/or in the form of a wafer that is 21nin thiclc and 150inm in diameter, for exainple. The wafer can be cleaned using an appropriate process, such as a piranha cleaning process. A spin-on glass (SOG) procedure can be used to create a boron-doped SOG contact region on the top of the wafer. The wafer then can be placed in a furnace or diffusion oven for appropriate rainp and dwell periods, as known in the art, then reinoved from the f-urnace where the SOG can be etched away, such as by using a Buffered Oxide Etch (BOE) solution. The BOE etch typically is started within 30 minutes of completion of a hard balce of the wafer. The sheet resistivity of the wafer then can be measured. A similar process can be used to create a phosphorus-doped SOG
contact region on the bottom of the wafer, with subsequent baking and etching steps.
The resistivity of the diffused layer then can be measured, as well as the diode properties (through the wafer). Since there are two oppositely doped regions on opposing sides of the bulk silicon, the diode properties through the wafer can be measured.

[0070] The SOG phosphorus on the bottom of the wafer can be an opposite polarity doped region to the SOG boron region. In one einbodiment, both SOG regions can be spun on at the same time, or approximately the saine time. The furnace drive for the two SOG
regions then could be done simultaneously. While such an approach can save time and money, there may be some contamination issues to be addressed.

[0071] The crystal silicon can come with a relatively low base resistivity, but the contact regions formed on the top and the bottom of a thick silicon wafer can be of much lower resistance. In one embodiment, the resistivity of the contact regions can be in the range of several ohms per square, where existing systems may only get to tens of ohms per square.
Since a small contact is being used that is going to extend over a large region of the device, such as a small metal device connected to a broad, doped contact, a lower resistance contact can be needed to the doped region.

[0072] A nitride layer can be deposited on each side of the device. The wafer then can be prepared for photoresist deposition, such as by applying a Hexamethyldisilazane (HMDS) primer to serve as an adhesion promoter for photoresist. The resist then can be spun on the front side of the wafer. A pattern which will create a via, etched through the top nitride, is exposed in the top resist. The pattern is transferred to the nitride, but the nitride etch is not extended all the way through the nitride, but more typically %2 of the thickness of the nitride.

A similar via pattern is exposed and etched on the nacx siae ot tne water, but the via slots 702 are made to align in between the slots made on the top of the wafer as shown in the side view 700 of FIG. 7. Again, the nitride etch is only extended part way through the wafer as the nitride layer is still needed. As in the previous embodiment, an oxide layer may be deposited over the nitride layer to allow a wet etch process to transfer the resist pattern to the nitride layer.

[0073] The top of the device then can be patterned for a deep etch procedure, with the patterned resist being baked by an appropriate baking procedure. The exposed top nitride layer can be etched down to the silicon, and the resist subsequently removed.
A similar procedure can be used for the bottom of the wafer, with the wafer being prepared for the resist deposition using a solvent based priming procedure, such as an HMDS
priming procedure, with the resist then being spun on the front side of the device and the bottom of the device being patterned for deep etch. The resist can be baked and the bottom nitride layer etched down to the silicon. The resist then can be removed.

[0074] In a process in accordance with another embodiment, the resist can be applied to the top and bottom of the wafer, with patterning being done substantially simultaneously. For example, the wafer can be placed in a jig device with a mask that can come down on the top and bottom such that both sides can be exposed simultaneously. The resist can be developed before baking. Such processing can be used for both the via etch pattern and the deep etch pattern.

[0075] The device then can undergo a deep etch in a wet bath, such as an anisotropic wet etching bath using a solution of 40% in weight of potassium hydroxide (KOH) in water. This etch can go from one direction, such as the front of the wafer, all the way through the wafer, or can start at the front and the back (using the nitride mask on both sides) of the wafer and meet in the middle. By starting at both sides, the etch can take less time and there can be less undercutting.

[0076] The deep etching can be critical in some embodiments. When using a solution such as a relatively hot KOH solution, there can be a number of issues with a wet etch. For example, uneven etching can produce cells of varying performance. Further, the front and back etches must be aligned to meet within a small tolerance.

[0077] The etching process (which can include any of a nunlber of other etching processes that a KOH wet etch) can create a number of slots through the wafer. An advantage to using substantially square cells, instead of elongated stnps as in tne prior art, is that virtually the entire wafer can be used. When using long strips that are all of the same size, the useable area of the wafer is effectively a square, which means that about half of a round silicon wafer is wasted in prior art systeins. When using rectangular cells, the slivers etched into the wafer that subsequently are diced into individual cells can be of varying length. As such, these slivers can extend over almost the entire length of the wafer, leaving only a thin rim around the edge, as well as any supporting structures needed to hold the slivers parallel. This can provide almost a 2X iinprovement in material usage. In one embodiment, a typical 2mm x 150mm diaineter wafer, witli a 100 in etch pitch, can produce over 84,000 square or slightly rectangular cells.

[0078] As described previously, a texturing process can be employed to reduce reflections.
A POCl3 diffusion step, or similar process step, then can be used to form a layer having a doping opposite to the bulk doping of the bulk silicon, thereby establishing the diode region across the whole surface of the device. The POCl3 diffusion creates different doped regions in the cells, namely the front and back of the cells or the sidewalls of the slivers formed by the deep etch. The POCl3 diffusion can form a glass or glaze on the device that can be removed from the top and bottom of the device where the contacts are to be placed, as the POCL can regrow some oxide on the top and bottom surfaces. At this point, more measurements of the diode properties can be made to measure properties of device.

[0079] As described previously, the PSG from the POCl3 diffusion can be designed to create an ARC layer. Alternately, the PSG can be removed and a thermal oxide of a similar thickness or other materials added to form the ARC.

[0080] The remaining nitride in the via slots can then be etched, such as by using hot phosphoric acid as discussed above. The nitride is etched down to the silicon.
This etch also can remove any overhanging nitride of the nitride deep etch mask.

[0081] In one embodiment, metal contacts are screen printed on the top and bottom of the wafer, being aligned and printed into the via slots. The p-doped contact region can be printed with an aluminum or silver or combination silver/aluminum paste. The n-doped contact region can be printed with a silver paste.

[0082] In an alternate embodiment, the metal contacts are printed as a part of the assembly process. In yet another embodiment, the n-doped contact region vias are not patterned and etched. Instead, a silver paste capable of firing through the nitnde layer is employed to make contact with the underlying heavily doped contact region.

[0083] In still another einbodilnent, the p-doped contact region vias are not patterned and etched. Instead, an aluminum or combination aluininurn/silver paste capable of firing through the nitride layer is einployed to make contact with the underlying heavily doped contact region. In the case where a POC13 step was einployed to form the front/back diode regions, care inust be exercised to prevent this paste step from allowing paste to bleed to the region where the POC13 was deposited, or the device may be shorted.

[0084] Once the contact regions are formed, the slivers can be diced into the individual cells as described previously. A panel then can be forined as described above.
For exainple, in a process embodiment which employs contacts having both metal contacts printed on the wafer prior to dicing, an advantage is created in that subsequent painel assembly processes can be employed which only require low temperatures to process. This enables the use of many more types of substrates to be used, such as plastics.

[0085] Different classes of substrates can be used to support the cells, such as thin flexible substrates and relatively thicker substrates that are more rigid. These rigid substrates can be, for exainple, 1/16" to 1/" acrylic sheets cut to the size of the panels of final product. The thin, flexible materials can be placed in a subassembly that can have a front and/or back for supporting and protecting the assembly. There may be advantages for certain applications to having a flexible device.

[0086] The separated cells are assenlbled onto an assembly fixture grid as has been previously described. Separately, a substrate is first printed with a pattern of lines of insulators, such as epoxy paint. Then in between the insulator lines, and of a slightly greater thickness, are printed a pattern of lines of conductors, for example using a low temperature thermoplastic silver paste or epoxy silver paste. The insulator lines prevent the conductor lines from bleeding together and form a stop when the cells are placed over the conductors.
While the conductor paste is still wet, the substrate is placed over the assembly fixture grid with the assembled cells. The wet paste sticks to the cells and allows the cells to be transferred to the substrate. The paste is then cured or dried.

[0087] In an alternate embodiment, an additional step of printing small dots of theimoplastic or epoxy silver pastes is employed to print over the cells at the via edges, to ensure that a connection is made from the contact regions on the cells to the underlying metal interconnect lines.

Third Exernplary Fof-fnation Approach [0088] In a process for forming cells in accordance with another einbodiment, the cells are fabricated in a syinmetric square or rectangular pattern out of a crystalline material such as <1,1,0> silicon crystal. An exainple of such a photovoltaic cell 800 is shown in FIG. 8. The cell in this exanple is front/back and side/side symmetric, such that the front and rear views are substantially identical. This particular view shows the bulk material 802, with a thickness that is determined primarily by the thickness of the silicon wafer or other material used to forin the die. It can be desired for some einbodiinents that the thickness be greater than that of a standard silicon wafer. This cell 800 has upper 804 and lower 806 doped regions, as will be discussed below, as well as a plurality of contact regions 808, 810, 812.

[0089] In a cell in accordance with one embodiment, the top region 804 is a boron.doped region and the bottom region 806 is a phosphorus doped region. This figure is not to scale, as each of these regions would typically be thinner relative to the thickness of the bulk silicon 802. While in at least some einbodiments it is preferred that the wafer be thicker, as having larger cells can be more efficient and require less processing, thicker wafers also can require longer etches, which can result in an undesirable amount of undercutting. In one embodiment the thickness of the bulk silicon can be on the order of about 1-2mm.

[0090] A process for making such a cell, in this case a square or rectangular cell, in accordance with one embodiment starts with a wafer of <1,1,0> oriented silicon with properties as discussed above. The wafer can be cleaned using an appropriate process, such as a piranha cleaning process. A spin-on glass (SOG) procedure can be used to create a boron-doped SOG contact region on the top of the wafer. The wafer then can be placed in a furnace or diffusion oven for appropriate ramp and dwell periods, as known in the art, then removed from the fiirnace where the SOG can be etched away, such as by using a Buffered Oxide Etch (BOE) solution. The BOE etch typically is started within 30 minutes of completion of a hard bake of the wafer. The sheet resistivity of the wafer then can be measured. A similar process can be used to create a phosphorus-doped SOG
contact region on the bottom of the wafer, with subsequent baking and etching steps. The resistivity of the diffused layer then can be measured, as well as the diode properties (through the wafer).

Since there are two oppositely doped regions on opposing sides of the bullc silicon, the diode properties through the wafer can be measured.

[0091] The SOG phosphorus on the bottom of the wafer can be an opposite polarity doped region to the SOG boron region. In one embodiment, both SOG regions can be spun on at the saine tiine, or approxiinately the same time. The furnace drive for the two SOG regions then could be done simultaneously. While such an approach can save time and money, there may be some contamination issues to be addressed.

[0092] The crystal silicon can come witll a relatively low base resistivity, but the contact regions formed on the top and the bottom of a thick silicon wafer can be of much lower resistance. In one embodiment, the resistivity of the contact regions can be in the range of several ohms per square, where existing systems may only get to tens of ohms per square.
Since a small contact is being used that is going to extend over a large region of the device, such as a small metal device connected to a broad, doped contact, a lower resistance contact can be needed to the doped region.

[0093] A nitride layer can be deposited on each side of the device. The wafer then can be prepared for photoresist deposition, such as by applying a Hexamethyldisilazane (HMDS) primer to serve as an adhesion promoter for photoresist. The resist then can be spun on the front side of the device. The top of the device can be patterned for a deep etch procedure, with the patterned resist then being baked by an appropriate baking procedure.
The exposed top nitride layer can be etched down to the silicon, and the resist subsequently removed. A
similar procedure can be used for the bottom of the wafer, with the wafer being prepared for the resist deposition using a process such as an HMDS priming procedure, with the resist then being spun on the front side of the device and the bottom of the device being patterned for deep etch. The resist can be baked and the bottom nitride layer etched down to the silicon.
The resist then can be removed.

[0094] In a process in accordance with another embodiment, the resist can be applied to the top and bottom of the wafer, with patterning being done substantially simultaneously. For example, the wafer can be placed in a jig device with a mask that can come down on the top and bottom such that both sides can be exposed siinultaneously. The resist can be developed before baking.

[0095] The device then can undergo a deep etch in a wet bath, such as an anisotropic wet etching bath using a solution of 40% in weight of potassium hydroxide (KOH) in isopropyl-alcohol, which tends to slow down the etch. This etch can go from one direction, such as the front of the wafer, all the way through the wafer, or can start at the front and the baclc (using the nitride mask on both sides) of the wafer and meet in the middle. By starting at both sides, the etch can take less time and there can be less undercutting.

[0096] The deep etching can be critical in some einbodiinents. When using a solution such as a relatively hot KOH solution, there can be a number of issues with a wet etch. For exainple, uneven etching can produce cells of varying perfonnance. Further, the fiont and back etches must be aligned to meet within a small tolerance.

[0097] The etching process (which can include any of a number of other etching processes that a KOH wet etch) can create a number of slots through the wafer. An advantage to using substantially square cells, instead of elongated strips as in the prior art, is that virtually the entire wafer can be used. When using long strips that must all be of the same size, the useable area of the wafer is effectively a square, which means that about half of a round silicon wafer is wasted in prior art systems. When using rectangular cells, the slivers etched into the wafer that subsequently are diced into individual cells can be of varying length. As such, these slivers can extend over almost the entire length of the wafer, leaving only a thin rim around the edge, as well as any supporting structures needed to hold the slivers parallel.
This can provide almost a 2X improvement in inaterial usage. In one embodiment, a typical 2mm x 150mm diameter wafer, with a 100 m etch pitch, can produce over 84,000 square or slightly rectangular cells.

[0098] Once the slivers have been formed in the wafer as a result of the deep etch, it can be desirable in at least some embodiments to texture at least one of the sides of the slivers. After a KOH or other deep etch, the surface can be relatively smooth. When used in an application such as a solar cell, some of the light incident on the cell will be reflected from the front and back surfaces. These reflections can be undesirable for various applications.
One way to reduce the amount of reflection is to texture at least one of the surfaces. In one approach, a layer such as a thin layer of nitride or other masking material is deposited, which is then wet etched and stripped in order to texture the surface. Texturing can add an additional cost, however, which can be balanced with the amount of improveinent obtained. Other approaches to reducing reflection can be used, such as flowing a material into space between the cell surface and any other optical interface.

[0099] A POCL diffusion step, or similar process step, can be used to form a layer having a doping opposite to the bulk doping of the bulk silicon, thereby establishing the diode region across the whole surface of the device. This can be seen, for example, in the cross section 900 of FIG. 9. The POCL diffusion creates different doped regions 902 in the cells, nainely the front and baclc of the cells or the sidewalls of the slivers formed by the deep etclh. The POCL diffusion can forin a glass or glaze on the device that can be removed from the top and bottom of the device where the contacts are to be placed, as the POCL can regrow some oxide on the top and bottom surfaces. In order to get the doping to extend to a desired depth and reduce crystal defects, at least one redrive step can be used as known in the art. A
redrive step can be perfonned by soaking in a f-urnace, or can be coinbined with a dry or wet thennal oxidization step to passivate the exposed areas of the wafer. This can help to minimize crystal defects. At this point, more measurements of the diode properties can be made to measure properties of device.

[0100] A mask such as a shadow mask can be used to fonn the contact regions for the device. A shadow mask is a pattern in a material such as silicon or metal that has openings, grooves, or other patterned features formed therein. The shadow mask can be brought down over the top and/or bottom of the device. The shadow mask can be used with an etching process, such as sputter etching, to remove any insulators, such as thermal oxide, under the open area of the mask. The shadow masks can be used to deposit a metal such as aluminum on the top and bottom of the device in order to form the contact regions 808, 810, 812. A
combination of metals also can be used, such as aluminum on one side of the device and Cr/Ni on the other.

[0101] Once the contact regions are formed, the slivers can be diced into the individual cells. Since attenzpting to dice the sliver into square cells, or "squivers,"
can destroy the slivers, an additional set of steps can be used to prevent damage to the slivers. In one embodiment, the structural integrity of the wafer slivers can be improved by filling the gaps between the slivers with a material such as a wax. A wax such as CrystalBond can be easily removed and "melts" at a moderate temperature, such that the wax can easily be flowed into the wafer to fill the cavities. The wax allows the slivers to be diced into individual cells without damage. The wax then can be removed in acetone at room temperature.
Other waxes can be used, but typically require a high temperature heating process in a noxious solvent. Other polymers or flowable materials can be used as well, such as polymers and low-melting-point materials. Any type of appropriate, selectively removable filler can be used to fill the gaps in the deep-etched wafer. In other einbodiments, the slivers can be adhered to what is referred to in the industry as "blue tape," typically used to hold wafers.
The slivers can be diced while mounted on blue tape, or another adhesive material, or when positioned between layers of tape. If an adhesive material is used on both sides of the sliver, only the material on one side may be cut.

[0102] When dicing the slivers, at least one notch can be cut in each die in accordance with one embodiment. These notches can help to ensure a desired alignment of the die in the final panel or device. In other einbodiments, the orientation is not important such that no notches are necessary.

Additional Assembly Processes [0103] Once the cells are fonned, additional process steps can be used to form a panel or other photovoltaic device using the cells. In one embodiment the cells are mixed with a fluid, with the slurry of cells and liquid then being flowed over a substrate. The substrate can be any appropriate substrate, such as a clear plastic ribbon in which depressions have been stamped to fit the cells. Different classes of substrates can be used to support the cells, such as thin flexible substrates and relatively thicker substrates that are more rigid. These rigid substrates can be, for example, 1/8" or 1/4" acrylic sheets cut to the size of the panels of final product. The thin, flexible materials can be placed in a subassembly that can have a front and/or back for supporting and protecting the assembly. There may be advantages for certain applications to having a flexible device.

[0104] A substrate ready to accept the cells can have a number of features, such as slots or indentations, formed therein. These slots/indentations can be made by stamping, using a frit or thin insulating material, or a conductor/interconnect, that would can create a frame for the cells. For instance, substantially square indentations can be stamped into a ribbon to hold cells in an array 1000, such as is shown in FIG. 10. The slots also can be vertical columns, or columns orthogonal to the plane of the substrate, such that when material is flowed in, the devices can stack on top of each other the vertical columns. For example, a slot might be 100mm in length by 2mm in width, such that die having dimensions of 2mm x 4mm can stack into this slot. In this case, the die can only load such that the long axis of the die matches the long axis of the slot. The die can stack one on top of each other until the slot is filled. In another example, the slot can have dimensions of 100mm in length by 4mm in widtli, where the die can stack such that the long axis of the die can align with the long axis of the slot. It also is possible, however, that the short axis of the die could align with the long axis of the slot, thereby forming undesirable gaps. In such a situation, an additional mechanism can be used to force the alignment of the die to a preferred orientation. The substrate also can have large openings into which the cells can flow and fill by staclcing.

[0105] The fraine surrounding the die can be fabricated of a material which, wllen heated, causes the fraine to reflow and flatten. The space between the frame and the die then can be reduced, thereby gripping and locking the die into position. For example, a defonnable material can be deposited onto a substrate that is to be used as the edge(s) of the slots. After the die are flowed into these slots, the slot edges can be heated in order to soften this ridge material, allowing the material to reflow around the die. This ridge material also can expand, further locking the cells into place. There are several other ways to load the die that will not be discussed herein but are known or would be obvious to one of ordinary skill in the art in light of the description herein.

[0106] The process of fluidic self assembly then can load the cells into most, if not all, of the available depressions in the ribbon. Approaches and materials used in many fluid assembly systems are known in the art, such as is described in U.S. Patent No.
6,623,579, entitled "Methods and Apparatus for Fluidic Self Asseinbly," to Smith, et al., which is hereby incorporated herein by reference.

[0107] In alternate embodiments, the cells can be loaded onto the substrate using a dry vibratory process. In such a process, the die can be packaged randomly, or in strips or lots, and can be dry flowed over substrate with a small amount of vibration, and flowed into the target receptacles in the substrate. There can be a slight inclination to the surface of the substrate in order to allow gravity to assist the flow of cells. Such a process can be used to assemble large panels of these cells in a quick and relatively inexpensive mamler.

[0108] In other embodiments, a combination of fluidic and vibratory processes can be used to load the cells onto the substrate. Where a fluid assembly is used, the fluid can be removed and the cells/substrate dried as known in the art. The fluid can be a simple liquid, such as de-ionized water, or can have any of a number of other desirable properties. For example, the liquid can have surfactant properties that improve the flow of the fluid and cells, and that improve the flow of the die over each other. The indentations in the substrate also can be patterned with a material that would give the die a particular attraction to that location, such that when a dies gets into that position the die tends to stay in that position.

[0109] The process of loading may be discrete, wherein the substrates are individual panels, or roll fed, wherein the substrate is a continuous ribbon of material fed througli the processing regions which supply the cells.

[0110] A cover sheet, which may have contact vias predrilled, can be laminated to the substrate to hold the cells in place. If the holes have not been pre drilled, the holes can be post drilled by laser or similar means. In some existing systems a backing is placed over the cells and holes drilled, but such a process would be difficult for long strips of the prior art, where the lamination rollers or other process components would tend to damage the long strips due to uneven pressure, etc.

[0111] The cells then can have a pattern of interconnect 1100 foi7ned as shown, for example, in FIG. 11. The interconnect can be silk screened, inkjet printed, or otherwise deposited to flow over and into the contact vias, such as using some form of conductive paste such as silver epoxy. Other techniques for depositing the interconnect, such as using a patterned roller, can be used as known in the art.

[0112] The conductive paste can be baked into a flexible but hard form, connecting the cells into groups which may have many cells in parallel, such as is shown in FIG.10. Some of those groups can be connected in series to raise the voltage of the ribbon to a higher level.
The ribbon then can be finally cut to form a coinpleted ribbon asseinbly.

[0113] In an alternate embodiment, a substrate can have interconnect already silk screened onto an interconnect substrate, such as FR4 printed circuit material, among many other possibilities. A pattern of square or rectangular depressions can be silk screened over the interconnect to forin regions into which the square or rectangular cells can be flowed. The substrate with cells then can be placed in a chemical bath that deposits a conductive material.
This conductive material bridges the contacts on the cells and the interconnect beneath. After deposition, the assembly can be rinsed and dried.

[0114] In another embodiment, the solar cells can be assembled using an interconnection matrix. An open weave matrix (such as may be similar to a window screen), for exainple, can be woven to precise dimensions that can substantially match the size of the squiver.
Adjusting the openings in the weave to match the dimensions of the squivers can provide a good fit with the squivers, and can substantially hold the squivers in place.
The matrix can be any appropriate interconnecting membrane, made of any appropriate material capable of fitting the squivers without damaging or contaminating the squivers. Such a weave can be used as a conductive interconnect and/or as a supporting structure. In one example, a conductive wire can be used on one axis of the ineinbrane, with an insulating wire used on the other axis. Using such an approach, many squivers can easily be wired in parallel. In another exainple, two (or more) different materials can be used to allow the squivers to self-align. These materials can be separately hydrophobic and hydrophilic, and can have a single axis of syininetry. In another example, an interconnect weave can be made with up to four different materials to provide multiple interconnects to each squiver. Using an open weave as an interconnect, even if only one connection is made, allows siinple screen printing to take place on the back and/or front of the squivers to provide an additional connection. Typically, only two connections are needed for solar module construction from individual solar cells.
[0115] Once diced into individual square or rectangular cells and assembled into a module, cells made from a wafer such as the exainple wafer presented above, with a typical 20%
efficiency, can produce over 67 watts of power from full solar irradiation. A
similar volume of single crystal silicon material cut into conventional solar cell wafers with the same efficiency from 5 wafers, for example, would produce about 17 watts. This results in almost a 4X improvement in power from the same amount of silicon.

[0116] Another advantage of such a process is that the above described process steps, although similar in complexity to the processing needed for conventional cells, need only be performed on one wafer, whereas a similar processing must be performed on five wafers to obtain the same device. This results in additional savings in the processing costs.

[0117] A key advantage of several embodiments is the use of a substantially square cell.
By placing two contacts on one side of a square cell and another contact on the other side, any orientation of the cell in a substrate indentation can be successfully operable. No matter which way a die is rotated or flipped, the die will always line up with the contacts that are associated with the correct polarity for making contact to the interconnects.
It also is possible to use only a single style of interconnect that goes over all these devices, such that no matter how each cell is rotated or flipped this particular contact layout will work.
This can greatly siinplify a fluid assembly process, for example, where it is only necessary to get a die to an indentation, irregardless of the orientation of that die.

[0118] In one example, a first set and a second set of spaced side contacts are used that allow for the orientation of cell to vary while still providing proper connection. The first set of side contacts are positioned differently than the second set of side contacts, such as with two side contacts on one side positioned opposite the gaps between three side contacts on the other side. If there are then five contact lines beneath the cell when positioned in a module, then the cell can be flipped either way and the contacts will still contact only the appropriate contact lines.

[0119] In other einbodiinents, the cells can be fabricated as slightly rectangular structures.
For example, structures with an aspect ratio of 1.5:1, 2:1, 3:1, or 4:1 may have certain advantages in various systems and/or applications. In such a situation, however, there is no complete symmetry. These die will not fit in just any rotation, but must match the orientation of the rectangular indentations of the indentations, for example, such that the self-assembly process can be longer and more difficult than for square cells. In the process of self assembly, however, the rectangular shape can ensure that the solar cell die will load in a preferred orientation, such as an orientation 1200 of 0 as shown in Fig 12 or 180 degrees (or depending on the orientation of the long axis, at 90 degrees or at 270 degrees). The die also can be flipped upside down, as the die is symmetric with respect to the Z
axis. Such an approach can allow the interconnect to be simplified, can require a fewer number of cuts of the processed wafer, and can substantially eliminate fill probleins.

[0120] In some embodiments, the cells can be fabricated with key slot(s) or protrusion(s) formed from conductive material(s) or insulator(s), in the die itself and/or in the substrate indentation. The slots can match the contact protrusions on the top and bottom of the die, as shown in the example 1300 of FIG. 13. In this way, the die can load into the indentations matching the slots. The die can be flipped over, but will always have the orientation which matches the key slot(s). In this embodiment, it is not necessary to have interconnect that can make contact to the top and bottom of the die, as the die cannot load with that orientation.
Only the three central interconnect lines are used in this embodiment.

[0121] Otlier embodiments can have inultiple slots and/or protrusions aligned along the edges of the die and the indentations in the substrate. These can be symmetric, allowing the die to orient normally or flipped over.

Other Cyystalline Materials [0122] Although many of the examples provided herein are described with respect to silicon of a certain orientation, it should be understood that there are a number of other materials and orientations that can be used as would be apparent to one of ordinary skill in the art in light of the teachings and suggestions contained herein. For example, cells could be built out of a material such as gennanium. Using such cells, a much higher efficiency multi-junction cell also could be formed by depositing many layers of different materials. An advantage of such an approach can be a large improvement in processing, such as a 20X
iinprovement in processing. For exainple, a wafer with a large ainount of surface area can be loaded along with a number of other wafers into a fi.i.rnace, and various gases can be flowed into the furnace to deposit the materials to build up the device. Presently, this is done for individual wafers, each of which only has a certain ainount of surface area.
In the saine slot where a thin wafer is placed can be placed a thiclc wafer, such as a wafer on the order of 2mm thick that can result in cells of about 2min in height or width. Such a process can end up using inuch more gas to fill up the larger surface area, but the tool itself can be a much smaller tool, can be less expensive, and can require many fewer runs. This then results in higher productivity and higher efficiency cells.

Optical Concentrator [0123] An additional benefit can be obtained when photovoltaic cells as discussed above are configured to work with an optical concentrator as known in the art. For example, a holographic pattern that functions as a multitude of lenses can be is stamped into the side of a clear plastic substrate, opposite a coluinn of square or rectangular cells 1400 as shown in FIG. 14. Such a concentrator can focus solar radiation onto the array of columns of cells.
Instead of using an array to cover a fall area, a device can include only columns or linear arrays 1402 of cells as in FIG. 14. This can reduce the number of cells needed and therefore the cost of the device. The example in FIG. 14 uses 1/ the number of cells needed for the same area of a system without the concentrator cells. The concentrator can focus solar radiation over a range of angles that the sun may have relative to the module, unlike conventional concentrators which may use Fresnel lenses. The concentrator itself can introduces losses, but for the example shown, with a 75% efficiency of the concentrator, the system can have an overall utilization of silicon that is 12X lower for the same power output than conventional silicon cells.

[0124] In some embodiments, photovoltaic materials which exhibit crystal structures which have etchants capable of preferentially etching at right angles to the surface of the material can be used. In some embodiments, dry etching processes such as a Bosch silicon etch process can be used to cut the wafer into segments. In some embodiments, a laser can be used to cut the photovoltaic material into segments. In some einbodiments, a narrow jet of high pressure liquid can be used to cut the photovoltaic material into segments.

[0125] It should be recognized that a nuinber of variations of the above-identified einbodiments will be obvious to one of ordinary skill in the art in view of the foregoing description. Accordingly, the invention is not to be limited by those specific einbodiinents and methods of the present invention shown and described herein. Rather, the scope of the invention is to be defined by the following claims and their equivalents.

Claims

1. A method of forming photovoltaic cells, coinprising:
depositing a mask layer on a substantially planar piece of crystalline material;
and etching the piece of crystalline material to form a plurality of substantially parallel slots in the crystalline material, the slots forming a plurality of substantially planar bars each extending substantially from one edge of the piece of crystalline material to the other edge of the piece along the direction of the bar, the width of each bar being substantially equal to a thickness of the piece of crystalline material.

2. A method according to claim 1, further comprising:
separating the bars from the piece of crystalline material; and dicing the bars to form a plurality of rectangular cells.

3. A method according to claim 1, wherein:
the crystalline material is selected from the group consisting of silicon, germanium, and gallium arsenide.

4. A method according to claim 1, further comprising:
forming a layer on each of the plurality of bars having a doping opposite a bulk doping of the respective bar.

5. A method according to claim 4, wherein:
forming a layer having a doping opposite a bulk doping of the respective bar includes performing POCl3 diffusion on the respective bar.

6. A method according to claim 2, further comprising:
forming contacts on a top and a bottom surface of each rectangular cell.

7. A method according to claim 2, further comprising:
forming contacts on opposing sides of each rectangular cell.

8. A method according to claim 7, wherein:
forming contacts on opposing sides includes forming a first set of contacts on a first side and forming a second set of contacts on a second side of each rectangular cell, at least one of the number and positions of each set of contacts being selected to provide for proper contact connections regardless of the orientation of the respective cell with respect to a connecting device.

9. A method according to claim 1, wherein:
the mask layer is used to form a non-rectangular region of parallel slots in the crystalline material.

10. A method according to claim 1, wherein:
depositing a mask layer includes depositing the mask layer on a substantially planar piece of <1,1,0> oriented silicon.

11. A method according to claim 1, further coinprising:
dicing the plurality of bars to form rectangular cells having an edge ratio of about 20:1 or less.

12. A method according to claim 1, wherein:
the mask layer includes a pattern region for forming the slots selected so that the resulting bars utilize at least 80% of the surface of the piece of crystalline material.

13. A method according to claim 1, further comprising:
depositing an anti-reflecting coating on a surface of each bar.

14. A method according to claim 1, further comprising:
texturing at least one surface of each bar.

15. A method according to claim 2, further comprising:
placing each rectangular cell on a substrate.

16. A method according to claim 15, wherein:
the substrate is at least one of a conductive substrate, a low temperature substrate, and a flexible substrate.

17. A method according to claim 15, further comprising:
depositing additional layers to form a multi-junction device.

18. A method according to claim 15, further comprising:
connecting at least a portion of the cells by a method selected from parallel, serial, parallel-serial, and serial-parallel connections.

19. A photovoltaic cell, coinprising:
a rectangular crystalline die including at least two oppositely doped regions forming a diode, the die having a width of about 2mm or less, a length of about 40 mm or less, and a thickness of about 100µm or less; and a pair of contacts placed on opposite edges of the crystalline die.

20. A photovoltaic cell according to claim 19, wherein:
the pair of contacts are placed on one of top and bottom edges of the die or opposing side edges of the die.

21. A photovoltaic cell according to claim 19, wherein:
the pair of contacts are part of a first set of contacts on a first edge of the crystalline die and a second set of contacts on a second edge of the crystalline die, the first edge being opposite the second edge, allowing the crystalline die to be placed in an array of substantially coplanar photovoltaic cells in any orientation.

22. A photovoltaic cell according to claim 19, wherein:
the rectangular crystalline die is substantially square.

23. A photovoltaic cell according to claim 19, wherein:
the rectangular crystalline die is formed from a substantially planar piece of <1,1,0> oriented silicon.

24. A photovoltaic cell according to claim 19, further comprising:
an anti-reflective coating on at least one surface of the crystalline die.

25. A photovoltaic cell according to claim 19, wherein:
at least one surface of the crystalline die is textured.

26. A solar module, comprising:
a substrate including an array of receptacles;
a plurality of rectangular photovoltaic cells positioned in the array of receptacles, each photovoltaic cell having a width of about 2mm or less, a length of about 40 mm or less, and a thickness of about 100µm or less, each photovoltaic cell further having contacts on two opposing edges of the photovoltaic cell; and an interconnect layout electrically connecting contacts of the plurality of rectangular photovoltaic cells.

27. A solar module according to claim 26, wherein:
the contacts are placed on a top and a bottom of each photovoltaic cell.

28. A solar module according to claim 26, wherein:
the contacts are placed on opposing side edges of each photovoltaic cell.

29. A solar module according to claim 28, wherein:
the contacts on a cell include at least one first contact on a first side edge and at least one second contact on a second edge, the first and second contacts being positioned at different edge locations so that each of the first and second contacts connects with a desired line of the interconnect layout regardless of the orientation of the photovoltaic cell in the respective receptacle.

30. A solar module according to claim 26, wherein:
the substrate is at least one of a conductive substrate, a low temperature substrate, and a flexible substrate.

31. A solar module according to claim 26, wherein:
the interconnect layout divides the plurality of photovoltaic cells in the array of receptacles into sub-modules.

32. A solar module according to claim 31, wherein:
the interconnect layout connects the photovoltaic cells in each module in parallel, and connects at least a portion of the sub-modules in series.

33. A solar module according to claim 31, wherein:
the interconnect layout connects the photovoltaic cells in each module in series, and connects at least a portion of the sub-modules in parallel.

34. A solar module according to claim 26, further comprising:
a laminate layer operable to hold the plurality of photovoltaic cells in the array of receptacles.