JP2009302308A - Method of manufacturing nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To keep the protection performance of a gate insulation film using a protective insulation film for enhancing reliability when a self-aligned contact structure is applied. <P>SOLUTION: Laminated films 6-10 are subjected to radical oxidation treatment to form a silicon oxide film 11 on the upper surface of a silicon nitride film 10 and on the respective side surfaces of the laminated films 6-10. After that, anisotropic etching treatment is performed so that the upper end 11a of the silicon oxide film 11 is aligned with the upper surface of a silicide layer 9 to expose the upper surface and the side surfaces of the silicon nitride film 10, and a silicon nitride film 13 is formed so as to cover the upper surface and the side surfaces of the silicon nitride film 10 and the upper end 11a and the side surfaces of the silicon oxide film 11, and then a contact hole DH is formed in a self-aligned manner. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device having a stacked gate electrode structure in which a floating gate electrode and a control gate electrode are sandwiched between gate insulating films, and a nonvolatile semiconductor memory device.

  In the technical field of nonvolatile semiconductor memory devices, design rules and element miniaturization have been strongly promoted. In general, a nonvolatile semiconductor memory device is a stack in which a floating gate electrode and a control gate electrode are sandwiched between a second gate insulating film and a cap insulating film is further stacked on a semiconductor substrate via a first gate insulating film. The gate electrodes are arranged in a matrix, and the source / drain regions are formed on the surface layer of the semiconductor substrate on both sides of the stacked gate electrodes (see, for example, Patent Document 1). According to the technique described in Patent Document 1, a gate barrier film made of a silicon dioxide film is formed along the side wall of the laminated gate electrode. Also disclosed is a form in which the contact barrier film is formed directly on the sidewall of the laminated gate electrode by a nitride insulating film.

  As shown in the technical idea described in Patent Document 1, in order to obtain electrical coupling with the source / drain regions formed in the surface layer of the semiconductor substrate, interelectrode insulation by BPSG is provided between the stacked gate electrodes. After embedding the film, a contact plug is formed between the plurality of stacked gate electrodes. With the recent reduction in design rules, the width of a plurality of adjacent memory cell gate electrodes and the interval between the gate electrodes have been remarkably narrowed. In order to form this contact plug, a self-aligned contact (SAC) structure is used. Applicable.

However, as disclosed in Patent Document 1, when the contact hole, which is a pretreatment for embedding the contact plug in the interelectrode insulating film, is formed by etching, the sidewall insulating film is also removed. As a result, a groove is formed along the side wall of the stacked gate electrode, and if the contact plug material is buried in the contact hole later, the contact plug material and the gate electrode come into contact with each other on the side surface, causing an electrical failure. There is also a risk that it will be inferior in terms of reliability. In addition, it is not preferable that the contact barrier film is formed directly by the nitride insulating film along the side wall of the gate insulating film because the reliability of the gate insulating film is inferior.
JP 2002-57230 A (0081 paragraph)

  The present invention relates to a method of manufacturing a non-volatile semiconductor memory device capable of improving the reliability while maintaining the protection performance of the gate insulating film by the protective insulating film when a self-aligned contact structure is applied, and the manufacturing An object of the present invention is to provide a nonvolatile semiconductor memory device manufactured by the method.

  According to one embodiment of the present invention, a plurality of floating gate electrodes, a plurality of second gate insulating films, a plurality of control gate electrodes, and a plurality of cap insulating films are sequentially stacked over a semiconductor substrate with a first gate insulating film interposed therebetween. Forming a plurality of stacked gate electrodes, and forming a first insulating film for gate protection so as to cover the upper surfaces and side surfaces of the plurality of stacked gate electrodes by radical treatment of the plurality of stacked gate electrodes. Forming a second insulating film with the same material as the cap insulating film so as to cover the first insulating film, the floating gate electrode, the second gate insulating film, the control gate electrode, and the cap insulating film Between the second insulating film and the inner side of the second insulating film up to a position above the upper surface of the second gate insulating film and not more than the height of the upper end of the control gate electrode. Etching Forming a sacrificial layer with a selectable material; and etching the second insulating film to a position below the height of the upper end of the control gate electrode and above the second gate insulating film. Exposing the upper portion of the film, and anisotropically forming the first insulating film so that the upper end of the first insulating film is below the upper surface of the cap insulating film and above the upper end of the second insulating film. Etching to expose the cap insulating film, forming a third insulating film of the same material as the second insulating film so as to cover the cap insulating film, and covering the third insulating film Forming an interelectrode insulating film with a highly selectable material at the time of etching with the cap insulating film, and the interelectrode insulating film under a condition having high selectivity with the cap insulating film The product is etched Forming a contact hole in a self-aligning manner while leaving the second insulating film so that a third insulating film covering the gate electrode covers the upper end of the second insulating film; and a contact plug in the contact hole Forming a step.

  One embodiment of the present invention includes a semiconductor substrate, a first gate insulating film formed over the semiconductor substrate, a plurality of floating gate electrodes formed over the first gate insulating film, and the plurality of floating floating electrodes. A plurality of second gate insulating films respectively formed on the gate electrodes, a plurality of control gate electrodes respectively formed on the plurality of second gate insulating films, and a part on the plurality of control gate electrodes A plurality of stacked gate electrodes each formed of a plurality of cap insulating films formed by removing upper shoulder portions in a cross section; a plurality of floating gate electrodes and a plurality of second gate insulators constituting the plurality of stacked gate electrodes; Sidewall insulating films formed along the sidewalls of the film, each having a top end located below the vicinity of the upper surface of the control gate electrode and formed by a silicon oxide film; A barrier film formed between the sidewall insulating films of the plurality of stacked gate electrodes so as to cover the sidewall insulating film; and a contact plug formed between the sidewall insulating films of the plurality of stacked gate electrodes. And a contact plug whose lower side surface is formed along the missing surface of the cap insulating film and the outer surface of the barrier film and is curved in a self-aligned manner until reaching the upper surface of the semiconductor substrate.

  According to one embodiment of the present invention, when a self-aligned contact structure is applied, the protection performance of the gate insulating film by the protective insulating film can be maintained and the reliability can be improved.

  Hereinafter, an embodiment in which the nonvolatile semiconductor memory device of the present invention is applied to a NOR type flash memory device will be described with reference to the drawings. In the description of the drawings referred to below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the plane dimension ratio of each layer, the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.

  The NOR type flash memory device 1 employs an ETOX type memory cell that uses hot electrons generated near the drain for data writing and uses an FN tunnel current from the floating gate electrode FG to the source region 2b for erasing. ing.

  FIG. 1 shows an equivalent circuit diagram of a part of an electrical configuration of a cell array constituting a NOR type flash memory device, and FIG. 2 is a plan view of a portion corresponding to the electrical configuration shown in FIG. Show. The NOR type flash memory device 1 is divided into a memory cell region M and a peripheral circuit region P, and a memory cell array (hereinafter referred to as cell array) Ar formed in the memory cell region M is driven by a peripheral circuit in the peripheral circuit region. It is configured as follows.

  As shown in FIG. 1, in the cell array Ar, memory cell transistors Tm1 and Tm2 (hereinafter abbreviated as transistors Tm1 and Tm2 respectively) are arranged in a matrix with respect to the XY direction (in-surface direction of the silicon substrate 2). Consists of. The transistors Tm1 and Tm2 are given the same reference numerals for the sake of explanation, but have almost the same structure. Here, the X direction and the Y direction are directions orthogonal to each other in the silicon substrate surface.

  As shown in FIG. 1, two (a set) of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the Y direction, and the set of transistors Tm1 and Tm2 share a drain region. ing. The drain region is electrically connected to a bit line BL extending in the Y direction.

  A pair of these transistors Tm1 and Tm2 are arranged in the Y direction. The drain regions of the plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are commonly connected to one bit line (data line) BL. Two pairs of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the local source line LSL1 or LSL2.

  A plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are arranged in a plurality of rows with a separation in the X direction. As a result, the transistors Tm1 and Tm2 are arranged in a matrix in the XY direction, and constitute a cell array Ar in the memory cell region M.

  A plurality of bit lines BL are juxtaposed in correspondence with the transistors Tm1 and Tm2 arranged in a plurality of columns separated in the X direction. The plurality of bit lines BL are formed at the same interval in the X direction, and a plurality of main source lines MSL are arranged between the plurality of bit lines BL for each of a plurality of predetermined numbers. The main source line MSL has a line structure that becomes a source potential.

  Transistors Tm1 arranged in the X direction have their gates (control gate electrode CG (see FIG. 3) commonly connected by a word line WL1. Transistors Tm2 arranged in the X direction have their gates (control gate electrode CG). (See FIG. 3) is commonly connected by a word line WL2, which extends in the X direction in parallel with each other.

  The transistors Tm1 arranged in the X direction are commonly connected to a local source line (common source line) LSL2 whose source (source region 2b) extends in the X direction. The plurality of local source lines LSL1 and LSL2 are spaced apart from each other in the Y direction, extend in the X direction, and are commonly connected to the main source line MSL extending in the Y direction.

  The gate electrode MG1 of the transistor Tm1 is configured in the intersection region between the word line WL1 and the bit line BL, and the gate electrode MG2 of the transistor Tm2 is configured in the intersection region between the word line WL2 and the bit line BL. Yes. The gate electrodes MG1 and MG2 of these transistors Tm1 and Tm2 are arranged in the XY direction.

  As shown in FIGS. 1 and 2, transistors Tm1 and Tm1 adjacent in the Y direction share one local source line LSL1 disposed in the center in the Y direction between the gate electrodes MG1-MG1. . Similarly, the transistors Tm2 and Tm2 adjacent in the Y direction share one local source line LSL2 disposed at the center in the Y direction between the gate electrodes MG2 and MG2.

  FIG. 3 schematically shows a longitudinal sectional view taken along the line AA of FIG. 2 in the memory cell region. As shown in FIGS. 2 and 3, a drain via plug DV and a drain contact DC are stacked so as to be located, for example, in the center between adjacent word lines WL1 and WL2 and immediately below the bit line BL. These drain via plugs DV and drain contacts DC are configured to extend in the vertical direction (Z direction orthogonal to the XY plane) from directly above the silicon substrate 2, and are formed in the drain regions 2a of the transistors Tm1 and Tm2 (FIG. 3). And a bit line BL disposed above in the vertical direction are provided for electrical and structural connection.

  The memory cell region M is divided into (1) surface layer LY1 of the silicon substrate 2, (2) contact plug formation layer LY2, (3) via plug formation layer LY3, and (4) wiring layer LY4 from the lower layer side to the upper layer side. Note that (2) the stacked gate electrode layer LY2a is provided in a part of the same layer as the (2) contact plug formation layer LY2. In these layers (1) to (4), the following electrically conductive elements are formed.

(1) Surface layer LY1
Drain region 2a, source region 2b
(2) Contact plug formation layer LY2
Drain contact DC, local source line LSL1, local source line LSL2
(2a) Stacked gate electrode layer LY2a
Memory cell transistor gate electrode MG1 (floating gate electrode FG, intergate insulating film 7, control gate electrode CG), memory cell transistor gate electrode MG2 (floating gate electrode FG, intergate insulating film 7, control gate electrode CG)
(3) Via plug formation layer LY3
Drain via plug DV
(4) Wiring layer LY4
Bit line BL, main source line MSL (not shown in FIG. 3)
Hereinafter, a cross-sectional structure of the memory cell transistor Tm1 in the memory cell region M will be described. As shown in FIGS. 2 and 3, the transistor Tm2 has a symmetrical structure in the Y direction across the transistor Tm1 and the drain contact DC, and the transistor Tm2 is almost the same as the structure of the transistor Tm1. The structure of the transistor Tm1 will be described, and the description of the transistor Tm2 will be omitted.

  FIG. 4 schematically shows a cross section of the gate electrode, particularly along the line BB in FIG. As shown in FIG. 4, a plurality of element isolation grooves 3 are formed in a p-type silicon substrate 2 as a semiconductor substrate so as to be separated from each other in the X direction. These element isolation trenches 3 are formed along the Y direction in FIG. 2 and divide the active region (active area) Sa of the silicon substrate 2 in the X direction. As shown in FIG. 3, these active regions Sa are regions including the drain region 2a and the source region 2b of the transistors Tm1 and Tm2 and the channel region sandwiched between them, and are located immediately below the bit line BL. It is formed.

  As shown in FIG. 4, an element isolation insulating film 4 is buried in each of the plurality of element isolation trenches 3 to form an element isolation region Sb. The element isolation insulating film 4 is configured to protrude upward from the surface of the silicon substrate 2. A gate insulating film 5 is formed on the active region Sa of the silicon substrate 2 partitioned by the element isolation trench 3. The gate insulating film 5 is formed of a silicon oxide film having a predetermined thickness and functions as a tunnel insulating film.

  A polycrystalline silicon layer 6 is formed on the gate insulating film 5. The polycrystalline silicon layer 6 is formed by polycrystallizing amorphous silicon doped with impurities due to phosphorus, and a predetermined film so that the upper surface thereof is positioned higher than the upper surface of the element isolation insulating film 4. Consists of thickness. The polycrystalline silicon layer 6 is formed in a self-aligned manner with the side surface of the element isolation insulating film 4 in the cross section in the X direction, and is configured as the floating gate electrode FG of the transistor Tm1.

  Intergate insulating film 7 is formed along the upper surface and side surfaces of polycrystalline silicon layer 6 and the upper surface of element isolation insulating film 4. The inter-gate insulating film 7 is composed of, for example, an ONO film (a three-layer structure film of silicon oxide film-silicon nitride film-silicon oxide film), etc., and includes a second gate insulating film, an interpoly insulating film, and a conductive interlayer insulating film. Configured as

  A polycrystalline silicon layer 8 is formed on the intergate insulating film 7. The polycrystalline silicon layer 8 is configured as a layer formed by polycrystallizing amorphous silicon doped with impurities due to phosphorus.

  A silicide film 9 made of a metal such as tungsten is formed on the polycrystalline silicon layer 8, and the control gate electrode CG is constituted by the layers 8 and 9. A silicon nitride film 10 is formed as a cap insulating film on the control gate electrode CG. In the cross section shown in FIG. 3, the silicon nitride film 10 has a so-called “convex shape” in which the upper shoulder portion 10 a serving as the upper end in the Y direction is missing.

  In this way, the laminated gate electrode MG1 is formed on the silicon substrate 2 with the laminated structure of the floating gate electrode FG, the intergate insulating film 7, the control gate electrode CG, and the silicon nitride film 10 via the gate insulating film 5. Yes. A silicon nitride film 13, a silicon oxide film 14, and a bit line BL are stacked on the stacked gate electrode MG1.

  Further, as shown in FIG. 3, a silicon oxide film 11 is formed as a protective insulating film on the side walls of the floating gate electrode FG, the intergate insulating film 7 and the control gate electrode CG constituting the stacked gate electrode MG1. . The silicon oxide film 11 is provided for protecting the sidewall of the stacked gate electrode MG1, but is also formed on the upper surface of the gate insulating film 5 on the side of the stacked gate electrode MG1. The silicon oxide film 11 is configured such that its upper end 11 a is located above the upper surface of the intergate insulating film 7 and below the upper surface of the silicide film 9.

  In the surface layer of the silicon substrate 2, on both sides of the gate electrode MG1 in the Y direction, a drain region 2a is formed on one side, and a source region 2b is formed on the other side. A silicon nitride film 12 is formed on these drain / source regions 2a and 2b with a gate insulating film 5 interposed therebetween. The silicon nitride film 12 is formed so as to cover a part of the outer surface of the silicon oxide film 11 along the side surface and the upper surface of the silicon oxide film 11 formed on the side wall of the gate electrode MG1. 5 is formed along the upper surface of the silicon oxide film 11 formed on the upper surface of the silicon oxide film 5 so as to cover the lower side wall surface of the silicon oxide film 11. The upper end 12 a of the silicon nitride film 12 is formed so as to be positioned below the upper end of the silicon oxide film 11 a and positioned above the upper surface of the gate insulating film 5.

  A silicon nitride film 13 is formed on the upper and side surfaces of the silicon nitride film 12 so as to cover the silicon nitride film 12. The silicon nitride film 13 is formed along the upper surface and the outer surface of the silicon nitride film 12. The silicon nitride film 13 is also formed on the convex central upper surface of the silicon nitride film 10.

  Since these silicon nitride films 13 are formed in the same process, they are given the same reference numerals. A silicon oxide film 14 is formed on the silicon nitride film 13 formed on the convex central upper surface of the silicon nitride film 10. This silicon oxide film 14 constitutes an interlayer insulating film and an inter-plug insulating film in the upper layer region of the gate electrode MG1.

  On the drain side shown in FIG. 3, a drain contact DC is formed inside the silicon nitride film 13 between the gate electrodes MG1 and MG1. The drain contact DC is formed so as to be located immediately above the drain region 2 a of the silicon substrate 2. The drain contact DC is formed along the side portion of the silicon nitride film 13 whose lower side surface is formed along the side surface and the upper surface of the silicon oxide film 12. The drain contact DC is formed along the side surface of the silicon oxide film 14, the side surface of the silicon nitride film 13 on the silicon nitride film 10, and the upper side surface of the silicon nitride film 10.

  As shown in FIG. 2, these drain contacts DC are juxtaposed in the X direction. As shown in FIG. 3, these drain contacts DC include a tungsten (W) layer 16 and a barrier metal film 17 made of titanium (Ti) or the like formed so as to cover the lower surface and side surfaces of the tungsten layer 16. It is configured as a metal wiring layer.

  On the source side, a plurality of source regions 2 b are arranged in parallel in the X direction with the element isolation insulating film 4 interposed therebetween. As shown in FIG. 3, a local source line LSL1 is formed on these source regions 2b. This local source line LSL1 is formed from directly above the source region 2b to the height of the upper surface of the silicon oxide film 14 along the Z direction, and is extended along the X direction in FIG.

  As shown in FIG. 2, the local source line LSL1 is connected across a plurality of source regions 2b provided in the X direction and is structurally and electrically connected to the plurality of source regions 2b. It is configured. The local source line LSL1 is formed along the X direction across the plurality of active regions Sa and element isolation regions Sb.

  A silicon oxide film 15 is formed as an interlayer insulating film on the upper surface of the silicon oxide film 14 and on the upper surface of the local source line LSL1. A via hole is formed in the silicon oxide film 15 so as to communicate with the upper surface of the drain contact DC. A barrier metal film 18 is formed along the inner surface of the via hole, and a metal layer 19 is formed inside the barrier metal film 18. As a result, a drain via plug DV is formed. A bit line BL is formed along the Y direction on the drain via plug DV.

  FIG. 5 schematically shows a perspective view of the R region (region where the drain contact DC is formed and its periphery) in FIG. In FIG. 5, the silicon nitride films 12 and 13 around the drain contact DC are not shown in order to simplify the description. A BPSG (Boron-phosphosilicate glass) film 21 is embedded as an interelectrode insulating film around the drain contact DC (side in the X direction in FIG. 2A). In FIG. 5, the BPSG film 21 is provided with a reference numeral in its formation region and is not shown. The BPSG film 21 is a film with better embedding than a silicon oxide film made of TEOS, and is formed on the side of the gate electrode MG1.

  As shown in FIG. 2, the drain contact DC extends over the gate electrodes MG <b> 1 and MG <b> 2 adjacent in the Y direction and has an elliptical upper surface. As shown in FIG. 5, the drain contact DC is formed between adjacent gate electrodes MG <b> 1-MG <b> 2 in the BPSG film 21. Further, as shown in FIG. 3A, the drain contact DC has a lower side surface formed along the outer surface of the missing portion of the upper shoulder 10a of the silicon nitride film 10, and covers the upper end 11a of the silicon oxide film 11. The silicon nitride film 13 is formed along the outer surface of the upper end 13a.

  The drain contact DC is curved so that its lower side surface extends from the missing portion of the upper shoulder 10 a of the silicon nitride film 10 to the upper surface of the silicon substrate 2. Further, as shown in FIGS. 2A and 5, the drain contact DC has a lower end surface configured in a rectangular frame shape, and a part in the X direction is mounted on a part of the upper surface of the upper part 4 a of the element isolation insulating film 4. It is configured to be placed. In this way, the drain contact DC is formed in a self-aligned manner. Although the silicon nitride film 13 remains in a spacer shape on the side wall surface along the Y direction of the upper portion 4a of the element isolation insulating film 4, the illustration is omitted. Since such a structure is substantially the same for the lower surface shape of the source line contacts LSL1 and LSL2, the description thereof is omitted.

A structure of a transistor configured in the peripheral circuit region P will be described in association with the above structure.
FIG. 6 schematically shows a plan view of a transistor formation region in the peripheral circuit region. As shown in FIG. 6, a gate electrode PG is formed across the active region (active area) Sa, and an element isolation region Sb is formed on the outer periphery of the active region Sa.

  FIG. 7 schematically shows a longitudinal sectional view taken along the line CC of FIG. Note that the structural elements that are formed of the same material and in the same process as the structural elements constituting the memory cell region M described above will be described with the same reference numerals.

  As shown in FIG. 7, in the peripheral circuit region P, a gate electrode PG is formed on the upper surface of the silicon substrate 2 via a gate insulating film 5. The gate electrode PG has substantially the same structure as the gate electrodes MG1 and MG2 in the memory cell region M, and includes a polycrystalline silicon layer 6, an intergate insulating film 7, a polycrystalline silicon layer 8, a silicide film 9, and silicon The nitride film 10 is sequentially stacked. Where the gate electrode PG is different from the gate electrodes MG1 and MG2, a through hole 7a is formed in the approximate center of the intergate insulating film 7, and the polycrystalline silicon layers 6 and 8 are structurally and electrically connected to each other. Is the main difference.

  A silicon oxide film 11 is formed along the side wall of the lower structure of the gate electrode PG (polycrystalline silicon layers 6 and 8, intergate insulating film 7 and silicide film 9). The silicon oxide film 11 is formed continuously from the side wall portion of the gate electrode PG to the immediate upper surface of the gate insulating film 5 in substantially the same manner as the structure of the memory cell region M.

  A silicon nitride film 22 is formed along the lower outer wall surface of the silicon oxide film 11 along the side wall of the gate electrode PG. The silicon nitride film 22 has an upper end 22 a located below the upper end 11 a of the silicon oxide film 11. The silicon nitride film 22 is configured to be continuously located beside the gate electrode PG from the portion along the side wall of the gate electrode PG to the bottom portion along the upper surface of the silicon oxide film 11.

  A silicon nitride film 12 is formed on the outer side of the gate electrode PG and directly outside the silicon nitride film 22. The bottom of the silicon nitride film 12 is formed on the top surface of the silicon oxide film 11 and is configured to be in contact with the outermost end of the bottom of the silicon nitride film 22. The gate electrode extends upward from the contact end. It is configured to bend toward the PG side (inner side).

  A silicon oxide film 23 remains in the lower part of the region surrounded by the silicon nitride films 12 and 22 extending in the vertical direction. The silicon oxide film 23 is formed along the inner wall surface of the silicon nitride film 12. Further, the silicon oxide film 23 is formed on the bottom of the silicon nitride film 22.

  These silicon oxide films 23 are formed as spacer insulating films for forming source / drain regions 2c having an LDD (Lightly Doped Drain) structure, and an upper portion is anisotropically etched in the process (described later). The remaining film is the remaining film.

  The silicon nitride film 13 includes the upper surface (upper end surface) and side surface of the silicon nitride film 10 of the gate electrode PG, the upper surface (including the upper end 11a) and upper surface of the silicon oxide film 11, the upper surface and upper side surface of the silicon nitride film 22, silicon The upper and side surfaces of the silicon oxide film 23 formed on the bottom of the nitride film 22 and the upper and side surfaces of the silicon nitride film 12 and the bottom are covered. The silicon nitride film 13 is configured to cover the remaining film after the upper portion of the silicon oxide film 23 is anisotropically etched. A BPSG film 21 is formed on the silicon nitride film 13. The silicon nitride film 13 functions as a barrier film for suppressing the passage of impurity ions contained in the BPSG film 21.

  A silicon oxide film 14 is formed on the upper end surfaces of the BPSG film 21 and the silicon nitride film 13. A contact hole PH is formed in the silicon oxide films 11 and 14, the gate insulating film 5, the BPSG film 21, and the silicon nitride films 13 and 12, and a contact plug PC is formed in the contact hole PH. Structural and electrical connection between the diffusion layer (drain region) 2c formed on the surface layer of the silicon substrate 2 beside the gate electrode PG is achieved. The contact plug PC includes a barrier metal film 24 made of titanium (Ti) or the like and a metal layer 25 made of tungsten (W) or the like.

Next, the manufacturing method of the said structure is demonstrated.
FIG. 8 is a cross-sectional view showing a state in which each gate electrode MG in the memory cell region M and the gate electrode PG in the peripheral circuit region are divided and formed, and FIG. 8A shows a line AA in FIG. FIG. 8B schematically shows a longitudinal sectional view in the peripheral circuit region shown along the line CC in FIG. 6 at this time. It shows.

  As shown in FIG. 8A, in the memory cell region M, on the gate insulating film 5 formed on the silicon substrate 2, the polycrystalline silicon layer 6 that becomes the floating gate electrode FG, the inter-gate insulating film 7, A polycrystalline silicon layer 8, a silicide film 9, and a silicon nitride film 10 to be the control gate electrode CG are sequentially stacked and divided in the X direction in FIG. 2 to form the gate electrode MG.

  FIG. 8B shows the structure of the gate electrode PG in the peripheral circuit region P. At the same time as the structure in the memory cell region M, the polycrystalline silicon layer 6 and the inter-gate insulating film are formed on the gate insulating film 5. 7, the polycrystalline silicon layer 8, the silicide film 9, and the silicon nitride film 10 are sequentially laminated, and a step of forming a through hole 7 a in the center of the inter-gate insulating film 7 is provided at an intermediate stage.

  Drawing (a)-Drawing 21 (a) which attached (a) and Drawing 22 are longitudinal sections in one manufacturing process in memory cell field M shown along the AA line of Drawing 2 after this. FIG. 9B is a plan view schematically showing the drawings (FIG. 9B to FIG. 21B), and FIG. 9B is a plan view of the peripheral circuit region P shown along the line CC in FIG. The longitudinal cross-sectional view in a manufacturing process is shown typically. 9 to 22 are views showing processes following the process cross section of FIGS. 8A to 8B.

  As shown in FIGS. 9A and 9B, radical oxidation is performed in the regions P and M to oxidize the gate electrodes MG1, MG2, and PG. This radical oxidation process is a process for preventing abnormal oxidation of the silicide film 9. By performing this radical oxidation treatment, a silicon oxide film 11 is formed on the upper and side surfaces of the silicon nitride film 10, the side surfaces of the silicide film 9, the side surfaces of the polycrystalline silicon layers 6 and 8, and the side surfaces of the intergate insulating film 7. The side walls of the gate electrodes MG1, MG2, and PG can be protected.

  Next, as shown in FIGS. 10A and 10B, a silicon nitride film 22 is deposited on the silicon oxide film 11 by the CVD method in the regions P and M. The silicon nitride film 22 is formed so as to cover the upper surface and the outer surface of the silicon oxide film 11.

  Next, as shown in FIGS. 11A and 11B, in the regions P and M, the silicon oxide film 23 is formed on the silicon nitride film 22 and silicon nitrided by the CVD method using TEOS gas. It is deposited thicker than the film 22.

  Next, as shown in FIGS. 12A and 12B, in the regions P and M, the silicon oxide film 23 is anisotropically etched under a condition having high selectivity with respect to the silicon nitride film 22. Process spacers. Then, the silicon nitride film 22 functions as a stopper for the etching process, and the silicon oxide film 23 is formed along the side wall of the gate electrode PG so that the outer surface is curved through the silicon oxide film 11 and the silicon nitride film 22. . Next, patterning is performed using the resist 28 as a mask only on the peripheral circuit region P side, and a buffered hydrofluoric acid treatment is performed to peel off the silicon oxide film 23 in the memory cell region M.

  Next, as shown in FIGS. 13A and 13B, the silicon nitride film 22 exposed at this point is removed by etching in the regions M and P by hot phosphoric acid treatment. . Then, in the peripheral circuit region P, the silicon nitride film 22 is peeled off while leaving a portion sandwiched between the silicon oxide film 11 along the inner side surface and the bottom surface of the silicon oxide film 23 subjected to spacer processing. . In the memory cell region M, the silicon nitride film 22 is entirely removed.

  Next, as shown in FIGS. 14A and 14B, a silicon nitride film 12 is deposited in the regions M and P by a low pressure CVD method. Then, in the memory cell region M, the silicon nitride film 12 is formed along the outer surface and the upper surface of the silicon oxide film 11. At the same time, in the peripheral circuit region P, the silicon nitride film 12 is configured as a bottom along the upper surface of the silicon oxide film 11 on the gate insulating film 5, and the bottom is the top of the silicon nitride film 22. It is configured in contact with the outer end. Further, the silicon nitride film 12 is formed along the outer curved side surface of the silicon oxide film 23 and is formed along the upper surface of the silicon oxide film 11.

  Next, as shown in FIGS. 15A and 15B, in the regions M and P, a BPSG film 29 is deposited as a sacrificial layer on the silicon nitride film 12 and formed on the upper surface of each gate electrode. A planarization process is performed using the silicon nitride film 12 thus formed as a stopper. Next, as shown in FIGS. 16A and 16B, the BPSG film 29 is etched back in the regions M and P, and the height of the upper surface of the BPSG film 29 is the upper end surface of the silicon nitride film 12. Drop adjustment is performed so that a predetermined ratio (for example, 1/2) is obtained between the height of 12c and the height of the inner lower end portion 12b serving as the bottom of the silicon nitride film 12. At this time, the inner and lower end portions 12b of the silicon nitride film 12 positioned between the plurality of adjacent laminated films 6 to 10 are not removed. Although the BPSG film 29 is applied as the sacrificial layer, a resist may be used.

  Next, as shown in FIGS. 17A and 17B, in the regions M and P, the silicon nitride film 12 and the silicon nitride film 12 are formed by hot phosphoric acid treatment under a condition having high selectivity with the BPSG film 29. 22 is wet-etched. In the memory cell region M, the upper end 12 a of the silicon nitride film 12 is configured to be located above the upper surface of the polycrystalline silicon layer 8 and below the lower surface of the silicon nitride film 10. At this time, in the peripheral circuit region P, the upper portion of the silicon nitride film 22 formed along the outer surface of the silicon oxide film 11 and the upper portion of the silicon nitride film 12 on the curved upper side surface of the silicon oxide film 23 are also removed at the same time. Therefore, the upper end 12 a of the silicon nitride film 12 and the upper end 22 a of the silicon nitride film 22 in the region P are configured to be located above the upper surface of the polycrystalline silicon layer 8 and below the lower surface of the silicon nitride film 10. The upper surface (inner surface, outer surface) of the silicon oxide film 23 is exposed.

  Next, as shown in FIGS. 18A and 18B, the BPSG film 29 is removed by performing an anisotropic etching process. At this time, the removal process of the BPSG film 29 and the removal process of the silicon oxide film 11 formed along the upper surface and the side surface of the silicon nitride film 10 expose the upper surface and the side surface of the silicon nitride film 10. At the same time, the silicon oxide film 11 is processed so as to remain along the upper portion of the sidewall of the silicide film 9. The silicon oxide film 23 whose upper side surface is exposed in the above process is also anisotropically etched in this process. A part of the silicon oxide film 23 in the peripheral circuit region P is near the lower end of the silicon nitride film 22. Is removed.

  The reason for processing by anisotropic etching is that the silicon oxide films 11 and 23 are left along the side walls, and the upper side surface of the silicon oxide film 11 formed along the upper side walls of the silicide film 9 is formed into a curved shape. Because. Here, if isotropic etching such as wet etching is used, the effect of the etching process may reach up to the inter-gate insulating film 7 and thus cannot be applied.

  Next, as shown in FIGS. 19A and 19B, a silicon nitride film 13 is formed by a low pressure CVD method. In the peripheral circuit region P, the silicon nitride film 13 includes upper and side surfaces of the silicon nitride film 10, upper surface (including the upper end 11a) and side surfaces of the silicon oxide film 11, and upper and outer surfaces (upper end 22a) of the silicon nitride film 22. The upper and inner side surfaces of the etching residual film of the silicon oxide film 23, and the upper and side surfaces (including the upper end 12a) and the bottom of the silicon nitride film 12 are formed. The silicon nitride film 13 functions as a barrier film for suppressing the passage of impurity ions contained in the BPSG film 21.

  Next, as shown in FIGS. 20A and 20B, a BPSG film 21 is deposited on the silicon nitride film 13 by the CVD method, and the silicon nitride film 13 formed on the upper surface of each gate electrode. The BPSG film 21 is planarized by the CMP method using as a stopper.

  Next, as shown in FIGS. 21A and 21B, a silicon oxide film 14 is deposited by plasma CVD using TEOS gas. Then, the silicon oxide film 14 is deposited along the upper surface of the BPSG film 21 and is deposited along the upper surface of the silicon nitride film 13.

  Next, as shown in the process of the memory cell region in FIG. 22, a photoresist (not shown) is applied, and the resist is patterned by photolithography in the formation region Rd of the drain contact DC and patterned. Using the resist as a mask, the silicon oxide film 14 and the BPSG film 21 are processed by anisotropic etching (RIE method) under conditions having high selectivity with respect to the silicon nitride film.

  At this time, since the opening width of the resist is set wider than the interval between the plurality of gate electrodes MG1-MG1 and between MG1-MG2, when the silicon oxide film 14 and the BPSG film 21 are etched, the silicon oxide film 14 and Although the BPSG film 21 is mainly processed, the upper corner (upper edge) 10a of the silicon nitride film 10 is etched at a low speed.

  When the etching process is performed by adjusting the time in a state where various conditions such as the film thickness of each of the films 5 to 10, 13, and 14 and the etching selectivity are adjusted, the contact hole DH reaches the upper surface of the silicon substrate 2. When formed in this manner, the upper shoulder portion 10a of the silicon nitride film 10 and the side portion of the silicon nitride film 13 are formed in a missing shape.

  In this case, the lower upper end 13 a of the silicon nitride film 13 is formed so as to cover the upper end 11 a of the silicon oxide film 11 and remain. That is, even if the anisotropic etching process is performed, the silicon oxide film 11 formed along the side wall of the gate electrode MG1 can be protected. Since the silicon nitride film 13 is formed vertically along the side walls of the gate electrodes MG1 and MG2 on the lower side surface of the contact hole DH, the contact hole DH extends along the outer surface of the silicon nitride film 13 and the upper surface of the silicon substrate 2. The contact hole DH is formed so as to extend upward, and the diameter of the contact hole DH gradually decreases from the upper layer side to the upper surface of the silicon substrate 2, and the influence of the etching process does not erode the silicon oxide film 11.

  In this way, the contact hole DH whose upper portion is planarly elliptical in the Y direction on the drain contact DC side while maintaining the film formation state of the silicon oxide film 11 is formed in a self-aligned (self-aligned) manner with high reliability. can do.

  As shown in the perspective view of FIG. 5, on the drain contact DC side, the silicon nitride film 10 and the silicon nitride film 13 are missing in the side wall portion along the other X direction other than the formation region of the contact hole DH. Never formed.

  As shown in FIG. 22, the process of forming the hole DH on the drain contact DC side in the memory cell region M is repeated in the same manner on the local source line contacts LSL1 and LSL2 side in the memory cell region M, thereby A similar self-aligned planar straight hole (upper side is a substantially rectangular parallelepiped shape and the lower surface is a curved surface shape between the gate electrodes) can also be formed on the contacts LSL1 and LSL2 side.

In addition, although the contact hole PH is formed in the BPSG film 21 and the like in the peripheral circuit region P, since the self-aligned contact hole is not applied in the peripheral circuit region P, description of the forming method is omitted.
Next, as shown in FIG. 3, a barrier metal film 17 of titanium (Ti) is formed along the holes DH and SH by sputtering, a tungsten layer 16 is deposited by CVD, and a silicon oxide film 14 is formed. As a stopper, the tungsten layer 16 and the barrier metal film 17 are planarized by CMP. At the same time, a barrier metal film 24 of titanium (Ti) is formed along the inner surface of the hole PH, and a tungsten layer 25 is deposited by the CVD method. Then, in the memory cell region M, the drain contact DC and the local source line contacts LSL1, LSL2 can be formed in a state of being separated from the gate electrodes MG1 and MG2. In the peripheral circuit region P, a contact PC can be formed.

  Next, as shown in FIG. 3, a silicon oxide film 15 is deposited by a CVD method, a resist (not shown) is patterned on the silicon oxide film 15, and the drain is drained using the patterned resist as a mask. A via hole reaching just above the contact DC is formed, a barrier metal film 18 is formed in the hole by sputtering, a metal layer 19 is deposited inside the barrier metal film 18 with tungsten or the like, and the silicon oxide film 15 is stoppered. As a result, the drain side via plug DV is formed. Next, the structure of the memory cell region M of the flash memory device 1 can be formed by forming the bit line BL structure or the like in the upper layer of the via plug DV. The subsequent steps are the same as the features of this embodiment. Since is not directly related, its description is omitted.

  According to this embodiment, the gate electrodes MG1 and MG2 are subjected to radical oxidation treatment so that the upper and side surfaces of the silicon nitride film 10, the side surfaces of the control gate electrode CG, the side surfaces of the inter-gate insulating film 7, and the side surfaces of the floating gate electrode FG. A silicon oxide film 11 is formed along the upper surface and side surfaces of the silicon nitride film 10 by adjusting the upper end 11a of the silicon oxide film 11 to the upper surface position of the silicide layer 9 by anisotropic etching after several steps. , And a silicon nitride film 13 is formed so as to cover the upper and side surfaces of the gate electrodes MG1 and MG2 and the upper end 11a and side surfaces of the silicon oxide film 11, and a BPSG film 21 is formed inside the silicon nitride film 13, The BPSG film 21 is etched under conditions having high selectivity with respect to the silicon nitride film.

  In this case, the silicon oxide film 11 and the BPSG film 21 are formed of a highly selectable material during the etching process with the silicon nitride films 10 and 13, respectively, and the lower upper end 13a of the silicon nitride film 13 is formed in the contact hole DH. After the formation, the thickness of each layer and the etching process conditions are adjusted in advance so as to cover the upper end 11a of the silicon oxide film 11. Then, when the contact hole DH is formed, since no oxide film material is interposed between the silicon nitride film 10 and the silicon nitride film 13, the influence of the etching process at the time of forming the contact hole DH is affected by the oxide film insulation. It can be configured not to erode to the control gate electrode CG side through the film, and the contact hole DH can be formed in a self-aligning manner.

  Therefore, it is possible to form the contact hole DH in a self-aligning manner while protecting the side surfaces of the gate electrodes MG1 and MG2, particularly the side surfaces of the inter-gate insulating film 7 with the silicon oxide film 11, and then the material of the drain contact DC in the contact hole DH. Even if embedded, the contact DC material can be prevented from contacting the gate electrodes MG1 and MG2, thereby improving the reliability. Moreover, a margin for misalignment in the lithography process can be ensured, and miniaturization can be achieved.

  Further, after forming the silicon oxide film 11, a silicon nitride film 12 is formed so as to cover the silicon oxide film 11, and a BPSG film 29 is formed inside the silicon nitride film 12 between the plurality of gate electrodes MG1-MG1. Then, the upper end 12a of the silicon nitride film 12 and the upper end 11a of the silicon oxide film 11 are dropped to form the silicon nitride film 13 so as to cover the silicon oxide film 11, and when the contact hole DH is formed, the upper end of the silicon oxide film 11 is formed. Since the contact hole DH is formed while the silicon nitride film 13 remains so as to cover 11a, the inter-gate insulating film 7 and the gate insulating film 5 are not exposed to the etching process, and the reliability is improved. it can.

  Since the upper end 11a of the silicon oxide film 11 is adjusted to be positioned near the interface between the silicon nitride film 10 and the silicide film 9 (near the upper surface of the control gate electrode CG), the control gate electrode CG, the gate The side walls of the inter-layer insulating film 7 and the floating gate electrode FG can be protected, and the reliability can be improved.

  The silicon oxide film 11 is formed along the side walls of the plurality of floating gate electrodes FG and the intergate insulating film 7 such that the upper end 11a is located near the upper surface of the control gate electrode CG, and the drain contact DC is formed in the BPSG film 21. The lower side surface is formed in a self-aligned manner along the missing surface of the upper shoulder portion 10a of the silicon nitride film 10 and the outer surface of the silicon nitride film 13 covering the upper end 11a of the silicon oxide film 11. Therefore, the reliability of the silicon oxide film 11 can be maintained, and the side walls of the gate electrodes MG1 and MG2 can be appropriately protected.

  Since the etching amount is controlled using anisotropic etching when the silicon oxide film 11 is etched, the process margin can be improved as compared with the case where isotropic etching such as wet etching is used.

  The upper end 11a of the silicon oxide film 11 is adjusted to any position as long as it is formed so as to be located above the upper surface of the inter-gate insulating film 7 and below the upper surface of the control gate electrode CG. Also good.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the above-described embodiment, the P-type silicon substrate 2 in which the well is appropriately formed on the surface layer is applied, and the structure on the silicon substrate 2 is mainly described. However, the P-well is formed on the surface layer of the N-type silicon substrate 2. The present invention may be applied to the structure of the region, and in the present invention, a semiconductor substrate of another material may be applied.

Although the embodiment has been described in which the contact hole DH is formed such that the upper end thereof is planarly elliptical, the present invention can be applied to a case where a contact hole whose upper end is planarly shaped is formed instead.
Although an ONO film is applied as the inter-gate insulating film 7, a high dielectric film such as alumina may be applied.
The present invention can also be applied to a T-shaped structure in which the polycrystalline silicon layer 6 (floating gate electrode FG) projects on the element isolation insulating film 4 adjacent in the X direction.

The silicide film 9 made of tungsten is applied as the lower resistance metal layer on the control gate electrode CG. However, in the present invention, a silicide layer made of another metal may be formed and applied if necessary, or the control gate electrode CG may be used. A poly gate may be applied.
Although the present invention is applied to a NOR type flash memory device, the present invention may be applied to a NAND type flash memory device or another nonvolatile semiconductor memory device such as an EEPROM.
Even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the object described in the column of the problem to be solved by the invention can be achieved, and is described in the column of the effect of the invention. If the effect is obtained, the configuration requirement from which this configuration requirement is deleted can be applied as an invention.

1 is an equivalent circuit diagram of an electrical configuration of a cell array according to an embodiment of the present invention. A plan view schematically showing the structure of the memory cell region FIG. 2 is a vertical cross-sectional view schematically shown along line AA in FIG. FIG. 2 is a vertical cross-sectional view schematically shown along line BB in FIG. The perspective view which shows typically about R area | region of FIG. A plan view schematically showing the structure of the peripheral circuit area FIG. 6 is a longitudinal cross-sectional view schematically shown along the line CC in FIG. FIG. 3 and FIG. 7 equivalent view schematically showing one manufacturing stage (part 1) FIG. 3 and FIG. 7 equivalent view (part 2) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (part 3) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (part 4) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (part 5) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view schematically showing one manufacturing stage (No. 6) FIG. 3 and FIG. 7 equivalent view (No. 7) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (No. 8) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (No. 9) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view schematically showing one manufacturing stage (No. 10) FIG. 3 and FIG. 7 equivalent view (11) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (No. 12) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (13) schematically showing one manufacturing stage FIG. 3 and FIG. 7 equivalent view (14) schematically showing one manufacturing stage FIG. 3 equivalent view schematically showing one manufacturing stage (No. 15)

Explanation of symbols

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 5 is a gate insulating film (first gate insulating film), 6 is a polycrystalline silicon layer (floating gate electrode), and 7 is an inter-gate insulating film (first gate insulating film). 2 is a silicon nitride film (cap insulating film), 11 is a silicon oxide film (first insulating film), 12 is a silicon nitride film (barrier film), 13 is a silicon nitride film (barrier film), 21 is a BPSG film (interelectrode insulating film), 22 is a silicon nitride film (second insulating film), 29 is a BPSG film (sacrificial layer), DH is a drain contact hole (contact hole), and SH is a source contact hole (contact hole). ), DC is a drain contact (contact plug), LSL1 and LSL2 are source line contacts (contact plug), FG is a floating gate electrode, and CG is a control gate. Gate electrode, MG1, MG2, PG denotes a gate electrode (stacked gate electrode).

Claims (5)

A plurality of stacked gate electrodes in which a plurality of floating gate electrodes, a plurality of second gate insulating films, a plurality of control gate electrodes, and a plurality of cap insulating films are sequentially stacked on a semiconductor substrate via a first gate insulating film. Forming, and
Forming a first insulating film for gate protection so as to cover the upper surface and side surfaces of the plurality of stacked gate electrodes by radical treatment of the plurality of stacked gate electrodes;
Forming a second insulating film of the same material as the cap insulating film so as to cover the first insulating film;
Located on the side of the floating gate electrode, the second gate insulating film, the control gate electrode, and the cap insulating film, and below the height of the upper end of the control gate electrode and above the upper surface of the second gate insulating film Forming a sacrificial layer with a highly selectable material during etching between the second insulating film and the inner side of the second insulating film to a position;
Exposing the upper portion of the first insulating film by etching the second insulating film to a position below the height of the upper end of the control gate electrode and above the second gate insulating film;
The cap insulating film is exposed by anisotropically etching the first insulating film so that the upper end of the first insulating film is below the upper surface of the cap insulating film and above the upper end of the second insulating film. A process of
Forming a third insulating film of the same material as the second insulating film so as to cover the cap insulating film;
Forming an interelectrode insulating film with a highly selectable material during etching so as to cover the third insulating film with the cap insulating film;
A third insulating film that covers the stacked gate electrode by etching the inter-electrode insulating film under a condition having high selectivity with the cap insulating film covers an upper end of the second insulating film. Forming a contact hole in a self-aligning manner while leaving the second insulating film on
Forming a contact plug in the contact hole. A method for manufacturing a nonvolatile semiconductor memory device. The sacrificial layer is made of the same material as the first insulating film,
2. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein in the step of anisotropically etching the first insulating film, the sacrificial layer is etched simultaneously. In the step of etching the second insulating film, the third insulating film in the peripheral circuit region is simultaneously etched,
3. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein, in the step of forming the fifth insulating film, the fifth insulating film is simultaneously buried in a region where the third insulating film is removed by etching. Method. The sacrificial layer is composed of an impurity-containing film,
4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 1, wherein the fourth insulating film functions as a barrier film for suppressing passage of impurities contained in the impurity-containing film. 5. . A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate; a plurality of floating gate electrodes formed on the first gate insulating film; and a plurality of first gate electrodes formed on the plurality of floating gate electrodes, respectively. 2 gate insulating films, a plurality of control gate electrodes formed on the plurality of second gate insulating films, respectively, and upper shoulder portions are missing in a partial cross section on the plurality of control gate electrodes. A plurality of laminated gate electrodes composed of a plurality of cap insulating films formed;
A sidewall insulating film formed along the sidewalls of the plurality of floating gate electrodes and the plurality of second gate insulating films constituting the plurality of stacked gate electrodes, the upper end height of which is higher than the vicinity of the upper surface of the control gate electrode Side wall insulating films formed by silicon oxide films located below,
A barrier film formed between the sidewall insulating films of the plurality of stacked gate electrodes and formed to cover the sidewall insulating film;
A contact plug formed between sidewall insulating films of the plurality of stacked gate electrodes, the lower side surface of which is formed along the missing surface of the cap insulating film and the outer surface of the barrier film and reaches the upper surface of the semiconductor substrate. A non-volatile semiconductor memory device comprising a contact plug that is curved in a self-aligning manner.

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