JP2009301415A - Memory module control method, memory module and data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption of an SDRAM DIMM or the like. <P>SOLUTION: An access means accesses an SDRAM controller. The SDRAM controller supplies control signals through an SDRAM control signal line group (3) and access lane code signals through an access lane code line (2) to a control signal filter logic circuit (5). The control signal filter logic circuit (5) selectively transfers the control signals to an SDRAM element #D0(10) to an SDRAM element #D7(17) and an SDRAM element #ECC on the basis of the access lane code signals. Thus, the SDRAM element #D0(10) to the SDRAM element #D7(17) are selectively activated and burst access to the activated SDRAM elements is executed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a memory module control method, a memory module, and a data transfer device, and more particularly to a memory module control method, a memory module, and a data transfer device that are useful for reducing power consumption of the memory module.

In various information processing apparatuses, a semiconductor memory device has been conventionally used. For example, in embedded devices, PCs, data servers, etc., standardized single inline memory modules (SIMMs) and SDRAMs (dual inline memory modules) such as SDRAMs (Synchronous Dynamic Random Access Memory) are placed on a single substrate. An integrated memory module is used. Each of these SDRAMs is composed of a predetermined number of SDRAM elements, and the input / output terminals of these SDRAM elements are connected in parallel to the data bus.
A plurality of SDRAMs can access a plurality of the data buses in parallel and simultaneously, and can be accessed with data having a desired data width.

FIG. 10 shows a conventional SDRAM DIMM 1001. In the SDRAM DIMM 1001, nine SDRAM elements # D0 1010 to # D7 1017 and SDRAM #ECC 1020 each having an 8-bit data input / output bus are mounted on the same substrate. The data input / output buses of the element # D0 1010 to the SDRAM element # D7 1017 are respectively connected to corresponding 8-bit lines in the 64-bit data line 1004 and are connected in parallel to the data line 1004. An ECC (Error Correcting Code) line 1006 is connected to the SDRAM element #ECC 1020, and an SDRAM control signal line group 1003 such as a clock, a command, and an address is connected to each of the SDRAM elements # D0 1010 to SDRAM elements # D7 1017 and the SDRAM elements. Connected to #ECC 1020 Its entirety is constructed.
The SDRAM control signal line group 1003, the data line 1004, and the ECC line 1006 constitute a data bus of the system. Therefore, the data line 1004 is used for reading or writing data corresponding to the bus width of the system.

The SDRAM DIMM 1001 is provided with power saving states such as a power-down mode and a self-refresh mode, and is configured to be able to switch between the power saving state and an active mode (normal state) during normal access. Yes. When the power saving state is set by switching the equipped functions, the current consumption is reduced by about 1/2 to 1/5 depending on the state.
However, the above switching causes overhead of several cycles to several tens of cycles depending on the state, resulting in performance degradation. The current consumption during the switching is equivalent to the normal state, and it is more efficient to reduce the number of times of switching from the power saving state as much as possible.

  In SDRAM, it is efficient to perform data burst transfer about 4 to 16 times in succession for one read command or write command for reading or writing. At that time, in the case of a single read, the remaining data is discarded and the read is performed, and in the case of a single write, other data in the burst cycle is masked. It is common to do that light.

Also, in the case of single read transfer, it is common to extract necessary data after performing burst transfer. A timing chart showing the operation in this case is shown in FIG.
In FIG. 11, when writing only the signal W3 into the SDRAM, the mask signals shown in 11g) and 11i) in FIG. 11 are enabled except for the second half of the cycle T5 in which W3 is written, and W1 and W2, and W4 to W8 and the corresponding ECC signals are prevented from being written to the SDRAM device.
In order to reduce useless transfer cycles, bursts can be interrupted when necessary data access is completed.

  However, when performing single data read transfer or write transfer as described above, all SDRAMs on the SIMM or DIMM need to be activated if necessary and further activated. There arises a problem that almost the same power as that of the transfer is consumed.

Patent Document 1 discloses an invention that solves this problem in a limited manner. An embodiment of the present invention is shown in FIG.
In the invention of Patent Document 1, as shown in FIG. 12, macro selection circuits MSE 1220 to 1223 are provided for the SDRAMs 1210 to 1213 of the SDRAM DIMM (MMD) 1201. The MSEs 1220 to 1223 have a register therein, and the register is set according to the bit width of the data input / output terminal.

The MSEs 1220 to 1223 also monitor the upper bits and commands of the addresses of external commands, and control the activation of the SDRAMs 1210 to 1213 by using these addresses and commands. The activation control is as follows.
That is, when the data of the DIMM data input / output terminal is four times as wide as the data width of each of the SDRAMs 1210 to 1213, each command activates each SDRAM, but the data width of the data input / output terminal of the DIMM If it is less than that, only the SDRAM corresponding to the address is activated after viewing the address.
However, for commands such as refresh, all SDRAMs are activated simultaneously regardless of the address, and SDRAM DIMMs having various input / output data width configurations are configured by combining the same SDRAM and MSE.

  Patent Document 2 discloses a memory control device for controlling the selective use of different types of SDRAM. This memory control device determines which type of SDRAM it is, activates the SDRAM according to the determination result, and exchanges data between the SDRAM and the memory interface according to the corresponding bus protocol. It is configured as follows.

Patent Document 3 discloses a data transfer control device that controls data transfer between a plurality of master devices and memory devices. This data transfer control device has a data bus having a data width wider than the data width of the memory device. It is configured to interface the data transfer with the corresponding number of data transfers (burst transfer).
JP 2003-006042 A JP 2003-076603 A JP 2007-164415 A

However, in the invention disclosed in Patent Document 1, the mode of access to the SDRAM is determined depending on the number of data input / output terminals (bit width).
Therefore, it can be said that nothing has been said about changing the activation mode freely according to the amount of data accessed to the SDRAM.
Further, when the bit width of the data input / output terminal of SIMM or DIMM is wide, all the SDRAM elements are activated at the same time, and thus the above problem cannot be solved.
Note that both Patent Document 2 and Patent Document 3 are premised on that when an SDRAM or a memory device is accessed, the entire device is activated.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a memory module control method, a memory module, and a data transfer device that achieve low power consumption by partial access to a plurality of memories.

  In order to solve the above-described problem, a first configuration of the present invention is a control for activating a memory when driving any of the memory modules having a plurality of memories each having a predetermined number of bits. A memory selection signal for selectively supplying a signal is input to the memory module, and the control signal is distributed to the memory corresponding to the memory selection signal based on the input memory selection signal to activate the memory. It is characterized by that.

  According to a second configuration of the present invention, when driving a plurality of memories each having a predetermined number of bits and any of the plurality of memories, a control signal for activating the memories is selectively selected. Input means for inputting a memory selection signal to be supplied, and distribution means for distributing the control signal to the memory corresponding to the memory selection signal based on the memory selection signal input by the input means Yes.

  According to the present invention, the memory selection signal is input to the memory module having a plurality of memories, and the control signal is supplied to the memory corresponding to the memory selection signal based on the memory selection signal. Can be achieved.

  The present invention is configured to include inputting a memory selection signal to a memory module having a plurality of memories and supplying a control signal to a memory corresponding to the memory selection signal based on the input memory selection signal.

Embodiment 1

  FIG. 1 is a block diagram showing an electrical configuration of an SDRAM DIMM according to Embodiment 1 of the present invention, FIG. 2 is a diagram showing a control signal filter rule (distribution rule) based on an address lane code of the SDRAM DIMM, and FIG. 4 is a diagram showing a memory storage address correspondence table of the SDRAM DIMM, FIG. 4 is a block diagram showing an electrical configuration of a chip for controlling the SDRAM SIMM, and FIG. 5 is a matrix rearrangement logic and buffer configuration of the SDRAM DIMM. FIG. 6 is a time chart showing an operation example in normal writing of the SDRAM DIMM, FIG. 7 is a time chart showing an operation example in partial writing of the SDRAM DIMM, and FIG. 8 is a normal time chart of the SDRAM DIMM. FIG. 9 is a time chart showing an operation example in reading, and FIG. 9 is a partial reading of the SDRAM DIMM. It is a time chart showing an example of the operation of the in out.

The SDRAM DIMM 1 of this embodiment relates to a system that can perform partial data access without requiring activation of all SDRAM elements constituting the SDRAM SIMM / DIMM. As shown in FIG. # D0 10 to SDRAM element # D717, SDRAM element #ECC 21 storing ECC for error detection and correction, and control signal filter logic circuit 5 are integrated on the board.
The SDRAM elements # D0 10 to # D7 17 are SDRAM elements accessed by 8-bit data, and each of them has 8 bit lines, and these 8 bit lines are 64 bits. The bit data line 4 can be connected to an input / output transfer terminal.
The SDRAM element #ECC 21 is an SDRAM element for storing an ECC for error detection and correction, and an ECC signal line 6 is disposed and connected to the SDRAM element #ECC 21.

  The control signal filter logic circuit 5 is a circuit that determines whether or not to transfer the signal of the control signal line group 3 to the SDRAM element # D0 10 to the SDRAM element # D717 and the SDRAM element #ECC 21. The signal line group 3 and the address lane code line 2 are arranged and connected. The control signal line group 3 is a signal line group for transferring an address, strobe signal, clock, clock enable, write mask signal, chip select signal, and the like. The signal of the control signal line group 3 is a control signal for activating the SDRAM element # D0 10 to the SDRAM element # D717 in this embodiment, and the signal of the address lane code line 2 sends the control signal to the SDRAM element #. Control signal selection signals (also referred to as memory selection signals) distributed to all or part of D0 10 to SDRAM element # D717. The control signal selection signal includes a data amount (all data to be transferred in burst or partial data to be subjected to burst transfer) and an address designating all or part of the SDRAM elements # D0 10 to # D7 17 of the data quantity. Is a signal generated based on

An example of the distribution rule of the control signal filter logic circuit 5 is as shown in FIG.
An example of the distribution rule will be described with reference to FIG. 2. When the 4 bits of the address lane code line 2 are 0b10, the SDRAM control signal line group 3 is connected to all the SDRAM elements # SD0 to # D717. However, when the upper 1 bit is 0b0, only the SDRAM element indicated by the value of the lower 3 bits is notified.

Next, access is made to the SDRAM element # D0 10 to the SDRAM element # D7 17 integrated in the SDRAM DIMM 1 for data to be transmitted / received to / from the matrix rearrangement logic and buffer 404 (FIG. 5) described later. Addressing is shown in FIG.
In FIG. 3, each of the addresses for sequentially accessing the matrix rearrangement logic and the buffer 404, which will be described later in the eight data buffers 510 to 517, is 0x0, 0x1,. 0x7, when the access order is second, the data buffer order is represented by 0x8, 0x9,..., 0xf, when the access order is third, the data buffer order is represented by 0x11, 0x12,. .., 0x3f in the data buffer order when the access order is eighth.

  The addressing of the SDRAM DIMM in the related technology is performed by interleaving the data arrangement in the SDRAM DIMM having the configuration shown in FIG. 1 into eight SDRAM elements. The addressing method is used in the direction of the number of repetitions). For example, in order to read out double word (8 bytes) data from the address 0x0, only the SDRAM element # D0 10 is reconfigured into an array of values output by 8-burst read transfer. In other words, this means that the data spread on the space axis of the data bus is expanded on the time axis into a plurality of serial data.

Next, an access control circuit of the SDRAM DIMM 1 (a chip that controls the SDRAM DIMM 1) will be described with reference to FIG.
This chip 401 is connected to the SDRAM DIMM 1. Various modules not directly related to the present invention are connected to the chip 401 via an in-chip system bus 402, but these modules are not shown.
As an access execution means to the SDRAM DIMM 1 connected to an access means (CPU, DMA controller, etc.) not shown via the in-chip system bus 402, there are an SDRAM controller 403, matrix rearrangement logic, and a buffer 404. It is connected to the SDRAM DIMM1.

The matrix rearrangement logic and buffer 404 plays a role of rearranging data with respect to the data lines. The SDRAM controller 403 controls the matrix rearrangement logic and the control signal line 409 connected to the buffer 404 in addition to controlling the signals to the SDRAM control signal line group 3 and the address lane code line 2 to the SDRAM DIMM 1. Is also generated.
Further, an error detection / correction / code generation logic circuit 405 is provided between the in-chip system bus 402 and the matrix rearrangement logic / buffer 404, and the matrix rearrangement logic / buffer 404 has an ECC line 6 ( 1) is also connected.

The arrangement of the matrix rearrangement logic and buffer 404 will be described with reference to FIG.
The matrix rearrangement logic / buffer 404 includes an access signal generation logic circuit 501, eight data buffers 510 to 517, and a data ECC buffer 520.
An access control signal 409 of the SDRAM controller 403 is connected to the access signal generation logic circuit 501, and access to each of the data buffers 510 to 517 is controlled by the access control signal of the control signal line 409. This access control signal is generated based on all or part of the data transferred in burst and the address designating all or part of the SDRAM elements # D0 10 to # D7 17 corresponding to all or part of the data. Signal.
Switches are provided at the input / output of the data buffers 510 to 517 and the data ECC buffer 520, and these switches are configured to be controlled by an access signal output from the access signal generation logic circuit 501. . In the following description, when “via a switch” is used, an access signal necessary for the operation of the switch is supplied to the switch.

The data buffers 510 to 517 and the data ECC buffer 520 are connected to the data line 502 on the system bus side via the error detection / correction and code generation logic circuit 405, while being connected to the data line 4 on the SDRAM DIMM side. It is configured. The connection to the data line 502 in the data buffers 510 to 517 is an 8-bit 8-entry buffer for each bit lane of the data line 502, while the connection to the data line 4 in the data buffers 510 to 517 is all The data lane (data lane 0 to data lane 7) signals (for example, 8 bits) can be connected to all the data buffers 510 to 517 via the switches described above, and one or more of the data lanes correspond to the switches. It can be selected by the operation of.
The data ECC buffer 520 is connected to the ECC line 6 (FIG. 1), and is connected to the error detection / correction / code generation logic circuit 506.

  An example of access control to each of the data buffers 510 to 517 by the access signal generation logic circuit 501 will be described. In this embodiment, both the system bus 402 and the data line 4 are lines for transmitting and receiving 8-byte data of 64 bits. Then, 64-bit 8-times data W0, W1, W2, W3, W4, W5, W6 and W7 (6d in FIG. 6) transmitted and received via the system bus 402 (FIG. 4) (data line 502 (FIG. 5)). The address attached to the write data on the bus shown in FIG. 4) is address A0 corresponding to the first 64 bits (W0), address A1 corresponding to the second 64 bits (W1), and address corresponding to the third 64 bits (W2). Address A2,..., Address A7 corresponding to the eighth 64-bit (W7).

First, the write control logic for the data buffers 510 to 517 by the access signal generation logic circuit 501 will be described.
Data and control signals for writing are received via the system bus 402. At the time of writing the data, 64-bit data is transferred to the data buffers 510 to 517 from the error detection / correction and code generation logic circuit 405 through the data line 502 eight times, and the ECC for each 64-bit is stored in the data ECC buffer. Forwarded to 520.

  The first 8 bytes (W0) are D0x0, D0x1, ..., D0x7, the second 8 bytes (W1) are D0x8, D0x9, ..., D0xf, and the third 8 bytes (W2) are D0x11. , D0x12,..., D0x17,..., D8x38, D0x39,..., D0x3f, the data composed of these eight bytes is transferred by the access signal generation logic circuit 501. Each of the bytes is input in parallel to each of the data buffers 510 to 517 via the corresponding switch, and 8 bytes sequentially input are written to the corresponding data buffers 510 to 517 for each byte. Simultaneously with this writing, the data-corresponding ECC is sequentially written into the data ECC buffer 520.

  The data written as described above is transferred from the data buffer 510 to D0x0 as shown by the burst repetition number 0 in FIG. 3 at the 0th read from the data buffers 510 to 517 by the access signal generation logic circuit 501. Data buffer 511 to D0x9, Data buffer 512 to D0x12, Data buffer 513 to D0x1b, Data buffer 514 to D0x24, Data buffer 515 to D0x2d, Data buffer 516 to D0x36, Data buffer 517 to D0x3f To the corresponding data lane on the data line 4 (burst repetition number 0 in FIG. 3, 6h in FIG. 6) and w0 in 7h) in FIG.

  In the next first read, as shown in the burst repetition number 1 in FIG. 3, the data buffers 511 to D0x1, the data buffers 512 to D0xa, the data buffers 513 to D0x13, the data buffers 514 to D0x1c, 515 to D0x25, data buffers 516 to D0x2e, data buffers 517 to D0x37, and data buffers 510 to D0x38 are read out to the corresponding data lanes of the data line 4 via the corresponding switches (burst in FIG. 3). Number of iterations 1, w1) of 6h) in FIG. 6 and 7h) in FIG.

Similarly, in the seventh read, as indicated by the burst repetition number 7 in FIG. 3, the data buffers 517 to D0x7, the data buffers 510 to D0x8, the data buffers 511 to D0x11, and the data buffers 512 to D0x1a However, data buffer 513 to D0x23, data buffer 514 to D0x2c, data buffer 515 to D0x35, and data buffer 516 to D0x3e are read to the corresponding data lanes of data line 4 (burst repetition number 7 in FIG. 3). 6h) in FIG. 6 and w7) in FIG. 7h), the bytes sequentially output on each data lane are SDRAMs accessed at addresses A0 to A7 on the bus shown in FIG. 6b). Elements, for example, D0x0, D0x1, D0x2, ..., D0 7, with go written in the SDRAM device # D0 10 addresses A0 corresponding, ECC corresponding from the data ECC buffer 520 at the timing of each burst iteration number is written to the SDRAM device #ECC 21 is read.
Thus, the write control logic from the data buffers 510 to 517 and the data ECC buffer 520 to the SDRAM element # D0 10 to the SDRAM element # D7 17 and the SDRAM element #ECC 21 by the access signal generation logic circuit 501 is configured.

Next, read control logic by the access signal generation logic circuit 501 will be described.
For convenience of explanation, the above-described data w0 (r0), w1 (r1), w2 (r2), w3 (r3), w4 (r4), w5 (r5), and the SDRAM element # D0 10 to SDRAM element # D7 17 are described. w6 (r6) and w7 (r7) are written. Therefore, the above-mentioned write data W0, W1, W2, W3, W4 are written in the SDRAM # D0 10, SDRAM # D1 10,..., SDRAM # D7 17, respectively. A control signal including read addresses A0, A1,..., A7 where W5, W6, and W7 are written and ECCE0, E1, E2, E3, E4, E5, E6, and E7 are written in the DRAM element #ECC 21. Shall be supplied.

  SDRAM bytes # D0 10 to # D7 The first 8 bytes read in parallel, that is, SDRAM # D0 10 to D0x0, SDRAM # D1 11 to D0x9, SDRAM # D2 12 to D0x12, SDRAM # D3 13 to D0x1b, SDRAM # D4 14 to D0x24, SDRAM # D5 15 to D0x2d, SDRAM # D6 16 to D0x36, SDRAM # D7 to D0x3f (burst repetition number 0 in FIG. 3, 8h in FIG. 8) r0) are read out to the corresponding data lanes of the data line 4, respectively.

  The read D0x0 is sent to the address 0x0 of the data buffer 510 via the corresponding switch, D0x9 is sent to the address 0x9 of the data buffer 511 via the corresponding switch, and D0x12 is the address 0x12 of the data buffer 512 via the corresponding switch. D0x1b is sent to the address 0x1b of the data buffer 513 via the corresponding switch, D0x24 is sent to the address 0x24 of the data buffer 514 via the corresponding switch, and D0x2d is sent to the address 0x2d of the data buffer 515 via the corresponding switch. D0x36 is written to address 0x36 of data buffer 516 via the corresponding switch, and D0x3f is written to address 0x3f of data buffer 517 via the corresponding switch.

  SDRAM bytes # D0 10 to SDRAM element # D7 17 bytes read in parallel second, ie, SDRAM # D0 10 to D0x1, SDRAM # D1 11 to D0xa, SDRAM # D2 12 to D0x13, SDRAM # D3 13 to D0x1c, SDRAM # D4 14 to D0x25, SDRAM # D5 15 to D0x2e, SDRAM # D616 to D0x37, SDRAM # D717 to D0x38 are read to the corresponding data lanes of data line 4, respectively. (R1 of burst repetition number 1 in FIG. 3, 8h in FIG. 8).

  The read D0x1 is the address 0x1 of the data buffer 511, D0xa is the address 0xa of the data buffer 512, D0x13 is the address 0x13 of the data buffer 513, D0x1c is the address 0x1c of the data buffer 514, and D0x25 is the data buffer 515. At address 0x25, D0x2e is written to address 0x2e of data buffer 516, D0x37 is written to address 0x37 of data buffer 517, and D0x38 is written to address 0x38 of data buffer 510.

  Similarly, 8 bytes sequentially read in parallel from the SDRAM element # D0 10 to the SDRAM element # D7 17 are written in the data buffers 510 to 517, and these reading and writing proceed, and the SDRAM element # D0 10 to the SDRAM element. # D7 8 bytes read in parallel from 8th, that is, SDRAM # D0 10 to D0x7, SDRAM # D1 11 to D0x8, SDRAM # D2 12 to D0x11, SDRAM # D3 13 to D0x1a, SDRAM # D4 14 to D0x23, SDRAM # D5 15 to D0x2c, SDRAM # D6 16 to D0x35, and SDRAM # D717 to D0x3e are respectively read to the corresponding data lanes of data line 4 (burst repetition of FIG. 3). 7, r7 of 8h) of FIG. 8).

  The read D0x7 is the address 0x7 of the data buffer 517, D0x8 is the address 0x8 of the data buffer 510, D0x11 is the address 0x11 of the data buffer 511, D0x1a is the address 0x1a of the data buffer 512, and D0x23 is the data buffer 513. Address 0x23, D0x2c is written to address 0x2c of data buffer 514, D0x35 is written to address 0x35 of data buffer 515, and D0x3e is written to address 0x3e of data buffer 516.

At the end of the writing, R0 (W0 correspondence), R1 (W1 correspondence),..., R7 (W7 correspondence) are written from the first writing position to the eighth writing position of the data buffers 510 to 517. These R0, R1, R2, R3, R4, R5, and R6R7 are 64-bit read data corresponding to the read addresses A0, A1, A2, A3, A4, A5, A6, and A7, respectively.
Along with the writing to the respective data buffers 510 to 517, the corresponding ECC is read from the SDRAM #ECC 21 and sequentially written to the data ECC buffer 520.
Thus, the read control logic from the SDRAM element # D0 10 to the SDRAM element # D717 and the SDRAM #ECC 21 to the data buffers 510 to 517 and the data ECC buffer 520 by the access signal generation logic circuit 501 is configured.

Next, the operation of this embodiment will be described with reference to FIGS.
When data is written to or read from the SDRAM DIMM 1, first, the ROW designated by the RAS signal and the address signal is opened, and then the writing or reading is performed by issuing the CAS signal, the address signal and the write command or the read command. Do. In order to simplify the timing charts shown in FIGS. 6 to 9, a write request or a read request is used as one command. Although the present invention will be described based on this simplified timing chart, the essence of the present invention is not changed.

First, normal writing for sequentially writing 64-bit data eight times will be described. FIG. 6 shows the timing chart.
The write address transferred through the system bus 402 is A0, A1,..., A7 for each cycle T0, T1,..., T7 as shown in FIG. The incoming write data is the write data W0, W1, W2, W3, W4, W5, W6 and W7 on the bus shown in FIG. These write data are, for example, the first 8 bytes [D0x0, D0x1,..., D0x7] in the description of the write control logic by the access signal generation logic circuit 501 and the second 8 bytes [D0x8, D0x9,. D0xf], the third 8 bytes [D0x11, D0x12,..., D0x17],..., The 8th 8 bytes are D0x38, D0x39,.

Each of these write data is sequentially transferred eight times in eight cycles T1 to T8 (6d in FIG. 6)). An ECC is generated for each piece of data by the error detection / correction / code generation circuit 405, and the combined data and ECC data are temporarily stored in the matrix rearrangement logic and buffer 404.
Then, before actually writing data to the SDRAM element, the SDRAM controller 403 issues an SDRAM command (write request) in the T3 cycle as shown in 6f) of FIG.

Data writing is started in T9 to T16 after the command is issued. The data array in this writing is not an array transferred on the bus, but a format converted into the data array shown in FIG. This conversion is performed in accordance with the matrix rearrangement logic and the write control logic of the buffer 404 described above.
After this conversion, writing of the converted data is performed sequentially. During this time, the address lane code signal shown in 6g) of FIG. 6 becomes 0b1000 according to FIG. 2 in order to access all SDRAM elements of the SDRAM DIMM1. As a result, the chip select signal of the SDRAM DIMM 1 is 0b00000000 as shown in 6i) of FIG.

  As a result, eight data (6h in FIG. 6) of the converted data array (w0, w1,..., W7) in SDRAM Write Data [0:63] and the ECC corresponding to the data before conversion (FIG. 6). 6j) E0, E1,..., E7) in SDRAM Write ECC [0: 7] are sequentially written to SDRAM element # D0 to SDRAM # D7 and SDRAM element # ECC21. Specifically, w0, w1,..., W7 are the in-column data of the number of burst repetitions in FIG.

Next, partial writing in which 64-bit data writing (single data writing) is performed once will be described. FIG. 7 shows the timing chart.
The write data transferred via the system bus 402 is W3 as shown in 7d) (write data on the bus) in FIG. This write data W3 is the above-described data W3 [D0x18, D0x19,..., D0x1f], and SDRAM element # D3 specified by the address A3 (address signal on the bus 7b in FIG. 7) transferred in the T0 cycle. 13 is the data to be written to 13. The write data in this example is transferred once in the T1 cycle of the eight cycles T1 to T8. Data in T2 to T7 cycles other than this T1 cycle is NULL. The ECC for the data W3 is generated by the error detection and correction and code generation circuit 405, and the data obtained by combining the data and the ECC is temporarily stored in the matrix rearrangement logic and buffer 404 in the same manner as normal writing. .
Then, before actually writing the data W3 into the SDRAM element, the SDRAM controller 403 issues an SDRAM command (write request) in the T3 cycle, as shown in 7h of FIG.

In T9 to T16 after the command is issued, data writing to the SDRAM DIMM 1 is started. The data array in this writing is not an array transferred on the bus, but a format converted into the data array shown in FIG. This conversion is the same as normal writing.
While this data array is written, the address lane code signal shown in FIG. 7g) in order to access only the SDRAM element # D3 13 and SDRAM element #ECC 21 of the SDRAM DIMM 1 is shown in FIG. According to the distribution rule, it becomes 0b0011, and as a result, the chip select signal of the SDRAM DIMM1 becomes 0b11110111 as shown in 7i) of FIG. The control signal is masked by the control signal filter logic circuit 5, the chip select signal to these SDRAM elements is not transferred, access is prohibited, and internal activation is not performed.
Therefore, each byte of the above-described write data is written in the SDRAM element # D3 13 in the order of D0x1b, D0x1c,..., D0x1a from the initial write position as shown in FIG.
Further, for the SDRAM element #ECC 21, the control signal filter logic circuit 5 uses the SDRAM Write of the write mask signal (7 k in FIG. 7) for the ECC so as to mask writing other than the T12 cycle in which the corresponding ECC data is written. (Mask ECC) is controlled.

Next, normal reading for sequentially reading 64-bit data eight times will be described. FIG. 8 shows the timing chart. Data similar to that described in the read control logic by the access signal generation logic circuit 501, that is, r 0, r 1,..., R 7 is written in the SDRAM elements #D 0 10 to #D 7 17 and SDRAM #ECC 21. Suppose that
When the 64-bit data is sequentially read eight times, the SDRAM controller 403 first issues an SDRAM command (read request) shown in FIG. 8F) via the SDRAM control signal line group 3 in the T1 cycle. Since this command is a normal read command, the address lane code signal (8g in FIG. 8) transferred from the SDRAM controller 3 via the address lane code line 2 becomes 0b1000, and the SDRAM chip select signal (8i in FIG. 8) is output under the control of the signal 0b00000000 for selecting all the chips.

R0, r1,..., R7 (r0, r1,..., R7) of data (8h in FIG. 8) read in parallel from the SDRAM elements # D0 10 to # D7 17 are w0, w1,. ECC) read from SDRAM element #ECC 21 corresponds to 8h) SDRAM Read Data [0:63] in FIG. 8 and 8i) SDRAM Read ECC [0: 7] in FIG. 8, respectively. ,..., E7, output from the T5 cycle, and stored in the matrix rearrangement logic and buffer 404 in the same manner as described in the read control logic. When the storage of all data is completed in the T12 cycle, the data designated by A0, A1,..., A7 is output from the T14 cycle to the system bus 402 (8d in FIG. 8). R0, R1,..., R7).
At the time of this output, error detection and correction, the code generation logic circuit 405 uses the ECC code to correct the data if there is an error.

Finally, an example of partial reading (reading of single data) for reading 64-bit data once will be described. FIG. 9 shows the timing chart. It is assumed that the data described in the partial writing is written in the SDRAM elements # D0 10 to # D717 and the SDRAM #ECC 21.
At the time of partial reading, the SDRAM controller 3 issues an SDRAM command (read request) (9f in FIG. 9) via the SDRAM control signal line group 3 in the T1 cycle. Since this command is a partial read, the address lane code signal on the address lane code line 2 becomes the signal 0b0011 in accordance with FIG. 2, and the control allows only the SDRAM element # 313 and the SDRAM element # ECC21 to be accessed. .
That is, the chip select signal output from the control signal filter logic circuit 5 to the SDRAM DIMM 1 becomes 0b11110111 (9i in FIG. 9), and the control signal to the SDRAM elements other than the SDRAM element # 313 and SDRAM element # ECC21 Therefore, the chip select signal to these SDRAM elements is not transferred, access is prohibited, and internal activation does not occur.

Since such access control is formed, data only from the SDRAM element # 313, that is, 64-bit data, in this example, D0x1b, D0x1c,..., D0x1a are sequentially output from the T5 cycle to T12. On the other hand, the ECC code (9j in FIG. 9) of the SDRAM element #ECC 21 outputs a valid signal only for the T8 cycle.
These data and ECC codes are stored in the matrix rearrangement logic and buffer 404 in the same manner as described in the read control logic. When all storage is completed in the T12 cycle, 64-bit read data (read data R3 on the 9d in FIG. 9) bus is output to the system bus 402 in the T14 cycle. In this example, R3 is D0x18, D0x19, ..., D0x1f.
At the time of this output, error detection and correction, the code generation logic circuit 405 uses the ECC code to correct the data if there is an error.

Since partial access of data to the SDRAM DIMM employs access control to the SDRAM DIMM that does not activate SDRAM elements other than the SDRAM element that is the partial access target, power consumption can be reduced.
In addition, the SDRAM DIMM or the like is also equipped with a low power consumption state setting means such as a power down mode. These are used by switching between a normal state and a low power consumption state by controlling a clock enable signal (CKE: Clock Enable).
If the CKE signal used in this setting means is incorporated in the control signal filter logic circuit so as to appropriately control each SDRAM element, not only the number of SDRAMs activated during partial access is reduced, but also the activation It is also possible to keep the SDRAM element that is not in a low power consumption state, and the power consumption can be further reduced.

In the embodiment of the present invention, even when the reading of data from the SDRAM element is started, the output to the system bus is not performed unless the reading is completed. For this reason, performance is degraded in a memory area where there are many normal accesses.
As a means for avoiding this problem, a data arrangement is performed by rearranging the data according to the present invention only for a memory area having a large number of partial data accesses, and a normal data arrangement is adopted for other data areas. . This can be dealt with by controlling the control signal filter logic circuit as a whole area access in a normal arrangement area and controlling the rearrangement logic and the data rearrangement in the buffer.
In addition, by changing the number of data SDRAM elements to be activated at the time of partial access from 1 to 2, for example, the number of activated SDRAM elements is increased from 2 to 3 including the ECC, Accordingly, the delay caused by the partial access is alleviated and the access speed can be increased.

Thus, according to this embodiment, in partial data access, it is not necessary to activate all SDRAM elements of the SDRAM DIMM, and it becomes possible to maintain a low power state, thereby reducing power consumption. Can be achieved.
Also, by performing ECC error detection and correction via a buffer, the present invention can be applied without impairing these functions, and both system reliability and power saving can be achieved.
Further, if the supply control of the CKE signal to the SDRAM element that is not activated is used together with the activation control of the SDRAM element, the power consumption can be further reduced.

Although the embodiments of the present invention have been described in detail with reference to the drawings, the specific configuration of the present invention is not limited to these embodiments, and the design does not depart from the gist of the present invention. These changes are included in the present invention.
For example, in the embodiment, the present invention has been described by taking an SDRAM element of an SDRAM DIMM as an example of the memory, but the present invention can be equally implemented with other types of memories.
The data buffer may be a register or the like that holds temporary data instead of the storage device. Also in this case, the input / output logic of the register is configured in the same manner as the write control logic and the read control logic in the access signal generation logic circuit 501 described above.
And in any case, those logics are not limited only to the above-mentioned logics.
Further, the number of bit lines of the data line 4 and the data line 402 may be a number other than the number of bit lines shown in the embodiment. The data line (bus) 402 may be bit serial instead of bit parallel.

  The memory module control method, the memory module, and the data transfer apparatus disclosed herein can be used in various information processing apparatuses.

1 is a block diagram showing an electrical configuration of an SDRAM DIMM that is Embodiment 1 of the present invention; FIG. It is a figure which shows the control signal filter rule by the address lane code of the same SDRAM DIMM. It is a figure which shows the memory storage address correspondence table | surface of the same SDRAM DIMM. It is a block diagram which shows the electric constitution of the chip | tip which controls the SDRAM SIMM. It is a block diagram which shows the matrix rearrangement logic of the same SDRAM DIMM, and the structure of a buffer. It is a time chart which shows the operation example in the normal writing of the SDRAM DIMM. 7 is a time chart showing an operation example in partial writing of the SDRAM DIMM. It is a time chart which shows the operation example in normal reading of the SDRAM DIMM. It is a time chart which shows the operation example in the partial reading of the SDRAM DIMM. It is a block diagram of the conventional SDRAM DIMM. It is a timing chart in the case of performing partial writing to the conventional SDRAM DIMM. It is a block diagram of other conventional SDRAM DIMM.

Explanation of symbols

1 SDRAM DIMM (memory module)
2 Address lane code line (line for transferring memory selection signal)
3 SDRAM control signal line group (lines for transferring control signals)
4 data lines 5 control signal filter logic circuit (distribution means)
402 System bus (data bus)
403 SDRAM controller (input means, signal generation means)
404 Matrix rearrangement logic, buffer (data transfer means, data rearrangement means on time axis and space axis)
501 Access signal generation logic circuit (signal generation means)

Claims (16)

When driving any one of the memory modules having a plurality of memories each having a predetermined number of bits, a memory selection signal for selectively supplying a control signal for activating the memory is input to the memory module. ,
A memory module control method comprising activating the memory by distributing the control signal to the memory corresponding to the memory selection signal based on the input memory selection signal. Memory selection for selectively supplying a control signal for activating the memory of any of the memory modules having a plurality of memories capable of writing or reading the first predetermined number of bits in parallel A signal is input to the memory module;
Based on the input memory selection signal, the control signal is distributed to the memory corresponding to the memory selection signal to activate the memory;
The data on the data bus having a second predetermined number of data widths greater than the first predetermined number is converted into a plurality of bit-parallel serial data and sequentially transferred to the activated memory or activated. A method for controlling a memory module, comprising: converting a plurality of serial data sequentially output from the memory into parallel data having the data width and transferring the parallel data to the data bus.   The second predetermined number is a number that is an integer multiple of the first predetermined number, and the serial data is a plurality of pieces of data that sequentially follow the time series of the first predetermined number of bits. 3. The memory module control method according to claim 2, wherein the memory module control method is configured as a converted version.   The memory selection signal selects only a part of the memory when transferring data having a size smaller than the unit of burst transfer defined by the data bus, and when transferring data having a size equal to or larger than the unit. 4. The memory module control method according to claim 2, wherein the memory module control method is generated so as to select all the memories.   When the data transfer amount is smaller than the unit, the memory for storing the detection or correction code is not updated so that the detection or correction code related to the memory other than the memory related to the data transfer is not updated. 5. The memory module control method according to claim 4, wherein a mask signal for memory writing is controlled.   When all the memories are in a low power consumption standby state, when entering a data transfer having a size smaller than the unit, the memory selection signal causes only the memory to be accessed for the data transfer from the standby state. 6. The memory module control method according to claim 2, wherein the memory module control method is generated as a signal for returning to a normal state and maintaining the other memory in the standby state. A plurality of memories configured with a predetermined number of bits;
An input means for inputting a memory selection signal for selectively supplying a control signal for activating the memory when driving any of the plurality of memories;
Distributing means for distributing the control signal to the memory corresponding to the memory selection signal based on the memory selection signal input by the input means. A plurality of memories capable of writing or reading a first predetermined number of bits in parallel;
An input means for inputting a memory selection signal for selectively supplying a control signal for activating the memory when driving any of the plurality of memories;
Distributing means for distributing the control signal to the memory corresponding to the memory selection signal based on the memory selection signal input by the input means;
The data on the data bus having a second predetermined number of data widths larger than the first predetermined number is converted into a plurality of bit parallel serial data sequentially to the memory to which the memory selection signal is distributed by the distributing means. Data transfer means for transferring or converting the plurality of serial data sequentially output from the memory to which the memory selection signal is distributed into parallel data having the data width and transferring the parallel data to the data bus. Features memory module.   The second predetermined number is a number that is an integer multiple of the first predetermined number, and the serial data is a plurality of pieces of data that sequentially follow the time series of the first predetermined number of bits. 9. The memory module according to claim 8, wherein the memory module is configured as a converted one.   The memory selection signal selects only a part of the memory when transferring data having a size smaller than the unit of burst transfer defined by the data bus, and when transferring data having a size equal to or larger than the unit. 10. The memory module according to claim 8, wherein the memory module is generated so as to select all the memories.   When the data transfer amount is smaller than the unit, the memory for storing the detection or correction code is not updated so that the detection or correction code related to the memory other than the memory related to the data transfer is not updated. 11. The memory module according to claim 10, wherein a mask signal for memory writing is controlled.   When all of the memories are in a low power consumption standby state, when entering a data transfer smaller than the unit, the memory selection signal only changes the memory to be accessed for the data transfer from the standby state to the normal state. 12. The memory module according to claim 8, 9, 10, or 11, wherein the memory module is generated as a signal that causes the other memory to return to the standby state and maintain the other memory in the standby state.   The data transfer means is connected to the data bus and generates an access signal. The data transfer means is connected to the data bus and the memory, and is connected to the data bus based on the access signal output from the signal generation means. Are converted into a plurality of bit-parallel serial data and transferred to the memory to which the memory selection signal is distributed, or the plurality of serial data sequentially output from the memory to which the memory selection signal is distributed 13. The apparatus according to claim 8, further comprising a time rearrangement unit that converts the data into data of the data width and transfers the data to the data bus and a data rearranging unit on the space axis. Memory module. Signal generating means connected to a data bus having a data width of a first predetermined number of bits and generating an access signal;
The data bus and a second predetermined number of bits less than the first predetermined number are connected to a predetermined memory among a plurality of memories capable of writing or reading in parallel and output from the signal generating means Based on the access signal, the data on the data bus is converted into a plurality of bit-parallel serial data and transferred to a predetermined memory, or the plurality of serial data sequentially output from a predetermined memory A data transfer apparatus comprising: a time axis for converting data of data width and transferring the data to the data bus; and a data rearranging means on the space axis.   15. The data transfer apparatus according to claim 14, wherein the data rearranging means on the time axis and the space axis includes a data buffer or a data register.   15. The first predetermined number is an integer multiple of a second predetermined number, and data obtained by paralleling the first predetermined number of bits is data that sequentially continues in time series. Or 15. The data transfer device according to 15.

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