JP2001035146A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reading/writing data to a memory under control similar to a storage device of one chip and attaining reduction of power consumption concerning the semiconductor memory device with which plural semiconductor chips are sealed in one package. SOLUTION: Concerning a semiconductor memory device 1 with built-in plural semiconductor chips 2 and 3 provided with memory arrays 22 and 32, this device is provided with control means 21 and 26 for deactivating at least one part of circuits 23 and 27 of the semiconductor chips 2 and 3 when a signal AX+1 of the most significant bits of an address signal is inputted to the respective semiconductor chips 2 and 3 and this signal AX+1 is not a prescribed signal. On the basis of the signal AX+1 of the most significant bit of the address signal, any one of the plural semiconductor chips 2 and 3 is operated and the other semiconductor chip is deactivated so as not to operate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DRAM (Dyna
mic Random Access memory) or SRAM (StaticRandom
The present invention relates to a technique that is useful when applied to a semiconductor memory device such as an access memory and a flash memory, and particularly relates to a technique that is particularly useful when applied to a stacked chip type semiconductor memory device in which a plurality of semiconductor chips are housed in one package.

[0002]

2. Description of the Related Art In recent years, a technique of doubling a memory capacity per area by, for example, stacking and packaging a plurality of memory chips has been put to practical use.

In a conventional storage device 100 having a plurality of semiconductor chips, as shown in FIG.
Independent address spaces are set for each of the memory chips 20, and by selecting one of the chips 110 and 120 by the chip select signals CS1 and CS2, the memory space is switched to the address space corresponding to the selected chip 110 or 120. Had gone. For example, the chip select signals CS1 and CS2 are input as one of the control signals transmitted from the outside via the control line CTL.

To read and write data by accessing such a storage device 100, first, a chip enable signal CE is output to the storage device 100 via a control line CTL to activate the storage device 100,
Next, one of the two chip select signals CS1 and CS2 is output via the control line CTL to select one of the two chips 110 and 120, and thereafter, each chip is independently controlled. set the address signal a ₀ are to a _X, the control signals such as write enable signal WE indicating the control contents of the read / write, and transmits the data signal D ₀ to D _Y performs memory access.

[0005]

However, in the conventional memory device having a plurality of chips, although the memory capacity per unit area is increased, any one of the chip select signals CS1 and CS2 is output at the time of accessing the memory. However, since it is necessary to select one of the chips, the control processing of the entire memory access (for example, memory access over two chips) is complicated. Furthermore, since a plurality of independent memory address spaces must be handled for each chip, there is a problem that processing related to addresses such as comprehensive address assignment becomes complicated.

Incidentally, in a typical semiconductor memory device, 1
In general, one chip is built in one package. And in memory modules etc.
A plurality of such semiconductor storage devices are mounted on one electronic board, and a controller for controlling the entirety of the plurality of semiconductor storage devices is mounted on the same board.

However, as described above, a stacked chip type semiconductor memory device in which a plurality of memory chips are sealed in a single package has two types of chip select in a single package despite the appearance of a single memory. Signal C
Since S1 and CS2 are input, there is a problem that the number of external terminals is increased by one as compared with a one-chip semiconductor memory device. Therefore, when a stacked chip type semiconductor memory device is mounted on a substrate to form a memory module, it is not possible to use a controller and a system substrate of the conventional standard, and it is necessary to change the design of the controller and the substrate wiring. However, there was a problem that the development was delayed.

[0008] In recent years, semiconductor memories such as DRAMs and flash memories have been increasingly used in portable electronic devices. Therefore, reducing the power consumption of semiconductor memories has become an important issue. However, in the conventional stacked chip type semiconductor memory device, while one chip is selected and accessed for memory, each circuit (for example, a memory array, an address buffer, an I / O buffer, an address decoder, etc.) of the other chip is used. ) Were also constantly activated, increasing power consumption.

An object of the present invention is to provide a semiconductor memory device having a plurality of semiconductor chips, only by changing the setting of the address space, and thereafter making it possible to access the memory under the same control as the one-chip memory device. It is to provide a semiconductor memory device.

Another object of the present invention is to provide a semiconductor memory device capable of reducing power consumption.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a semiconductor memory device having a plurality of built-in semiconductor chips having a memory array, a signal of a predetermined bit (for example, the most significant bit) of an address signal is input to each semiconductor chip, and the signal corresponds to each chip. Control means for inactivating at least a part of the circuit of the semiconductor chip when the signal is not a predetermined signal (for example, a low-level signal or a high-level signal). One of the semiconductor chips is operated, and the other semiconductor chips are deactivated so as not to operate.

According to such means, the chip selection is performed based on the predetermined bit signal of the address signal. Therefore, it is not necessary for the external device accessing the semiconductor memory device to increase the chip select signal. This can be dealt with simply by adjusting the setting of the memory address space to each semiconductor memory device. Therefore, for an external device accessing the semiconductor memory device, the access processing is simplified as compared with the conventional access to the semiconductor memory device having a plurality of memory chips, and the semiconductor memory device having one chip is built in. Similarly, it can be accessed with simple processing.

Furthermore, even when this semiconductor memory device is mounted on a printed circuit board or the like to create an arbitrary system, a printed circuit board on which a semiconductor memory device having the same storage capacity is mounted or a plurality of mounted semiconductor memory devices is used. As a controller for external control, a conventional controller can be used as it is, or a one-chip semiconductor memory device having the same storage capacity and the semiconductor memory device of the present invention can be used in combination.

Further, when memory access is performed to one semiconductor chip, since a part of the circuit is inactivated in the other semiconductor chip, power consumption can be reduced accordingly.

[0017] The above-mentioned means is provided such that a plurality of semiconductor chips are stacked and sealed in one package, and a control terminal connected to a control signal line and an address terminal connected to an address signal line are provided outside the package. This is particularly useful in a stacked chip type semiconductor memory device provided with I / O terminals (data terminals) connected to data signal lines.

Desirably, terminals corresponding to input / output terminals (control signals, address signals, data signals, and respective input / output terminals) of a plurality of semiconductor chips are not used as independent external terminals. It is configured to be shared and connected to external terminals. As a result, when viewed from the outside, the terminal configuration becomes exactly the same as that of a one-chip memory, and can be handled in the same manner as a one-chip semiconductor memory device.

More specifically, the circuit inactivated by the control means includes an address data buffer circuit (address buffer) and / or an input / output data buffer circuit (I / O buffer). It can be. Further, by providing a means for shutting off the power supply by shutting off the power supply voltage and ground potential of the circuits, the power supply of these circuits is cut off and deactivated, thereby further reducing the power consumption. Can be done.

Preferably, an address counter for automatically generating an address is provided for each of the plurality of semiconductor chips, and when a bit of the address counter corresponding to a predetermined bit of the address terminal changes, the change causes a data access. The following address generation is performed in cooperation with the address counter of the resulting semiconductor chip. According to this configuration, control of a continuous access mode (for example, page mode) in which continuous writing and reading of data can be performed by one address input can be performed under the same control as that of a one-chip storage device.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the present invention will be described below with reference to FIGS.

[First Embodiment] FIG. 1 is a block diagram showing a memory (semiconductor memory device) 1 according to a first embodiment of the present invention, and FIG. (A) is an external perspective view, and (b) is a longitudinal sectional view.

The memory 1 of this embodiment is a stacked chip type flash memory in which two semiconductor chips 2 and 3 are stacked and packaged, and a control terminal, an address terminal, an I / O External terminals 51 such as terminals and power supply terminals are provided. The control terminal is connected to a control signal line for transmitting a control signal, the address terminal is connected to an address signal line for transmitting an address signal, and the I / O terminal is a data signal for transmitting and receiving the I / O signal. It is connected to the wire. As shown in FIG. 2B, for example, the semiconductor chips 2 and 3 are bonded to each other on the back surfaces of the chips with an adhesive and fixed inside the package 50 via a cushioning material such as silicon rubber. Pads, which are terminals of each of the semiconductor chips 2 and 3, are connected to external terminals 51 on the package substrate 50a side, for example, via bonding wires 53 made of gold.

The two semiconductor chips 2 and 3 have substantially the same configuration. The semiconductor chip 2, which is one of them, has a memory mat (memory array) 22, in which a large number of memory cells are arranged in a matrix, a normal address buffer 23, which captures and holds address signals of memory cells to be accessed. An X decoder 24 that decodes an address signal to set a corresponding word line in memory mat 22 to a select level, and a Y decoder 25 that sets a corresponding bit line to a select level, from a memory cell selected according to an address signal An I / O buffer 27 for accumulating read data and external write data, a chip select address buffer 26 for holding a chip select signal, and outputting an activation signal to the address buffer 23 and the I / O buffer 27. Write data by stopping and activating or deactivating Control circuit 21 or the like for controlling and reading is provided.

The storage capacity of the memory mat 22 is half the capacity corresponding to the address signals A _{0 to} A _{X + 1} input from the outside. Normally, the signals input to address buffer 23 are lower-order X-bit signals A _{0 to} A _X of address signals A _{0 to} A _{X + 1} , and the memory capacity of memory mat 22 corresponds to lower-order X-bit signal A 0. which corresponds to ₀ ~A _X.

The chip select address buffer 26 has 1
While a low-level (Vss) or high-level (Vcc) activation signal is input from one input terminal, a signal A _{X +} of the most significant bit of an address signal input from another external terminal (address terminal T _AD ) is input. ₁ is entered. If the activation signal is low level (Vss), this chip 2 is used when the signal A _{X + 1} of the most significant bit is a low level signal.
Is output to the control circuit 21 indicating that is selected, and if the signal AX _{+ 1} is a high-level signal, the chip select signal CS is not output. In this embodiment, the activation signal of the chip select address buffer 26 is supplied at a low level by fixing a predetermined external terminal of the chip to the power supply voltage Vss. However, the activation signal of the chip select address buffer 26 is controlled by the control circuit 21 to control its input, and based on the input of an external chip enable signal CE, Vcc or Vss.
May be input.

On the other hand, a high level (Vcc) is input as an activation signal to the chip selection address buffer 36 of the chip 3, whereby the signal A _{X + 1} of the most significant bit is output in contrast to the case of the chip 2. A valid chip select signal CS is output to the control circuit 31 in the case of a high level signal.
Output to Thus, chip 2,
At level 3, the chip select address buffers 26, 3
6 has the same configuration. Instead of supplying Vss and Vcc as activation signals to the chips 2 and 3 respectively, Vss (or Vcc) is commonly supplied and the package substrate 5 is supplied.
It provided an inverter circuit in the middle of the signal line for supplying the most significant bits of the address terminal T _AD on 0a, configured to provide a signal obtained by inverting the signal (most significant bit) supplied to the chip 2 to the tip 3 By doing so, a contrasting operation similar to the above may be performed.

The control circuit 21 receives an I / O signal based on an external chip enable signal CE and a chip select signal CS from a chip select address buffer 26.
The O buffer 27 and the normal address buffer 23 are activated, and the X decoder 24, the Y decoder 25,
A driver circuit (a sense amplifier, a precharge circuit, an erase circuit, etc.) of the memory mat 22 is activated. The activation / deactivation of each circuit is performed by connecting / cutting off the power supply voltage Vcc and connecting / cutting off the ground potential Vss. The control circuit 21 also receives an external write enable signal W indicating write / read control contents.
E by switching the I / O buffer 27 etc.
Controls reading.

Next, the operation of the memory 1 configured as described above will be described.

When the chip enable signal CE is not inputted from the outside, the memory 1 is in the power save mode, only the control circuits 21 and 31 and the chip select address buffers 26 and 36 are activated, and the other circuits are deactivated. You. In addition, DRA which needs refresh
In the case of a storage device such as M, a control circuit for performing self-refresh is also activated.

To access the memory from the outside, first,
The chip enable signal CE is input. Then, the necessary circuits are activated by the control circuits 21 and 31. In the case where the chip selection address buffers 26 and 36 are activated by the control circuits 21 and 31, the chip selection address buffer 2 is activated at this timing.
An activation signal is output to 6, 36 to activate the buffer.

Next, during the input of the chip enable signal CE, the address signals A _{0 to} A _{X + 1} and the write enable signal WE for instructing whether to read or write data are input from outside. At this time, the signal A _{X + 1} of the most significant bit of the address signal is input to the chip select address buffers 26 and 36 of both chips 2 and 3, respectively. If the signal A _{X + 1} of the most significant bit is at a low level, a chip select signal CS is output from the chip select address buffer 26 of the chip 2 on the lower address side to the control circuit 21 while a chip select signal CS on the upper address side is output. 3
In this case, the chip select signal CS is not output from the chip select address buffer 36.

When a valid chip select signal CS is input to the chip 2 on the lower address side, the control circuit 21 controls the normal address buffer 23, I / O
The buffer 27, the X decoder 24, the Y decoder 25, the driver circuit of the memory mat 22, and the like are activated to enable memory access. While the chip select signal CS is being output, the address signals A ₀ -A
_{Since X + 1} is input, the address signals A _{0 to} A _{X + 1}
X signals A _{0 to} A _X excluding the most significant bit are latched in the normal address buffer 23.

On the other hand, in the upper address side chip 3 to which the valid chip select signal CS is not input, the normal address buffer 33, the I / O buffer 37, the X decoder 34, the Y decoder 35, the driver circuit of the memory mat 32, etc. Is inactive and does not accept memory access.

Then, external address signals A ₀ -A
After the input of _{X + 1} , data input / output to / from the memory mat 22 is performed after a preset time has elapsed. That is, in the case of data reading, the data stored in the memory cells corresponding to the address signals A _{0 to} A _X is read out, latched by the I / O buffer 27, and stored in the data terminal T _{I / O.}
Is output to In the case of data write, the control terminal T _CTL write enable signal WE indicating the writing is input from, I / O terminals T _{I / O} write from the data D ₀ to D _Y is input, the The data D _{0 to} D _Y are written to the selected memory cell in the memory mat 22 via the I / O buffer 27 and the Y gate circuit of the Y decoder 25.

In a flash memory or the like,
The process of writing data to the memory 1 is not performed for each of the _{0 to Y} bit data D ₀ to DY input / output at a time, but is temporarily stored in the I / O buffers 27 and 37 until a predetermined amount of data is obtained. After that, the write control is performed inside the chip by the control circuits 21 and 31, and the stored predetermined amount of data is collectively written to the memory mats 22 and 32. In the case of this method, during write control inside the chip, data input from the outside is temporarily stopped, and after the write control is completed, an end signal is transmitted to the outside to restart data input.

On the other hand, when the address signals A _{0 to} A _{X + 1} are input and the signal A _{X + 1} of the most significant bit is at a high level, the chip 3 on the upper address side is activated. And the chip 2 on the lower address side is inactivated and cannot be accessed. Then, the activated upper address side chip 3 reads or writes data according to the same operation as that described above.

As described above, according to the memory 1 of this embodiment, the signal A of the most significant bit of the address signals A _{0 to} A _{X + 1} is used.
_Since either the chip 2 on the lower address side or the chip 3 on the upper address side in the package is selected by _{x + 1,} the external device accessing the memory 1 increases the chip select signal to perform complicated control. No need to
This can be dealt with simply by adjusting the setting of the memory address space. That is, as compared with the case of accessing a conventional semiconductor memory device in which a plurality of chips are packaged, external memory access processing can be performed by a simple process as in the case of a one-chip semiconductor memory device.

Furthermore, even when this memory is mounted on a printed circuit board or the like to create an arbitrary system, a printed circuit board used for a one-chip memory having the same storage capacity and a plurality of mounted memories are externally controlled. A conventional controller can be used as it is, and a one-chip memory of the same capacity and the memory 1 of this embodiment can be used in combination.

Also, in the memory of this embodiment, while the memory access to one semiconductor chip 2 is being performed, most circuits in the other semiconductor chip 3 are inactive as described above. Power consumption is reduced.

The input / output terminals (control signal, address signal, data signal, and respective input / output terminals) of the semiconductor chips 2 and 3 are shared by corresponding terminals.
The external terminals T _CTL ,
Since it is exposed to the outside as T _AD and T _{I / O} , when viewed from the outside, it has exactly the same terminal configuration as a one-chip memory, and can be handled in exactly the same way as a one-chip memory.

Note that the semiconductor chips 2 and 3 of the first embodiment
Can use the chip to constitute a memory of a normal package in which only one chip is mounted in the package.

FIG. 3 is a block diagram in the case where a one-chip normal package is formed using the same semiconductor chips as in the first embodiment. Reference numeral 4 denotes a chip having the same configuration as the chip 2 or 3 in FIG.

In this embodiment, the signal line 46a of the chip select address buffer 46 (the signal line to which the most significant bit A _{X + 1} of the address signal is input) and the input / output terminal of the activation signal are connected by a circuit outside the chip, for example. Always fixed (pulled up) to high level. As a result, the chip is always activated. In this case, the number of bits of the address of the chip is one bit smaller than that of the memory 1 of the first embodiment. As a result, the same memory package as the conventional one-chip memory is formed.

[Second Embodiment] FIG. 4 is a block diagram showing a memory 1B according to a second embodiment of the present invention.

The memory 1B of this embodiment includes the chips 7,
8 are provided with chip selection address counters 78 and 88 to automatically generate addresses, thereby enabling the two chips 7 and
It enables reading and writing of continuous data over eight intervals. Other circuits (control circuit 7
1, 81, memory mats 72, 82, normal address buffers 73, 83, X decoders 74, 84, Y decoder 7
5, 85, chip select address buffers 76, 86, I
/ O buffers 77 and 87) have substantially the same configuration as that of the first embodiment.

The control signals externally input to the control terminal TCTR include a new mode select signal MS.
Is added. Based on the input of the mode select signal MS, the control circuits 71 and 81 output control signals to the chip select address counters 78 and 88 and operate the chip select address counters 78 and 88.
Are configured to be active when the chip enable signal CE is input to the memory 1B, regardless of the signal A _{X + 1} of the most significant bit of the address signal.

The chip selection address counters 78 and 8
Reference numeral 8 denotes a counter having the same number of bits as the address signals A _{0 to} A _{X + 1} and further has a function of loading data of the address signals A _{0 to} A _{X + 1} output to the address lines. Count is initiated signals A _{X + 1} most significant bits of the address signal A ₀ ~A X + ₁ as a trigger, and load addresses, the address signal A ₀ ~A X + ₁ of the most significant bit of the signal This is performed using A _{X + 1} as a trigger.

For example, when activated by a control signal from the control circuit 71, the chip selection address counter 78 on the lower address side firstly activates the most significant bit of the externally input address signals A _{0 to} A _{X + 1.} Signal A _{X + 1}
When the signal A _{X + 1} is at a low level, the remaining address signals A _{0 to} A _X are loaded and set as their own count values. Then, the count is incremented by "1" every predetermined period. The count is calculated by the control circuit 71,
The process is terminated based on the termination of the control signal from 81. On the other hand, when the input most significant bit signal A _{X + 1} is at the high level, the counting is not performed.

When the input most significant bit signal A _{X + 1} is at a high level, the chip address selector 88 on the upper address side loads the address signals A ₀ -A _X and sets them as its own count value. Is incremented by "1" every predetermined period. On the other hand, when the input most significant bit signal A _{X + 1} is at the low level, the counting is not performed.

These chip selection address counters 78,
The count data of 88 is stored in the normal address buffers 73 and 83 and the chip select address buffer 7 on the same chip.
6, 86, and is also output to the chip select address counters 78, 88 of the adjacent chip via the address line. For example, during counting of the chip selection address counter 78 on the lower address side, the lower 0 to lower 0 of the count data is counted.
The X-bit signal is input to the normal address buffer 73 and the most significant 1-bit signal is input to the chip select address buffer 76. At the same time, the count data is sent to the chip select address counter 88 of the next chip via the address line. Is also output to Then, by this output, it is transmitted that the most significant signal is inverted during the progress of the count, and the chip select address counters 7 of both chips 7 and 8 are transmitted.
At 8,88, cooperation is achieved as follows.

Next, the chip selection address counter 7
Operation of continuous memory access using 8,88 (1
The operation of continuously performing a plurality of memory accesses by inputting the address signal twice) will be described in more detail.

When performing continuous memory access,
First, a mode select signal MS is input from the outside via the control terminal _TCTL to select the continuous access mode. Then, predetermined control signals are output from control circuits 71 and 81 of both chips 7 and 8, and chip select address counters 78 and 88 are activated.

Next, address signals A _{0 to} A _{X + 1 of} the head address for data access are externally input. When an address signal is input, the most significant bit signal A
_If the signal is at a low level in response to _{X + 1} , the lower address side chip selection address counter 78 loads address data and starts counting, and the upper address side chip selection address counter 88 enters a standby state. The counting is not performed until the signal A _{X + 1} of the most significant bit is changed to the high level.

On the other hand, if the signal A _{X + 1} of the most significant bit of the input address signal is at a high level, the chip selection address counter 88 on the upper address side loads address data and starts counting, and at the same time, starts counting. The address-side chip selection address counter 78 is in a standby state and does not count until the signal A _{X + 1} of the most significant bit becomes low level.

During these counts, when the most significant bit of the count data carries up and the data of the most significant bit is inverted, the count data is output to the outside, so that the most significant bit of the address signal line is output. Signal A
_{X + 1 is} also inverted from high level to low level or from low level to high level.

As described above, when the count advances and the signal A _{X + 1} of the most significant bit is inverted, the chip selection address counter 78 (,
88) stops counting and enters a standby state, while the chip selection address counter 88 (,
In step 78), the count data value output to the address signal line is loaded to start the subsequent counting, and the continuous counting operation is performed.

During data writing during the above-described series of counting, data input from the outside to the memory is performed continuously for a predetermined period at a preset cycle so as to synchronize with the counting. When reading data,
Data output from the I / O buffers 77 and 87 to the outside is performed in synchronization with the count. The write operation and the read operation are the same as the operations described in the first embodiment.

It is to be noted that writing of data to the memory 1B is not performed for each of the data D _{0 to} D _{Y of 0 to Y} bits input / output at a time as in a flash memory or the like.
I / O buffers 77 and 8 are temporarily stored until a predetermined amount of data is obtained.
7 and then write control is performed inside the chip to collectively write a predetermined amount of stored data to the memory mats 72 and 82.
While writing is performed by the chip 7 on the lower address side,
The chip 8 on the upper address side accumulates data and alternately repeats the data, thereby enabling a continuous writing process. By this control, the total predetermined time required for the writing process can be reduced.

As described above, according to the memory 1B of this embodiment, it is possible to handle the memory in exactly the same manner as a one-chip memory, and to reduce the power consumption. In addition, the chip selection address counters 78 and 88 that automatically generate addresses enable continuous data access by automatically generating addresses, and enable continuous data access between two chips 7 and 8. Since the chip selection address counters 78 and 88 of both chips 7 and 8 cooperate to continue counting addresses, a continuous access mode (for example, a page mode) can be realized by the same control as a one-chip memory.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in the above-described embodiment, a laminated chip type semiconductor memory device constituted by laminating two semiconductor chips has been described as an example, but not two but three or more semiconductor chips are collectively collected. Alternatively, the chip mounting format and the package format are not particularly limited.
When three or four semiconductor chips are used, a 2-bit signal among address signals may be assigned for chip selection.

It is desirable that the signal for selecting one of the plurality of chips be the most significant bit signal A _{X + 1} of the address signals A _{0 to} A _{X + 1} , but the least significant bit signal A _{X + 1} is selected.
The signal may be 0 or an intermediate bit signal.

Further, the write control and read control sequence for the memory mat is not limited to the method specifically shown in this embodiment, and it goes without saying that there are various modifications.

In the above description, the invention made by the present inventor has been mainly described with respect to a flash memory which is a field of application which is the background of the invention. However, the present invention is not limited thereto, and various types of semiconductor memory such as DRAM and SRAM can be used. Can be widely used in equipment.

[0066]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, a chip is selected from a plurality of built-in semiconductor chips by a signal of a predetermined bit of an address signal. There is an effect that access can be made by simple processing as in the semiconductor memory device described above.

Further, when memory access is performed to one of the built-in semiconductor chips, the circuit is inactivated in the other semiconductor chip, so that power consumption can be reduced accordingly. effective.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first preferred embodiment of a memory to which the present invention is applied.

FIGS. 2A and 2B show a package structure of a memory according to a first embodiment, wherein FIG. 2A is an external perspective view and FIG. 2B is a longitudinal sectional view.

FIG. 3 is a block diagram in the case of forming a one-chip normal package using the semiconductor chip of the first embodiment.

FIG. 4 is a block diagram showing a second preferred embodiment of a memory to which the present invention is applied;

FIG. 5 is a block diagram showing an example of a conventional stacked chip type semiconductor memory device.

[Explanation of symbols]

Reference Signs List 1 memory (semiconductor storage device of first embodiment) 2, 3 semiconductor chip 21, 31 control circuit (control means) 22, 32 memory mat (memory array) 23, 33 normal address buffer 24, 34 X decoder 25, 35 Y Decoders 26, 36 Chip selection address buffer (control means 27, 37 I / O buffer 50 Package 51 ... External terminal 1B Memory (semiconductor storage device of second embodiment) 7, 8 Semiconductor chip 78, 88 Chip selection address counter (address) Counter) T _CTL control terminal T _AD address terminal T _{I / O} data terminal CS Chip select signal CE Chip enable signal A ₀ -A _{X + 1} address signal

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (reference) G11C 11/401 G11C 11/34 301E 16/02 345 371K 17/00 601Z F-term (reference) 5B015 JJ00 JJ07 KB32 KB33 KB42 KB45 KB47 KB74 PP03 5B024 AA01 AA11 BA17 BA18 BA29 CA16 CA21 CA27 5B025 AD00 AD01 AD02 AE00 AE06 5B060 AB18 CA11 MM16 MM19

Claims (6)

[Claims] A plurality of semiconductor chips each including a memory array; and external terminals including a control terminal connected to a control signal line, an address terminal connected to an address signal line, and an I / O connected to a data signal line. A semiconductor memory device provided with an O terminal, wherein a plurality of semiconductor chips are connected to a predetermined bit terminal of the address terminal, and a predetermined signal corresponding to each semiconductor chip is input from the predetermined bit terminal. Control means for inactivating at least a part of the circuit of the semiconductor chip when not performed, and operating any one of the plurality of semiconductor chips based on a signal of the predetermined bit of an address terminal, A semiconductor memory device characterized in that a semiconductor chip is configured to be inactivated and not operated. 2. The method according to claim 1, wherein the plurality of semiconductor chips are stacked to form one
2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is enclosed in one package. 3. The plurality of semiconductor chips each include a terminal for inputting and outputting a control signal, an address signal, and a data signal, and the corresponding terminals are shared among the plurality of semiconductor chips and provided outside the package. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is connected to an external terminal. 4. The circuit according to claim 1, wherein said circuit deactivated by said control means is an address signal buffer circuit and / or an input / output data signal buffer circuit. 13. The semiconductor memory device according to claim 1. 5. The control means according to claim 1, wherein said control means is configured to deactivate circuits to be deactivated by stopping power supply to those circuits.
5. The semiconductor memory device according to any one of items 1 to 4, 6. The plurality of semiconductor chips are provided with an address counter for automatically generating an address, and the data value of the bit of the address counter corresponding to the predetermined bit of the address terminal changes according to the count by the address counter. 6. The semiconductor memory device according to claim 1, wherein, in this case, an address counter of another semiconductor chip performs a subsequent address generation in cooperation with the change.