JP2003249087A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with an address signal transfer circuit in which applying needless stress to a specific data storage region is prevented. <P>SOLUTION: The device is provided with a memory cell array, a decoding circuit performing selection of a memory cell of this memory cell array, an address signal transfer circuit having a transfer circuit transferring an address signal to the decoding circuit and an initialization circuit initializing a transferred internal address signal, and a reset circuit controlling the initialization circuit of the address signal transfer circuit by a reset signal generated on the basis of at least one of power-on detection or a signal from the outside and initialing the internal address signal. A row address signal transfer circuit 82 has a transfer path 30 and a latch circuit 40 being the initialization circuit. The latch circuit 40 initializes an internal row address signal to an all '1' state in which the head block to which an address initial value is allotted is not selected but the end block is selected by the reset signals PWRON and RST. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device whose internal address is initialized by detection of power-on, command input, or the like.

[0002]

2. Description of the Related Art Conventionally, a semiconductor memory such as an EEPROM is provided with a function of initializing an internal address to address 0 at power-on or by forced reset by command input. To initialize such an internal address, the address signal transfer circuit is provided with an initialization circuit.

FIG. 11 shows the configuration of a conventional row address signal transfer circuit for one bit of row address data. Inverter 61 and clocked inverter 6
The portion 2 is the transfer path of the internal row address signal. When the row address enable signal AE is “H”, the row address signal Add output from the address register is
The internal row address signal is transferred from the inverters 61 and 62 and sent to the decoding circuit.

A latch circuit composed of a NAND gate 63 and a clocked inverter 64 is connected to the output node N of the row address signal transfer circuit as an initialization circuit. A signal LOWVDD which becomes “L” is input to the NAND gate 63 at the time of power-on or when a command is issued to instruct a forced reset. At this time, the row address enable signal AE is "L", the clocked inverter 62 in the transfer path is off, and the clocked inverter 64 in the latch circuit section is on. Therefore, LOWVD
When D = “L” is input, the node N becomes “L”, which is fed back to the NAND gate 63, and the output node N thereafter holds “L”.

The row address selects a block of the EEPROM cell array and a word line in the block. By this row address reset, the row address signal becomes all “0” (address initial value), and the address 0 (first block of the cell array) to which the address initial value is assigned is initialized to a selected state.

[0006]

In the EEPROM, special information relating to the entire system such as device management information is often written at address 0 which is the head block of the cell array. Further, the EEPROM module and the power supply may be unintentionally removed and inserted even after the system is powered on. In such a situation, when the address is initialized to address 0 as in the conventional address signal transfer circuit, unnecessary stress is applied to the area storing the management information of the activated EEPROM, and important data May be destroyed.

An object of the present invention is to provide a semiconductor memory device having an address signal transfer circuit for preventing unnecessary stress application to a specific data storage area.

[0008]

In a semiconductor memory device according to the present invention, a memory cell array, a decode circuit for selecting a memory cell of the memory cell array, and a transfer path for transferring an address signal to the decode circuit are transferred. An address signal transfer circuit having an initialization circuit for initializing an internal address signal, and a reset signal generated based on at least one of power-on detection and an external signal controls the initialization circuit of the address signal transfer circuit. And a reset circuit for initializing an internal address signal. The initialization circuit of the address signal transfer circuit selects a storage area excluding a storage area to which an initial address value of the memory cell array is assigned by the reset signal. Is configured to initialize the internal address signal to the That.

According to the present invention, at the time of forced reset, the storage area other than the storage area to which the address initial value is allocated is initialized to a selected state, so that the storage area to which the normal address initial value is allocated. It is possible to prevent unnecessary stress on the user.

Specifically, assuming that the storage area to which the initial address value is assigned is an area for storing the memory management information, the data in the memory management area deteriorates even if the memory is removed and inserted after the forced reset. Is prevented.

Specifically, in the present invention, the memory cell array is divided into a plurality of blocks selected by a row address signal, and the first block of the plurality of blocks to which a row address initial value is assigned stores memory management information. In this case, the reset circuit causes the initialization circuit of the part of the address signal transfer circuit that transfers the row address signal to select the internal row address from the blocks other than the first block among the plurality of blocks. It is configured to initialize the signal.

The semiconductor memory device according to the present invention also includes a memory cell array, a decode circuit for selecting a memory cell of the memory cell array, a transfer path for transferring an address signal to the decode circuit, and an internal address signal transferred. And an internal address signal by controlling the initialization circuit of the address signal transfer circuit by a reset signal generated based on at least one of a power-on detection signal and an external signal. A reset circuit for initializing the, and an initialization circuit of the address signal transfer circuit, by the reset signal,
And a reset address setting circuit for setting a reset address for initializing an internal address.

By thus adding the reset address setting circuit, the reset address (initialization address)
Can be set appropriately. As a result, when the reset address is fixed, it is possible to prevent the cell at that address from being overstressed.

The reset address setting circuit has, for example, a latch circuit that holds a reset address supplied from outside the chip. Alternatively, it is assumed that the chip includes a reset address storage circuit that stores a reset address, and the reset address setting circuit has a latch circuit that holds the reset address read from the reset address storage circuit.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows the structure of an EEPROM according to an embodiment of the present invention. The memory cell array 1 is an EEPROM cell array in which electrically rewritable nonvolatile memory cells are arranged. EEP
The ROM cell array 1 is divided into a plurality of blocks B0, B1, ... As shown in FIG. 5, for example, and each block serves as a data erasing unit.

A row decoder 5 selects a block of the memory cell array 1 and a word line in the block.
A column decoder (including a column gate) 4 performs bit line selection. The bit line of the memory cell array 1 is connected to the sense amplifier 2. The sense amplifier 2 and the data register 3 holding the write data are connected to the external I / O terminal via the data line and the I / O buffer 6.

An address signal supplied from the outside via the I / O buffer 6 is held in the address register 7, and the command is transferred to the control circuit 9. Address register 7
The address signal held in the address signal transfer circuit 8
To the row decoder 5, the column decoder 46, and the chip address determination circuit 12 via.

The control circuit 9 controls the timing of the address register 7 according to an operation mode such as writing / erasing, and outputs an enable signal for instructing the address signal transfer circuit 8 to transfer an internal address signal. The power-on circuit 11 is a reset circuit in a broad sense, detects the power-on and sends the reset signal PWR to the address signal transfer circuit 8.
Turn on. The reset circuit 10 uses the address signal transfer circuit 8 based on a reset command supplied from the outside.
A signal RST for resetting (initializing) is output.

FIG. 2 shows a specific configuration of the address signal transfer circuit 8. The address signal transfer circuit 8 has a chip address signal transfer circuit 81, a row address signal transfer circuit 82, and a column address signal transfer circuit 83. The chip address signal transfer circuit 81 is activated by the chip address enable signal CHE and internally transfers the chip address signal CHAdd. The row address signal transfer circuit 82 is activated by the row address enable signal RAE and internally transfers the row address signal RAdd. The column address signal transfer circuit 83 is activated by the column address enable signal CAE and internally transfers the column address signal CAdd.

These address signal transfer circuits 81 and 8
Reference numerals 2 and 83 have basically the same structure, and together with an address signal transfer path, a power-on signal PWRON generated by detecting power-on or a reset signal RST generated by an external command An initialization circuit for initializing an address is provided.

The above address signal transfer circuits 81, 82,
Of the 83, the chip address signal transfer circuit 81 and the column address signal transfer circuit 83 have the same configuration as the conventional one shown in FIG. The row address signal transfer circuit 82
At least a part related to block selection has a configuration different from the conventional one. As an example, the EEPROM cell array 1 is
It is assumed that the 8-block configuration is as shown in FIG. Of the eight blocks, the row address initial value, that is, the block address BA <0: 2) = (0,0,0) is assigned to the first block B0 (0th address) and the last block is 7th address. So, BA <0: 2> = (1,1,
It shall be selected according to 1).

At this time, the row address signal transfer circuit 82
All, or at least the upper address portion related to block selection, that is, the block address BA <0: 3 in FIG.
> The corresponding part is configured as shown in FIG. The address signal transfer path 30 is formed by interposing an inverter 31 and a clocked inverter 32 between the input node N1 and the output node N2, as in the conventional case. When the clocked inverter 32 is activated by the row address enable signal RAE, the row address signal RAdd output from the address register 7 is transferred to the output node N2.

A latch circuit 40 forming an initialization circuit is provided at the output node N2. Latch circuit 40
Has a NAND gate 41 whose output node N2 is fed back through an inverter 44, the output of which is an inverter 4
2 and the clocked inverter 43 to output node N
Connected to 2. A signal which becomes "L" at the time of power-on or at reset is input to the other input node N0 of the NAND gate 41.

Output reset signal RS of reset circuit 10
T is "L" at the time of reset, and the output reset signal PWRON of the power-on circuit 11 is "H" at the time of power-on. The former is directly input to the NAND gate 46, and the latter is inverted by the inverter 45 and enters the NAND gate 46. The output of the NAND gate 46 is further passed through the inverter 47 to the NAND gate 4
1 input node N0.

The operation of the row address signal transfer circuit 82 thus constructed will be described with reference to FIG. At power-on, when the output PWRON of the power-on circuit 10 becomes "H" (time t0), the output of the NAND gate 46 is "H", and therefore the input node N0 of the NAND gate 41 is
Becomes "L". Enable signal RAE at power-on
Is “L”, the transfer path 30 is off, and the latch circuit 40 is
, The clocked inverter 43 is on. Therefore, the output node N2 becomes "H", which is inverted by the inverter 44 and fed back to the NAND gate 41, and the latch circuit 40 holds the "H" output state.

As a result, at least the upper address of the row addresses, that is, the block address BA <in FIG.
0: 2> becomes all “1”, and the end block B7 in the EEPROM cell array is initialized to the selected state.

When the address enable signal RAE becomes "H" (time t1), the latch circuit 40 is turned off, the transfer path 30 is turned on, and the row address signal RAdd supplied to the input node N1 is transferred through the transfer path 30. Then, the data is sent to the row decoder for normal access.

When the output signal RST of the reset circuit 10 becomes "L" by the command input from the outside (time t
2) The output node N2 becomes "H" by the same operation as at power-on, and this state is held by the latch circuit 40. That is, also in this case, the tail block B7 in the EEPROM cell array is reset to the selected state.

As described above, according to this embodiment, after the power is turned on or after the forced reset, the row address signal RAadd becomes all “1” (= “H”), and the head block is selected as in the conventional case. It is initialized to the selected state of the last block, not the address initial value which is the state. Therefore, when the system management information or the like is stored in the head block of the cell array, unnecessary stress is applied to the storage area of the important system management information even when the EEPROM module is inserted or removed after power-on or forced reset. Can be prevented. Even if the tail block is stressed and the operating margin of the circuit is lowered, it is irrelevant to the management information of the chip and the reliability of the entire memory is prevented from being lowered.

In the above embodiment, at the time of forced reset,
An example is shown in which the last block of the plurality of blocks of the cell array is initialized to the selected state. However, assuming that the management information is stored in the first block, in order to prevent the stress of the first block, if the blocks other than the first block are initialized to a selected state, the same effect can be obtained. can get. Even more generally, by configuring the address signal transfer circuit so that even if the area for storing the management information is not the first block, it is initialized while avoiding the specific area in which the management information is stored. , The same effect can be expected.

In the above embodiment, the address initialization is performed so as to avoid the specific address of the cell array after power-on or reset, but even if the initialized address is not in the memory management area, it is always performed. If they are initialized to the same address, only the cell of that address is heavily loaded. Therefore, it is also preferable that the initialization address can be changed appropriately. Such an embodiment will be described below.

FIG. 6 shows an EEPRO according to this embodiment.
The configuration of M is shown in correspondence with FIG. The difference from FIG. 1 is that a reset address setting circuit 13 is added. The reset address setting circuit 51 is capable of setting a row address to be initialized for each power-on signal PWRON or reset signal RST.

With the addition of the reset address setting circuit 13, the configuration of the row address signal transfer circuit 82 in the address signal transfer circuit 8 is as shown in FIG. 7 in correspondence with FIG. Unlike FIG. 3, the latch circuit 40
Is configured by the anti-parallel connection of only the inverters 42 and 44, and outputs RSTAdd of the reset address setting circuit 13.
Of the latch circuit 40 via the clocked inverter 48.
Is transferred to the node N0. The clocked inverter 48 is controlled by the power-on signal PWRON and the reset signal RST.

As with the previous embodiment, the reset circuit 1
The reset signal RST, which is an output of 0, is "L" at reset, and the output reset signal PWRON of the power-on circuit 11 is "H" at power-on. The former is directly input to the NAND gate 46,
The latter is inverted by inverter 45 and enters NAND gate 46. The output of the NAND gate 46 is further passed through an inverter 47 to generate complementary reset enable signals RSTE, RSTEn, which controls the clocked inverter 48 and causes the output of the reset address setting circuit 13 to enter the node N0. It is like this.

FIG. 8 shows the operation timing of the row address transfer circuit 82 thus constructed. When the power is turned on and the power-on signal PWRON becomes “H” (time t0), the NAND gate 46 outputs RSTE =
It outputs "H" and RSTEN = "L". As a result, the clocked inverter 48 is turned on, the initialization row address RSTAdd1 set by the reset address setting circuit 13 is transferred to the node N0, and the latch circuit 4
It is held at 0. The initialization address RSTAdd1 held in the latch circuit 40 is transferred to the clocked inverter 43 that is on while the enable signal RAE is “L” and the transfer path 30 is off, and is output to the output node N2.

After that, the row address enable signal RA
When E becomes "H" (time t1), the input row address RAdd is transferred through the transfer path 30 instead of the initialization address held in the latch circuit 40, and is output to the output node N2.

Further, when the reset signal RST becomes "L" (time t2), the NAND gate 46 has RSTE =
It outputs "H" and RSTEN = "L". As a result, the clocked inverter 48 is turned on, and another initialization row address RSTAdd2 set by the reset address setting circuit 13 is transferred to the node N0 and held in the latch circuit 40. The initialization address RSTAdd1 held in the latch circuit 40 is transferred to the clocked inverter 43 that is on while the enable signal RAE is “L” and the transfer path 30 is off, and is output to the output node N2.

As described above, after power-on or reset, the reset address setting circuit 13 initializes the row address to an arbitrary row address set each time.
This prevents the situation where the same block is always initialized to the selected state, and the stress is distributed. Therefore, the probability of data destruction due to stress concentration decreases,
The reliability of the EEPROM can be improved. Of course, also in the case of this embodiment, it is preferable to prevent the initialization of the storage area of the management information and the like related to the operation of the entire chip.

Reset address (initialization address) RSTAAdd set by the reset address setting circuit 13
Can be supplied from the outside of the chip, or can be stored in the chip in advance and selected. A specific configuration example of the reset address setting circuit 13 is shown below.

FIG. 9 shows the I / O buffer 6 from outside the chip.
This is the configuration of the reset address setting circuit 13 when the reset address is input through the. A clocked inverter 101 controlled by complementary capture signals InE and InEn is provided at an input end, and a clocked inverter 104 and an inverter 10 are provided at an output end thereof.
5 is provided with the latch circuit 103. The clocked inverter 104 is the clocked inverter 10 of the input stage.
Similar to 1, it is controlled by the fetch signals InE and InEn. With such a configuration, it is possible to hold an arbitrary reset address RSTAdd input from the external I / O terminal and set the row address initial value after power-on or after reset.

On the other hand, FIG. 10 shows an example in which the reset address storage circuit 20 stores the reset address to be held in the reset address setting circuit 13 inside the chip. The reset address setting circuit 13 is shown in FIG.
Although it has an input stage clocked inverter 101 and a latch circuit 103 similar to, the reset address to be set is
It is stored and held in advance in the nonvolatile memory 202 for storing the reset address in the chip. And the read circuit 203
By this, it is read out and transferred and held in the latch circuit 103. This makes it possible to set the row address initial value after power-on or after reset.

Non-volatile memory 2 for storing reset address
Reference numeral 02 is electrically rewritable and may be a part of the cell array 1 shown in FIG. 1 or may be configured as another array. The non-volatile memory 202 can be appropriately written by the writing circuit 201. For example, each time a reset command is input, the reset address is changed and stored one by one within a certain range.
As a result, the stress can be reduced by switching the reset address as described above.

As a reset address setting method in the reset address setting circuit 13 shown in FIGS. 9 and 10, it is effective to select the start address of the unused area in the cell array 1. That is, when the blocks of the cell array 1 are sequentially used, they are initialized to the head address of the unused area at the time of reset. As a result, at the next chip enable, the start address of the unused area of the cell array is automatically selected. Further, if the reset address RSTAdd set in the reset address setting circuit 13 is configured to be monitored and output to the external terminal in this manner, the user can confirm the unused area of the chip, which is preferable.

[0044]

As described above, according to the present invention, it is possible to obtain a semiconductor memory device having an address signal transfer circuit for preventing unnecessary stress application to a specific data storage area.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an EEPROM according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of an address signal transfer circuit of the same embodiment.

FIG. 3 is a diagram showing a configuration of a row address signal transfer circuit in the address signal transfer circuit of FIG.

FIG. 4 is a timing chart for explaining the operation of the row address signal transfer circuit.

FIG. 5 is a diagram showing address allocation of a cell array block according to the same embodiment.

FIG. 6 is an EEPROM according to another embodiment of the present invention.
It is a figure which shows the structure of.

FIG. 7 is a diagram showing a configuration of a row address signal transfer circuit according to the same embodiment.

FIG. 8 is a timing chart for explaining the operation of the row address signal transfer circuit.

FIG. 9 is a diagram showing a configuration example of a reset address setting circuit of the same embodiment.

FIG. 10 is a diagram showing another configuration example of the reset address setting circuit of the same embodiment.

FIG. 11 is a diagram showing a configuration of a conventional address reset circuit.

[Explanation of symbols]

1 ... Memory cell array, 2 ... Sense amplifier, 3 ... Data register, 4 ... Column decoder, 5 ... Row decoder, 6
... I / O buffer, 7 ... Address register, 8 ... Address signal transfer circuit, 9 ... Control circuit, 10 ... Reset circuit,
11 ... Power-on circuit, 12 ... Chip address determination circuit, 13 ... Reset address setting circuit, 30 ... Transfer path, 40 ... Latch circuit (initialization circuit).

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Hiroshi Nakamura             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside (72) Inventor Yoshiyuki Tanaka             1st Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa             Ceremony Company Toshiba Microelectronics Sen             Inside F term (reference) 5B025 AD01 AE00

Claims (9)

[Claims] 1. A memory cell array, a decode circuit for selecting a memory cell of the memory cell array, a transfer path for transferring an address signal to the decode circuit, and an initialization circuit for initializing the transferred internal address signal. An address signal transfer circuit and a reset circuit that controls an initialization circuit of the address signal transfer circuit by a reset signal generated based on at least one of power-on detection and an external signal to initialize an internal address signal. The initialization circuit of the address signal transfer circuit is configured to initialize the internal address signal to a state in which a storage area other than a storage area to which an initial address value of the memory cell array is assigned is selected by the reset signal. A semiconductor memory device characterized by being provided. 2. The semiconductor memory device according to claim 1, wherein the memory area to which the initial address value is assigned is an area for storing memory management information. 3. The memory cell array is divided into a plurality of blocks selected by a row address signal, and
A first block of the plurality of blocks to which a row address initial value is assigned stores memory management information, and an initialization circuit of a portion of the address signal transfer circuit that transfers a row address signal is the reset circuit. 2. The semiconductor memory device according to claim 1, wherein the internal row address signal is initialized to a state in which a block other than the first block among the plurality of blocks is selected by a signal. 4. A memory cell array, a decode circuit for selecting a memory cell of the memory cell array, a transfer path for transferring an address signal to the decode circuit, and an initialization circuit for initializing the transferred internal address signal. An address signal transfer circuit, and a reset circuit that controls an initialization circuit of the address signal transfer circuit by a reset signal generated based on at least one of power-on detection and a signal from the outside to initialize an internal address signal, A reset address setting circuit for setting a reset address for initializing an internal address by the reset signal in the initialization circuit of the address signal transfer circuit;
A semiconductor memory device comprising: 5. The memory cell array is divided into a plurality of blocks selected by a row address signal, and the reset address setting circuit transfers a row address signal of the address signal transfer circuit by the reset signal. 5. The semiconductor memory device according to claim 4, wherein a row address for selecting a predetermined block is set as a reset address in the initialization circuit. 6. The semiconductor memory device according to claim 4, wherein the reset address setting circuit includes a latch circuit that holds a reset address supplied from outside the chip. 7. A chip has a reset address storage circuit for storing a reset address, and the reset address setting circuit has a latch circuit for holding a reset address read from the reset address storage circuit. The semiconductor memory device according to claim 4. 8. The semiconductor memory device according to claim 7, wherein the reset address memory circuit is an electrically rewritable nonvolatile memory. 9. The semiconductor memory device according to claim 1, wherein the memory cell array is configured by arranging electrically rewritable nonvolatile memory cells.