CN103150411A

CN103150411A - Universal embedded multi-path data collector and signal collection wave filtering method

Info

Publication number: CN103150411A
Application number: CN2013100720506A
Authority: CN
Inventors: 李艳辉; 赵辉; 刘斌; 周宾; 张莹; 李珊珊
Original assignee: Northeast Petroleum University
Current assignee: Northeast Petroleum University
Priority date: 2013-03-07
Filing date: 2013-03-07
Publication date: 2013-06-12
Anticipated expiration: 2033-03-07
Also published as: CN103150411B

Abstract

A universal embedded multi-path data collector is characterized by comprising a core plate and a functional expansion plate, wherein the core plate is provided with a processor, the processor is connected with a crystal oscillator circuit, a core plate power supply circuit, a reset circuit, a storage SDRAM unit, a FLASH storage unit and a JTAG debugging unit; the functional expansion plate is equipped with an A/D converter, an indicator circuit, a PLL (Phase Lock Loop) clock circuit, 4*1 keys, a GPRSDTU wireless module, a series interface circuit and a display plate connecting socket, which are respectively connected to the processor on the core plate through the core plate connecting socket. According to the invention, a wireless communication mode based on GPRSDTU and a wired communication mode based on interfaces of 232 and 485 can be flexibly connected, so that the adaptability is better, signals are collected by adopting an interference signal eliminating wave filtering method, so that the calculated average value is further approximate to a theoretical virtual value, and a more accurate data basis is provided for later monitoring control.

Description

Universal built-in type multiplex data acquisition unit and signal collection filtering method used

Technical field

The present invention relates to a kind of data acquisition equipment and method, particularly relate to a kind of universal built-in type multiplex data acquisition unit and signal collection filtering method used.

Background technology

Along with the development of social progress and science and technology, automatically be controlled in productive life and use more and more extensively, significantly improved efficiency and quality of the life, to develop contribution huge for its people.want to realize automatically to control to only have the collection of control object implementation data, thereby could grasp the object situation and implement appropriate Monitoring and Controlling, also different for the different object data acquisition means of different field, data acquisition machine in the market is various in style, but these data acquisition machines are mostly for a certain concrete work condition environment and specialized designs exploitation, the poor cost of development of versatility is high, construction cycle is long, the approach that adopts aspect the data transmission is also more single, wireless or wired, can't satisfy simultaneously the different condition environmental demand, as factory building, workshop and well site, open-air.also has the applied environment in the face of numerous and complicated, during data acquisition, analog signals inevitably can be subject to the impact of on-the-spot undesired signal in transport process before and after sensor, prior art is all generally to adopt digital filter to carry out filtering to reduce to disturb, in digital filtering algorithm, commonly used is the average value filtering algorithm, at first will be through N the digital signal summation M that obtains after the A/D conversion, then get the mean value Aver=M/N of this group data as the effective value of this sampled signal, when having the disturbing pulse signal to scurry into ALT-CH alternate channel, itself can not identify it the A/D test section, just disturbing pulse is shared as useful signal, cause the mean value that calculates and desirable effective value to produce certain error, in order to reduce to share the error that causes, what every group of data amount check N can be arranged is larger, make mean value keep a suitable flatness, but the N value increases the space that will take larger internal memory, also have influence on computing velocity, still await improving.

Summary of the invention

In order to solve the problem of the single and filtering deficiency of available data collector communication mode, the invention provides a kind of with type built-in type multiplex data acquisition unit and signal collection filtering method used.

The technical solution used in the present invention is: a kind of universal built-in type multiplex data acquisition unit is characterized in that comprising core board and expansion board; Core board is provided with processor, and processor is connected with crystal oscillating circuit, core board power circuit, reset circuit, internal memory SDRAM unit, FLASH storage unit, JTAG debugging unit; Expansion board is provided with A/D converter, indicating circuit, PLL PLL clock circuit, 4 * 1 buttons, GPRS DTU wireless module, serial interface circuit, display board gang socket, is connected with processor on core board by core board gang socket respectively; Processor is connected with GPRS DTU wireless module by serial interface UART 0, is connected with serial interface circuit by serial interface UART 1.

Described serial interface circuit is comprised of 485 data acquisition circuits that are connected with processor respectively, 232 data acquisition circuits and commutation circuit, and display board gang socket is connected with display module.

universal built-in type multiplex data acquisition unit signal collection filtering method used, at first will be through N the digital signal summation M that obtains after the A/D conversion, then get the mean value Aver=M/N of this group data as the effective value of this sampled signal, it is characterized in that at first arranging an error constraints value e and N value, be used for representing the maximum changing range of neighbouring sample value difference, then take successively several data, adopt to such an extent that data and adjacent front data compare calculating at every turn, with difference surpass adopting of e data are rejected, until adopt to such an extent that data reach N, again with N digital signal summation M, the effective value of Aver=M/N as this sampled signal of averaging at last.

Described data and adjacent front the data when comparing of at every turn adopting to get, continuous three differences surpass e, reject and adopt to get data and front data as a comparison for these three times, again adopt to get data data as a comparison.

Described sum formula be M=Samp 1+Samp 2+...+Samp N.

Described sum formula is for first asking m=aver*N, then asks M=m-aver+Samp i, i=2 in formula, 3 ... .N, aver is hypothesis mean value, m hypothesis and.

The present invention can adopt flexibly based on the communication of GPRS DTU with based on the wire communication mode of 232,485 serial ports, better adaptability, the filtering method that signals collecting adopts undesired signal to reject, make the mean value of calculating more near theoretical effective value, for the later stage Monitoring and Controlling provides data foundation more accurately.

Description of drawings

Fig. 1 to 5 is core board circuit theory diagrams of the present invention;

Fig. 6 to 8 is expansion board circuit theory diagrams of the present invention;

Fig. 9 is signals collecting filtering process flow diagram of the present invention.

Embodiment

Embodiment of the present invention circuit is as shown in Fig. 1 to 8, and this universal built-in type multiplex data acquisition unit is provided with core board and expansion board; Core board is provided with processor S3C44B0X, and processor is connected with crystal oscillating circuit, core board power circuit, reset circuit, internal memory SDRAM unit, FLASH storage unit, JTAG debugging unit; Expansion board is provided with A/D converter, indicating circuit, PLL PLL clock circuit, 4 * 1 buttons, GPRS DTU wireless module, serial interface circuit, display board gang socket, is connected with processor on core board by core board gang socket respectively.The core board power circuit is with ASM1117-3.3 and ASM1117-2.5 voltage transitions chip, and the power supply of standard 2.5V and 3.3V is provided for processor cores and input/output end port; The outside crystal oscillating circuit that connects of S3C44B0X is made of the 10M crystal oscillator, is up to 203MHz after inner PLL frequency multiplication, and in sheet, the PLL circuit has the function that signal amplifies and purifies concurrently simultaneously; Reset circuit with VCC+5V voltage produces reset signal nRESET voltage after through 74HC32 chip twice driving conversion, has the chip that resets and need, the threshold that resets to be elected to for system and be selected as 2.93V; The inner integrated JTAG debugging module of S3C4B0X, for software debugging brings convenience, avoided buying expensive emulator, the JTAG interface of standard is 4 lines: TMS, TCK, TDI, TDO, be respectively test pattern selection, test clock, test data input and test data output, sometimes for strengthening the software debugging dirigibility, can define reset signal nRST, the interface pin number that is used for the JTAG debugging on engineering mainly contains three kinds, 10 pins, 14 pins and 20 pins, the connected mode of every kind of plug-in unit is slightly different, and the present embodiment selects the plug-in unit of 14 pins; Used a slice SST39VF160 in the selection of Flash storer, this chip is the multi-functional Flash device of the CMOS of 16 Mbit2Mx8/1Mx16, indicate completing of programming operation by trigger bit or data query position, have hardware and software data protection mechanism; The SDRAM memory unit plays the effect of buffer memory in embedded system, can liken the internal memory in PC to, and the present embodiment has been selected a slice HY57641620; On core board, whole outer the diffusing on double contact pin of 44B0X pin, so just reduced the area of core board, and port OM1-OM3 and ENDIAN are connected respectively at the 51-55 pin of S3C44B0X, utilize to jump and emit and can run on greatly/the small end state by selection processor.The upper core board gang socket of expansion board is double slot, and core board is inserted in circuit top and on expansion board and is connected; The expansion board power supply obtains the 5V direct supply by J101, then is converted to 3.3V voltage through AMS1117-3.3; 4 independent buttons all are linked on the external interrupt I/O interface of 44B0X, can realize fast key response in programming procedure, be connected on respectively on GPG4, GPG5, GPG6, GPG7 pin, the corresponding port is low level when having button to press, otherwise is high level; Indicating circuit 74HC04 is six passage band buffer inverter, realizes that LED drives, and three light emitting diodes are controlled by GPC1, GPC2, GPC3 respectively, and high level is lighted, and low level is extinguished, and is used to refer to system running state; The PLL PLL clock circuit is comprised of 32768Hz crystal oscillating circuit and battery circuit, when system powers on, can automatically charge to battery, hardware supported to S3C44B0X inside RTC is provided, 32.768kHz the parallel resonance crystal oscillator be connected between XCLKI pin and XCLKO pin, play electric capacity with being connected respectively 22pF between ground, this crystal oscillator can make inner PLL phaselocked loop correctly lock and produce the clock frequency of 41.78MHz.processor is connected with GPRS DTU wireless module by serial interface UART 0, utilize public carrier network to provide wireless long distance transmit for the user, adopt high performance technical grade 8/16/32 bit walk processor and technical grade wireless module, take embedded real-time operating system as the software support platform, RS232 and RS485 interface are provided simultaneously, can directly connect serial equipment, realize the data transparent transmission function, the UART0 level shifting circuit directly is connected with GPRS DTU module gets final product, nCTS0, nRTS0, RXD0 and TXD0 are respectively at 101 of S3C44B0X, 102, 99 are connected with 100 pins, be connected to the wire communication mode by serial interface UART 1 and serial interface circuit, the present embodiment has adopted RS232 and two kinds of optional communication modes of RS485, can select the RS485 mode when long distance wired communication, RS232 is used for system testing and uses, emitted by jumping in the middle of two kinds of communication modes and select, MAX3232 consists of RS232 communication mode level shifting circuit, here nCTS1 and nRTS1 respectively at 105 of S3C44B0X, 106 pins are connected, MAX3485 consists of RS485 bus communication mode, this moment RE_485 and DE_485 respectively with the 60GPF1 of S3C44B0X, the 61GPF0 pin is connected, by switching the conversion that just can realize dual mode at 485-232 wire jumper translation interface JP17, if when selecting, 1 of JP17 is connected with 3 pin, 2 are connected with 4 pin just can be chosen as RS232 bus communication mode, if be connected with 4

3,4 are connected with 6 pin just can be chosen as the RS485 communication mode, and RXD1 is connected with 103,104 pins of S3C44B0X respectively with TXD1 here.Be connected with LCD liquid crystal display with touch screen function by display board gang socket, this display is the TFT screen of 260,000 looks, and pixel is 240 * 320.S3C44B0X provides 10 CMOS analog input channels of 8 tunnel for the user, maximum slew rate is 100ksps, require input voltage between 0-2.5V, the input signal bandwidth range is 0-100Hz, in design with the AIN0 external temperature sensor LM35 in 8 tunnel analog input channels, be used for the measurement of temperature, all the other AIN1-AIN7 interface circuits are following be used to connecing other data acquisition signals sources.

The software systems that good acquisition system also will have the performance that can make hardware processor to bring into play, embedded OS is this a kind of software.In the present embodiment, embedded OS μ C/OS-II is transplanted in S3C44B0X, dividing system task on the operating system aspect, call the related functions such as bottom driver in task, just can realize set function, simultaneously in order there to be one to observe intuitively the interface, again μ C/GUI is transplanted in system, by calling the api function of GUI, just can designs the interface environments that needs.After powering on, system at first system hardware equipment is carried out initialization, this initialization procedure comprises processor volume I/O is defined, serial ports initialization and selection, initialization is interrupted, initialization system clock and LCD initialization, be mainly the driver that has designed by calling in this course, complete the initialization of hardware resource, for ensuing call function is given security.The hardware resource initialization is complete, will carry out the initialization of operating system, calls the inside api function of μ C/OS-II, some data link tables that completion system can move, and various communication mechanisms and task management scheduling etc.Just can create initial task after completing top two ones.Create again other functional task functions in initial task.the task of dividing in an embodiment has key scan task KeyScan_Task, LCDs refreshes demonstration task LcdFresh_Task, serial ports receive data task UartRx_Task, serial ports sends data task UartTx_Task etc., realize the task intercommunication by statement semaphore and mailbox, when having button to press, the semaphore relevant to button is set to effective status, this moment, the keystroke handling task just brought into operation, the key scan task can be glimmered once by each official hour in normal operation, if system occurs abnormal, flicker will be interrupted.

Do not need human intervention after native system powers on, the man-machine conversation window by the GUI drafting will occur on the LCD touch-screen, this moment, the user can select according to the needs of oneself.The content of selecting is included in the adc data ALT-CH alternate channel mouth that in drop-down menu, selection need to be checked; Select wired or wireless mode in the communication mode choice menus, make software setting and wire jumper select the consistent of maintenance; Can trade-off curve and text mode after checking historical data.At last, complete above-mentioned the setting afterwards and just can enter normal working method.Data processing speed of the present invention is fast, on data mode, otherness according to environment for use, can select the wire communication mode based on RS485, realize and the data exchange of host computer, also can use the radio data communication mode based on GPRS DTU, applying flexible, at 8 road analog signals input ends, as long as just can change in 4-20mA or 0-2.5V scope from the signal of sensor acquisition, the large field of usable range is wide.

The present invention adopts distinctive signal collection filtering method used in addition, as shown in Figure 9, at first an error constraints value e and N value are set, be used for representing the maximum changing range of neighbouring sample value difference, then take successively several data, adopt to such an extent that data and adjacent front data compare calculating at every turn, calculate by following formula (1)

(1)

With difference surpass adopting of e data are rejected, until adopt to such an extent that data reach N, then with N digital signal summation M, by following formula (2) calculating,

M= Samp 1 + Samp 2 + ... + Samp N (2)

Formula (2) Samp 1, Samp 2 ... Samp N for effectively adopt data at last by following formula (3) computational data mean value,

Aver =M/N （3）

With the effective value of data mean value Aver as this sampled signal.This filtering method makes the mean value of calculating more near theoretical effective value, for the later stage Monitoring and Controlling provides data foundation more accurately.

The summation of this algorithm can also be adopted another kind of method, and hypothesis mean value aver, then calculate hypothesis and m in initialization N value and e value,

m=aver*N

M = m - aver + Samp i (4)

I=2 in formula (4), 3 ... .N, subsequently again according to formula (3) Aver=M/N computation of mean values, improve summation efficient.

This algorithm is asked and is adopted to get data and adjacent front data when comparing at every turn, and continuous three differences surpass e, reject and adopt to get data and front data as a comparison for these three times, again adopts to get data data as a comparison, prevents from that correlation data from makeing mistakes to cause erroneous judgement.

Claims

1. a universal built-in type multiplex data acquisition unit, is characterized in that comprising core board and expansion board; Core board is provided with processor, and processor is connected with crystal oscillating circuit, core board power circuit, reset circuit, internal memory SDRAM unit, FLASH storage unit, JTAG debugging unit; Expansion board is provided with A/D converter, indicating circuit, PLL PLL clock circuit, 4 * 1 buttons, GPRS DTU wireless module, serial interface circuit, display board gang socket, is connected with processor on core board by core board gang socket respectively; Processor is connected with GPRS DTU wireless module by serial interface UART 0, is connected with serial interface circuit by serial interface UART 1.

2. universal built-in type multiplex data acquisition unit according to claim 1, it is characterized in that described serial interface circuit is comprised of 485 data acquisition circuits that are connected with processor respectively, 232 data acquisition circuits and commutation circuit, display board gang socket is connected with display module.

3. universal built-in type multiplex data acquisition unit according to claim 1 and 2 is signal collection filtering method used, at first will be through N the digital signal summation M that obtains after the A/D conversion, then get the mean value Aver=M/N of this group data as the effective value of this sampled signal, it is characterized in that at first arranging an error constraints value e and N value, be used for representing the maximum changing range of neighbouring sample value difference, then take successively several data, adopt to such an extent that data and adjacent front data compare calculating at every turn, with difference surpass adopting of e data are rejected, until adopt to such an extent that data reach N, again with N digital signal summation M, the effective value of Aver=M/N as this sampled signal of averaging at last.

4. universal built-in type multiplex data acquisition unit according to claim 3 is signal collection filtering method used, it is characterized in that described data and adjacent front the data when comparing of at every turn adopting to get, continuous three differences surpass e, reject and adopt to get data and front data as a comparison for these three times, again adopt to get data data as a comparison.

5. universal built-in type multiplex data acquisition unit according to claim 3 is signal collection filtering method used, it is characterized in that described sum formula be M=Samp 1+Samp 2+...+Samp N.

6. universal built-in type multiplex data acquisition unit according to claim 3 is signal collection filtering method used, it is characterized in that described sum formula for first asking, then asks m=aver*N, M=m-aver+Samp i, i=2 in formula, 3 ... .N, aver is hypothesis mean value, m hypothesis and.