JP2009295886A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2009295886A
JP2009295886A JP2008149775A JP2008149775A JP2009295886A JP 2009295886 A JP2009295886 A JP 2009295886A JP 2008149775 A JP2008149775 A JP 2008149775A JP 2008149775 A JP2008149775 A JP 2008149775A JP 2009295886 A JP2009295886 A JP 2009295886A
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lead
region
semiconductor element
electrode
strap member
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Tomohiro Iguchi
知洋 井口
Hideo Nishiuchi
秀夫 西内
Tomoyuki Kitani
智之 木谷
Takahiro Aizawa
隆博 相澤
Hiroshi Tojo
啓 東條
Masako Oishi
昌子 大石
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Toshiba Corp
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Toshiba Corp
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    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/4005—Shape
    • H01L2224/4009—Loop shape
    • H01L2224/40091—Arched
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    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
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    • H01L2224/401—Disposition
    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device using a strap member, which can improve productivity and production efficiency while more reducing resistance of internal resistance, and to provide a manufacturing method of the semiconductor device. <P>SOLUTION: The semiconductor device is equipped with: a semiconductor element 2; a lead 3 having an electrode to be connected to an electrode provided in the semiconductor element 2; metal wire W which electrically connects the electrode of the semiconductor element 2 with the electrode of the lead 3, and an area except an area joined to the semiconductor element 2 and an area joined to the lead 3 of the metal wire W is formed thinner than the area joined to the semiconductor element 2 and the area joined to the lead 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体素子の電極と接続されることにより内部抵抗を低減するストラップ部材が設けられた半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device provided with a strap member that reduces internal resistance by being connected to an electrode of a semiconductor element, and a manufacturing method thereof.

半導体装置の一例として、電流のスイッチングや増幅に使用されるＦＥＴを含むトランジスタパッケージを挙げることができる。このトランジスタパッケージにおいて、半導体素子上の電極とリードの電極とは、金（Ａｕ）やアルミニウム（Ａｌ）等の導電性を有する金属から形成された複数本のワイヤによって電気的に接続されている。   As an example of the semiconductor device, a transistor package including an FET used for current switching and amplification can be given. In this transistor package, the electrode on the semiconductor element and the lead electrode are electrically connected by a plurality of wires formed of a conductive metal such as gold (Au) or aluminum (Al).

近年の半導体市場では、高速に動作し高い処理能力を有しつつ、動作中の消費電力は低い半導体装置が求められている。例えば携帯電話やノートパソコン等に使用される場合等はバッテリー駆動されることが多いが、その内部に使用される電子部品の抵抗値が高いと消費電力が多くなりバッテリーの駆動時間が短くなる。このような相反する２つの課題を克服するために、半導体装置の回路の微細化が進められるとともに、供給された電力を半導体装置全体で効率よく利用するために、内部抵抗（ＯＮ抵抗）の低抵抗化が進められている。   In the semiconductor market in recent years, there is a demand for a semiconductor device that operates at high speed and has high processing capability and low power consumption during operation. For example, when it is used in a mobile phone, a notebook computer, etc., it is often driven by a battery. However, if the resistance value of an electronic component used therein is high, the power consumption increases and the driving time of the battery is shortened. In order to overcome these two conflicting problems, the miniaturization of the circuit of the semiconductor device is promoted, and in order to efficiently use the supplied power throughout the semiconductor device, the internal resistance (ON resistance) is reduced. Resistance is being promoted.

この内部抵抗の例としては、電流経路部材として用いられる金属ワイヤを挙げることができるが、この金属ワイヤの抵抗が半導体装置全体の内部抵抗値に対して無視できない程に大きくなることもある。   An example of the internal resistance is a metal wire used as a current path member, but the resistance of the metal wire may be so large that it cannot be ignored with respect to the internal resistance value of the entire semiconductor device.

このような問題を解決するための１つの方法として、以下の特許文献１には、半導体装置全体の低抵抗化を図るため、導電性を有する平板状の金属材料を用いて半導体素子の電極とリードの電極とを電気的に接続する半導体装置が提示されている。すなわち、この方法により半導体素子の電極とリードの電極との間の電流の流路断面積が拡大されるので、電極とリードとの間における抵抗を下げることができるとされる。
特許第３２４０２９２号公報 As one method for solving such a problem, in Patent Document 1 below, in order to reduce the resistance of the entire semiconductor device, an electrode of a semiconductor element is formed using a conductive flat metal material. A semiconductor device that electrically connects an electrode of a lead has been proposed. In other words, this method increases the cross-sectional area of the current flow path between the electrode of the semiconductor element and the electrode of the lead, so that the resistance between the electrode and the lead can be reduced.
Japanese Patent No. 3340292

しかしながら、上述した特許文献１に記載されている平板状の金属材料（以下、このような半導体素子の電極とリードの電極との間の電流の流路断面積を拡大する導体を「ストラップ部材」と呼ぶ）は、例えば、縦５００μｍ、横１．２ｍｍ、厚さ１００μｍといった大きさであり、非常に微細である。このストラップ部材は通常打ち抜いて形成するが、微細であるが故に打ち抜く際に歪みが発生してしまう可能性があった。   However, the flat metal material described in Patent Document 1 (hereinafter referred to as a “strap member” is a conductor that expands the cross-sectional area of the current flow path between the electrode of the semiconductor element and the electrode of the lead. For example) are 500 μm in length, 1.2 mm in width, and 100 μm in thickness, and are very fine. This strap member is usually formed by punching. However, since the strap member is fine, there is a possibility that distortion occurs when punching.

また、打ち抜く対象となる金属、例えばアルミは巻き取られてリボン状になっており、打ち抜く際にはこのリボンからアルミを引き出しながら打ち抜く。リボンを引き出す際に例えば振動が発生すると、リボン上においてストラップ部材を打ち抜く位置にズレが生じ誤差が発生する。この誤差はストラップ部材の大きさからすれば非常に大きなものとなってしまうため、高い生産性を維持するためには精度良く打ち抜くことが求められる。   Further, a metal to be punched, for example, aluminum is wound up into a ribbon shape, and when punching, the aluminum is pulled out from the ribbon while being pulled out. If, for example, vibration occurs when the ribbon is pulled out, a deviation occurs at a position where the strap member is punched on the ribbon, and an error occurs. Since this error is very large considering the size of the strap member, it is required to punch with high accuracy in order to maintain high productivity.

本発明は上記課題を解決するためになされたものであり、本発明の目的は、内部抵抗の一層の低抵抗化を図りつつ生産性及び生産効率の向上をも可能とするストラップ部材を使用した半導体装置及びこの半導体装置の製造方法を提供することである。   The present invention has been made to solve the above-described problems, and an object of the present invention is to use a strap member that can improve productivity and production efficiency while further reducing internal resistance. A semiconductor device and a method for manufacturing the semiconductor device are provided.

本発明の実施の形態に係る第１の特徴は、半導体装置において、半導体素子と、半導体素子に設けられた電極と接続される電極を有するリードと、半導体素子の電極とリードの電極とを電気的に接続する金属ワイヤと、を具備し、金属ワイヤのうち、半導体素子と接合されている領域及びリードと接合されている領域を除く領域が、半導体素子と接合されている領域及びリードと接合されている領域よりも薄く成形されている。   A first feature of the embodiment of the present invention is that in a semiconductor device, a semiconductor element, a lead having an electrode connected to an electrode provided in the semiconductor element, an electrode of the semiconductor element, and an electrode of the lead are electrically connected. A region of the metal wire excluding the region bonded to the semiconductor element and the region bonded to the lead, the region bonded to the semiconductor element and the lead It is molded thinner than the area where it is.

本発明の実施の形態に係る第２の特徴は、半導体装置の製造方法において、半導体素子に設けられた第１の電極と第１のリードに設けられた電極とを接続する工程と、半導体素子に設けられた第２の電極と第２のリードに設けられた電極とを接続するストラップ部材を成形する工程と、ストラップ部材を用いて半導体素子の第２の電極と第２のリードに設けられた電極との間を電気的に接続する工程とを備える。   According to a second aspect of the present invention, in the method for manufacturing a semiconductor device, the step of connecting the first electrode provided in the semiconductor element and the electrode provided in the first lead, and the semiconductor element Forming a strap member that connects the second electrode provided on the second electrode and the electrode provided on the second lead; and using the strap member to provide the second electrode and the second lead of the semiconductor element. Electrically connecting the electrodes to each other.

本発明によれば、内部抵抗の一層の低抵抗化を図りつつ生産性及び生産効率の向上をも可能とするストラップ部材を使用した半導体装置及びこの半導体装置の製造方法を提供することができる。   According to the present invention, it is possible to provide a semiconductor device using a strap member that can improve productivity and production efficiency while further reducing internal resistance, and a method for manufacturing the semiconductor device.

以下、本発明の実施の形態について図面を参照して詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

図１は、本発明の実施の形態における半導体装置の平面を簡易に表わした平面図である。半導体装置Ａは、第１のリード１と、半導体素子２と、第２のリード３と、第３のリード４と、半導体素子２と第２のリード３とを電気的に接続するストラップ部材５と、半導体素子２と第３のリード４とを電気的に接続する金属ワイヤ６とから構成される。また、第１のリード１と、半導体素子２と、第２のリード３と、第３のリード４と、ストラップ部材５と、金属ワイヤ６とは、基板７上に載置されている。なお、後述するようにストラップ部材５は金属ワイヤＷを加工することによって製造されるため、加工前の金属ワイヤＷと加工後のストラップ部材５は同一物である。従って、以下、説明によって適宜、「金属ワイヤＷ」と表わしたり「ストラップ部材５」と表わしたりする。   FIG. 1 is a plan view simply showing a plane of a semiconductor device according to an embodiment of the present invention. The semiconductor device A includes a first lead 1, a semiconductor element 2, a second lead 3, a third lead 4, and a strap member 5 that electrically connects the semiconductor element 2 and the second lead 3. And a metal wire 6 that electrically connects the semiconductor element 2 and the third lead 4. The first lead 1, the semiconductor element 2, the second lead 3, the third lead 4, the strap member 5, and the metal wire 6 are placed on the substrate 7. As will be described later, since the strap member 5 is manufactured by processing the metal wire W, the metal wire W before processing and the strap member 5 after processing are the same. Therefore, in the following description, it is expressed as “metal wire W” or “strap member 5” as appropriate.

図１に示される半導体素子２には、図示しないドレイン電極Ｄ、ソース電極Ｓ及びゲート電極Ｇの各電極が設けられている。第１のリード１は、図示しない第１のリード電極を備え、半導体素子２のドレイン電極Ｄとダイボンド材を介して電気的に接続される。第２のリード３は、図示しない第２のリード電極を備え、半導体素子２のソース電極Ｓとストラップ部材５を介して電気的に接続される。さらに、第３のリード４は、図示しない第３のリード電極を備え、半導体素子２のゲート電極Ｇと金属ワイヤ６を介して電気的に接続される。この第３のリード４、金属ワイヤ６を介してゲート電極Ｇに電圧が印加されると、ソース電極Ｓとドレイン電極Ｄとの間で電流が流れる。   The semiconductor element 2 shown in FIG. 1 is provided with drain electrode D, source electrode S, and gate electrode G (not shown). The first lead 1 includes a first lead electrode (not shown), and is electrically connected to the drain electrode D of the semiconductor element 2 via a die bond material. The second lead 3 includes a second lead electrode (not shown) and is electrically connected to the source electrode S of the semiconductor element 2 via the strap member 5. Further, the third lead 4 includes a third lead electrode (not shown), and is electrically connected to the gate electrode G of the semiconductor element 2 via the metal wire 6. When a voltage is applied to the gate electrode G via the third lead 4 and the metal wire 6, a current flows between the source electrode S and the drain electrode D.

図２は、図１におけるＸ−Ｘ線で切断した様子を示す断面図である。ストラップ部材５は、その端部領域Ｍ１，Ｍ２において半導体素子２のソース電極Ｓ及び第２のリード３に設けられている第２のリード電極に対して例えば、超音波振動を印加しつつ圧着される。すなわち、ストラップ部材５のうち半導体素子２と接合されている領域を示すのがＭ１の領域であり、リード３と接合されている領域を示すのがＭ２の領域である。   FIG. 2 is a cross-sectional view showing a state cut along line XX in FIG. The strap member 5 is crimped to the source electrode S of the semiconductor element 2 and the second lead electrode provided on the second lead 3 in the end regions M1 and M2, for example, while applying ultrasonic vibration. The That is, the region of the strap member 5 that is bonded to the semiconductor element 2 is the region M1, and the region that is bonded to the lead 3 is the region M2.

また、図１に示す平面図では平面に見えるが、その断面を見ると、段差のある半導体素子２のソース電極Ｓ及び第２のリード３に設けられている第２のリード電極とを接触することなく接続させるために、ストラップ部材５の端部領域Ｍ１，Ｍ２に挟まれる領域（以下、「領域Ｎ」という。）は薄く湾曲するように形成されている。   Moreover, although it looks like a plane in the plan view shown in FIG. 1, when the cross section is viewed, the source electrode S of the semiconductor element 2 having a step and the second lead electrode provided on the second lead 3 are in contact with each other. In order to make a connection without any problem, a region between the end regions M1 and M2 of the strap member 5 (hereinafter referred to as “region N”) is formed to be thinly curved.

図３ないし図７は、ストラップ部材５の製造工程を示す図面である。本発明の実施の形態におけるストラップ部材５は、金属ワイヤを利用して製造される。すなわち、長い金属ワイヤを所定の長さに切り出して加工して所望のストラップ部材５を製造する。   3 to 7 are drawings showing the manufacturing process of the strap member 5. The strap member 5 in the embodiment of the present invention is manufactured using a metal wire. That is, a desired metal strap member 5 is manufactured by cutting and processing a long metal wire into a predetermined length.

図３は切り出された金属ワイヤＷを正面から見た図である。円柱形状の金属ワイヤを切り出しているので、正面から見ると長方形に見える。なお、金属ワイヤＷは、ゲート電極Ｇと第３のリード４とをつなぐ金属ワイヤ６よりも太い金属ワイヤである。   FIG. 3 is a view of the cut metal wire W as seen from the front. Since the cylindrical metal wire is cut out, it looks rectangular when viewed from the front. The metal wire W is a metal wire that is thicker than the metal wire 6 that connects the gate electrode G and the third lead 4.

図４及び図５は、図３に示す切り出した金属ワイヤＷを加工した状態を示す正面図（図４）と平面図（図５）である。切り出された金属ワイヤＷは図４において図示しない治具を用いてその領域Ｎを押しつぶすとともに湾曲させる。領域Ｎを押しつぶして図５の平面図に示すように薄い平板状に加工するのは、電流の流路断面積を拡大してその抵抗を低くするためである。   4 and 5 are a front view (FIG. 4) and a plan view (FIG. 5) showing a state in which the cut-out metal wire W shown in FIG. 3 is processed. The cut-out metal wire W is crushed and bent by using a jig not shown in FIG. The reason why the region N is crushed and processed into a thin flat plate as shown in the plan view of FIG. 5 is to increase the cross-sectional area of the current flow path and reduce its resistance.

端部領域Ｍ１，Ｍ２はそれぞれ半導体素子２のソース電極Ｓの領域と第２のリード電極の領域に、例えば超音波振動を印加しつつ圧着することになるため、接続が終了したときに端部領域Ｍ１，Ｍ２の断面は概ね平板状になる。一方、この領域Ｎの部分は半導体素子２と第２のリードとを跨ぐ部分であるため、図４に示す矢印方向からの圧力を掛けることができない。そのため、端部領域Ｍ１，Ｍ２のように圧力を掛けて押しつぶすことで概ね平板状に加工することができないため、金属ワイヤＷの端部領域Ｍ１，Ｍ２よりも先に領域Ｎを平板状に加工するものである。   The end regions M1 and M2 are, for example, crimped to the source electrode S region and the second lead electrode region of the semiconductor element 2 while applying ultrasonic vibration, for example. The cross sections of the regions M1 and M2 are substantially flat. On the other hand, since the region N is a portion straddling the semiconductor element 2 and the second lead, it is impossible to apply pressure from the direction of the arrow shown in FIG. Therefore, since it cannot be processed into a generally flat plate shape by applying pressure and crushing like the end regions M1 and M2, the region N is processed into a flat plate shape before the end regions M1 and M2 of the metal wire W. To do.

このように加工されると、図５の平面図にも表わされるように、治具によって押しつぶされた金属ワイヤＷの該当領域（領域Ｎ）は押しつぶされていない端部領域Ｍ１，Ｍ２よりも薄く幅が広くなる。   When processed in this way, as shown in the plan view of FIG. 5, the corresponding region (region N) of the metal wire W crushed by the jig is thinner than the end regions M1 and M2 that are not crushed. The width becomes wider.

さらに、ストラップ部材５の領域Ｎについては湾曲するように加工がなされる。図４に示すように、領域Ｎはアーチ状に湾曲している。これは、端部領域Ｍ１が接続される半導体素子２と端部領域Ｍ２が接続される第２のリード３の基板７からの高さが相違するため、領域Ｎを直線上に成形すると半導体素子２にストラップ部材５が接触することになる。この状態を避けるために、領域Ｎは端部領域Ｍ１側で一旦上方に上がり湾曲して端部領域Ｍ２に向けてなだらかにつながる。   Further, the region N of the strap member 5 is processed to be curved. As shown in FIG. 4, the region N is curved in an arch shape. This is because the semiconductor element 2 to which the end region M1 is connected and the height of the second lead 3 to which the end region M2 is connected from the substrate 7 are different from each other. 2 is brought into contact with the strap member 5. In order to avoid this state, the region N once rises upward on the end region M1 side and curves to be gently connected toward the end region M2.

なお、金属ワイヤＷのどの領域を端部領域Ｍ１，Ｍ２とし、領域Ｎとするかは半導体装置Ａ内の半導体素子２と第２のリード３との位置関係によって自由に設定することが可能である。   Note that which region of the metal wire W is the end region M1, M2 and the region N can be freely set depending on the positional relationship between the semiconductor element 2 and the second lead 3 in the semiconductor device A. is there.

図６は、これまで説明してきたストラップ部材５を表わす斜視図である。この斜視図において明らかなように、手前側の端部領域Ｍ１は半導体素子２と接続される領域であり、領域Ｎを挟んで奥側の端部領域Ｍ２は第２のリード３と接続される領域である。領域Ｎはそれぞれ接続される半導体素子２と第２のリード３との高さの違いに合わせて、一旦盛り上がってから手前側の端部領域Ｍ１から奥側の端部領域Ｍ２へ向けて低くなるように湾曲する。   FIG. 6 is a perspective view showing the strap member 5 described so far. As is clear from this perspective view, the end region M1 on the near side is a region connected to the semiconductor element 2, and the end region M2 on the back side across the region N is connected to the second lead 3. It is an area. In accordance with the difference in height between the semiconductor element 2 and the second lead 3 connected to each other, the region N rises once and then decreases from the front end region M1 toward the back end region M2. To bend.

なお、領域Ｎについては治具を用いて上下から金属ワイヤＷを挟み込み押しつぶすことで平板状へと加工される。本発明の実施の形態においては、金属ワイヤＷを挟み込む下側の治具を固定し上側の治具のみを動かして加圧している。そのため、図４や図６に示されるように、領域Ｎは端部領域Ｍ１の下端部と端部領域Ｍ２の下端部とをつなぐように形成される。   The region N is processed into a flat plate shape by sandwiching and crushing the metal wire W from above and below using a jig. In the embodiment of the present invention, the lower jig sandwiching the metal wire W is fixed, and only the upper jig is moved and pressurized. Therefore, as shown in FIGS. 4 and 6, the region N is formed so as to connect the lower end of the end region M1 and the lower end of the end region M2.

一方で、上下の治具を用いて金属ワイヤＷに上下から同じ圧力を掛けて加圧し押しつぶすと領域Ｎは端部領域Ｍ１の中央部と端部領域Ｍ２の中央部とをつなぐように形成され、上側の治具を固定し下側の治具のみを動かして金属ワイヤＷに加圧すると領域Ｎは端部領域Ｍ１の上端部と端部領域Ｍ２の上端部とをつなぐように平板状に形成される。いずれの加工方法を採用して金属ワイヤＷの断面のどの位置に領域Ｎを形成するかは任意である。   On the other hand, when the same pressure is applied to the metal wire W from above and below using the upper and lower jigs and pressed and crushed, the region N is formed so as to connect the center of the end region M1 and the center of the end region M2. When the upper jig is fixed and only the lower jig is moved to pressurize the metal wire W, the region N has a flat plate shape so as to connect the upper end of the end region M1 and the upper end of the end region M2. It is formed. Which processing method is employed to form the region N in the cross section of the metal wire W is arbitrary.

このようにして成形されたストラップ部材５は、接続される半導体素子２と第２のリード３の該当領域上に載置され、図７に示すような治具８を用いて圧着させる。治具８を用いての圧着に際しては、例えば超音波振動を印加しても良い。   The strap member 5 thus molded is placed on the corresponding region of the semiconductor element 2 and the second lead 3 to be connected, and is crimped using a jig 8 as shown in FIG. At the time of pressure bonding using the jig 8, for example, ultrasonic vibration may be applied.

治具８がストラップ部材５の端部領域Ｍ１，Ｍ２の領域に対して加圧することによって金属ワイヤＷが次第に押しつぶされて、最終的に図２に示すような厚さになる。すなわち、切り出された金属ワイヤＷに領域Ｎが加工されたときから半導体素子２及びリード３への接合終了後に至るまで、領域Ｎの方が端部領域Ｍ１，Ｍ２よりも薄く成形されていることになる。なお、治具８には、加圧する際に湾曲して成形されている領域Ｎをつぶすことのないようにくぼみ８ａが設けられている。   When the jig 8 presses against the end regions M1 and M2 of the strap member 5, the metal wire W is gradually crushed and finally has a thickness as shown in FIG. That is, the region N is formed thinner than the end regions M1 and M2 from the time when the region N is processed to the cut metal wire W until the end of the bonding to the semiconductor element 2 and the lead 3. become. Note that the jig 8 is provided with a recess 8a so as not to crush the region N which is curved and molded when pressed.

このように、ストラップ部材をアルミのリボンから打ち抜くのではなく金属ワイヤＷを加工して製造することによって、微細なストラップ部材を精度良く加工することできるとともに、内部抵抗の一層の低抵抗化を図りつつ生産性及び生産効率の向上をも可能とするストラップ部材を使用した半導体装置及びこの半導体装置の製造方法を提供することができる。   As described above, by manufacturing the metal wire W instead of punching the strap member from the aluminum ribbon, the fine strap member can be processed with high accuracy and the internal resistance can be further reduced. In addition, it is possible to provide a semiconductor device using a strap member that can improve productivity and production efficiency and a method for manufacturing the semiconductor device.

なお、この発明は、上記実施の形態そのままに限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で構成要素を変形して具体化できる。また、上記実施の形態に開示されている複数の構成要素を適宜組み合わせることにより種々の発明を形成できる。例えば、実施の形態に示される全構成要素から幾つかの構成要素を削除してもよい。更に、異なる実施の形態に亘る構成要素を適宜組み合わせても良い。   Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

本発明の実施の形態における半導体装置の平面を簡易に表わした平面図である。It is a top view which represented the plane of the semiconductor device in an embodiment of the invention simply. 図１におけるＸ−Ｘ線で切断した様子を示す断面図である。It is sectional drawing which shows a mode that it cut | disconnected by the XX line in FIG. ストラップ部材の製造工程を示す図面である。It is drawing which shows the manufacturing process of a strap member. ストラップ部材の製造工程を示す図面であり、ストラップ部材の正面図である。It is drawing which shows the manufacturing process of a strap member, and is a front view of a strap member. ストラップ部材の製造工程を示す図面であり、ストラップ部材の平面図である。It is drawing which shows the manufacturing process of a strap member, and is a top view of a strap member. ストラップ部材の製造工程を示す図面であり、ストラップ部材の斜視図である。It is drawing which shows the manufacturing process of a strap member, and is a perspective view of a strap member. ストラップ部材の製造工程を示す図面である。It is drawing which shows the manufacturing process of a strap member.

符号の説明Explanation of symbols

１…第１のリード、２…半導体素子、３…第２のリード、４…第３のリード、５…ストラップ部材、６…金属ワイヤ、７…基板、８…治具、Ａ…半導体装置、Ｍ…端部領域、Ｎ…領域。 DESCRIPTION OF SYMBOLS 1 ... 1st lead, 2 ... Semiconductor element, 3 ... 2nd lead, 4 ... 3rd lead, 5 ... Strap member, 6 ... Metal wire, 7 ... Board | substrate, 8 ... Jig, A ... Semiconductor device, M ... end region, N ... region.

Claims (5)

半導体素子と、
前記半導体素子に設けられた電極と接続される電極を有するリードと、
前記半導体素子の電極と前記リードの電極とを電気的に接続する金属ワイヤと、を具備し、
前記金属ワイヤのうち、前記半導体素子と接合されている領域及び前記リードと接合されている領域を除く領域が、前記半導体素子と接合されている領域及び前記リードと接合されている領域よりも薄く成形されていることを特徴とする半導体装置。 A semiconductor element;
A lead having an electrode connected to an electrode provided in the semiconductor element;
A metal wire that electrically connects the electrode of the semiconductor element and the electrode of the lead,
Of the metal wire, a region excluding a region bonded to the semiconductor element and a region bonded to the lead is thinner than a region bonded to the semiconductor element and a region bonded to the lead. A semiconductor device which is molded. 前記金属ワイヤは、前記金属ワイヤの端部領域を円柱形状とし前記端部領域に挟まれた領域を湾曲した板状に成形されていることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein the metal wire is formed in a plate shape in which an end region of the metal wire is cylindrical and a region sandwiched between the end regions is curved. 半導体素子に設けられた第１の電極と第１のリードに設けられた電極とを接続する工程と、
前記半導体素子に設けられた第２の電極と第２のリードに設けられた電極とを接続するストラップ部材を成形する工程と、
前記ストラップ部材を用いて前記半導体素子の第２の電極と前記第２のリードに設けられた電極との間を電気的に接続する工程と、
を備えることを特徴とする半導体装置の製造方法。 Connecting the first electrode provided in the semiconductor element and the electrode provided in the first lead;
Forming a strap member for connecting the second electrode provided on the semiconductor element and the electrode provided on the second lead;
Electrically connecting the second electrode of the semiconductor element and the electrode provided on the second lead using the strap member;
A method for manufacturing a semiconductor device, comprising: 前記ストラップ部材を成形する工程は、金属ワイヤの端部領域の形状はそのままに前記端部領域に挟まれた領域を板状に成形するとともに、前記挟まれた領域を湾曲させる工程であることを特徴とする請求項３に記載の半導体装置の製造方法。 The step of forming the strap member is a step of forming a region sandwiched between the end regions without changing the shape of the end region of the metal wire into a plate shape and curving the sandwiched region. The method for manufacturing a semiconductor device according to claim 3, wherein: 前記ストラップ部材を接続する工程は、前記ストラップ部材の端部領域を加圧して変形させつつ前記前記半導体素子の第２の電極と前記第２のリードに設けられた電極とに接続することを特徴とする請求項３または請求項４に記載の半導体装置の製造方法。 The step of connecting the strap member connects to the second electrode of the semiconductor element and the electrode provided on the second lead while pressing and deforming the end region of the strap member. A method for manufacturing a semiconductor device according to claim 3 or 4.
JP2008149775A 2008-06-06 2008-06-06 Semiconductor device and manufacturing method thereof Pending JP2009295886A (en)

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JP2013235882A (en) * 2012-05-07 2013-11-21 Mitsubishi Electric Corp Semiconductor device
EP3244448A1 (en) * 2016-05-09 2017-11-15 Heraeus Deutschland GmbH & Co. KG Connector, method for manufacturing a connector, power semiconductor module and method of manufacturing a power semiconductor module

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JP2003303845A (en) * 2002-04-10 2003-10-24 Fuji Electric Co Ltd Semiconductor device and wire bonding method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003303845A (en) * 2002-04-10 2003-10-24 Fuji Electric Co Ltd Semiconductor device and wire bonding method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013235882A (en) * 2012-05-07 2013-11-21 Mitsubishi Electric Corp Semiconductor device
EP3244448A1 (en) * 2016-05-09 2017-11-15 Heraeus Deutschland GmbH & Co. KG Connector, method for manufacturing a connector, power semiconductor module and method of manufacturing a power semiconductor module

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