JP2006203039A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
JP2006203039A
JP2006203039A JP2005014018A JP2005014018A JP2006203039A JP 2006203039 A JP2006203039 A JP 2006203039A JP 2005014018 A JP2005014018 A JP 2005014018A JP 2005014018 A JP2005014018 A JP 2005014018A JP 2006203039 A JP2006203039 A JP 2006203039A
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semiconductor device
lead
leads
main
resin package
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JP4849802B2 (en
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Satoru Utsunomiya
哲 宇都宮
Yoshihiro Takano
好弘 高野
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device for forming a compact MOSFET having low ON resistance also when it is used for a large chip. <P>SOLUTION: The semiconductor device includes a resin package 10; at least two main leads 2a, 2b, 2c for composing an integrated chip mounting section 2d inside the resin package 10; a semiconductor chip 6 mounted to the chip mounting section 2d; and first and second surface leads 3a, 3b connected to each electrode on the surface of the semiconductor chip. The main leads 2a, 2b, 2c and the first and second surface leads 3a, 3B are extended straight on the same surface as the bottom surface of the resin package 10. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、半導体装置にかかり、特にスイッチング用ＭＯＳＦＥＴ等の実装に用いられる半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device used for mounting a switching MOSFET or the like.

近年、パーソナルコンピュータ、携帯電話に代表される電子機器の小型化に伴う電子部品の高密度実装化が進んでおり、それに伴いダイオード、トランジスタなどの半導体装置においては、実装面積を縮小するため、種々の工夫が重ねられている。なかでも、電池などの電源からのスイッチングに用いるロードスイッチとして用いられるスイッチング用ＭＯＳＦＥＴは、実装面積の縮小を達成するための小型化、薄型化への要求に加え、オン抵抗の低減という大きな要求がある。   In recent years, electronic components, such as personal computers and mobile phones, have been increasingly mounted with high-density mounting due to miniaturization of electronic devices. In connection with semiconductor devices such as diodes and transistors, various mounting methods have been used to reduce the mounting area. Have been repeated. In particular, a switching MOSFET used as a load switch used for switching from a power source such as a battery has a large demand for a reduction in on-resistance in addition to a demand for downsizing and thinning to achieve a reduction in mounting area. is there.

そこで、実装面積の縮小のために、面実装型半導体装置が提案されている。このような面実装タイプの半導体装置においては、製造コスト低減のために、材料が安く、生産性の良好な樹脂封止型半導体装置が広く使用されている。   Thus, surface mount semiconductor devices have been proposed to reduce the mounting area. In such surface mounting type semiconductor devices, resin-encapsulated semiconductor devices with low material and good productivity are widely used to reduce manufacturing costs.

樹脂封止型半導体装置においては、電子装置を小型化していくと、外部導出リードの封止樹脂底面付近の折り曲げ部の微妙な折り曲げ形状により、封止樹脂の回り込み、リード自体の強度、リードと封止樹脂との付着強度および実装用半田の付着回り込みにより不良を生じ易いという問題があった。   In the resin-encapsulated semiconductor device, when the electronic device is reduced in size, the encapsulating resin wraps around the bottom of the sealing resin bottom surface of the lead-out lead, the strength of the lead itself, There was a problem that defects were likely to occur due to adhesion strength with the sealing resin and adhesion of the mounting solder.

そこで、本発明者らは、半導体装置の小型化においても、外部リードの封止樹脂底面付近の折り曲げ部への封止樹脂の周り込みや、リードと封止樹脂との付着強度が良好で、リード自体の強度を十分に高く維持することのできる半導体装置を提案している（特許文献１）。   Therefore, the present inventors have good sealing resin wrap around the bent portion near the bottom surface of the sealing resin of the external lead and the adhesion strength between the lead and the sealing resin even in the miniaturization of the semiconductor device, A semiconductor device has been proposed that can maintain the strength of the lead itself sufficiently high (Patent Document 1).

この半導体装置では、素子載置部を備えた第１外部導出リードと、素子載置部と離間して配置された第２外部導出リードとを備え、これらの一部を樹脂封止してなり、第１外部導出リードをＳ字形に折り曲げると共に折り曲げ深さｄが第１外部導出リードの厚さｔ以上であり、かつ素子載置部の裏面側の封止樹脂の厚さＴがこの折り曲げ深さｄより小さくなるようにしている。このようなリード形態はいわゆるガルウィングと呼ばれるもので、パッケージの両サイドから外部導出リードがＳ字状をなすように導出されている。これら第１および第２の外部導出リードの厚さｔは通常０．２ｍｍ程度であり、最近では０．１５ｍｍ未満のものも増えてきている。   This semiconductor device includes a first external lead having an element placement portion and a second external lead having a distance from the element placement portion, and a part of these is sealed with resin. The first external lead is bent into an S-shape, the bending depth d is equal to or greater than the thickness t of the first external lead, and the thickness T of the sealing resin on the back side of the element mounting portion is the bending depth. It is designed to be smaller than d. Such a lead form is called a so-called gull wing, and the external lead leads are led out from both sides of the package so as to form an S shape. The thickness t of the first and second lead-out leads is usually about 0.2 mm, and recently, the thickness t is less than 0.15 mm.

この構成により、半導体装置の高さを低く抑えることができるとともに、素子載置部として必要な平坦領域を確保することができ、また素子載置部と第２外部導出リードとの間隔を短くすることができるため、縦方向の寸法を小さく抑えることができる。   With this configuration, the height of the semiconductor device can be kept low, a flat region necessary for the element mounting portion can be secured, and the distance between the element mounting portion and the second external lead is shortened. Therefore, the vertical dimension can be kept small.

しかしながら、このような半導体装置は、強度を高く維持することはできるが、スイッチング用ＭＯＳＦＥＴでは、オン抵抗の低減という大きな要求があり、さらなるオン抵抗の低減が求められていた。また大電流用のＭＯＳＦＥＴにおいては、更なる放熱性が求められていた。   However, although such a semiconductor device can maintain high strength, there is a great demand for a reduction in on-resistance in the switching MOSFET, and further reduction in on-resistance has been demanded. Further, in the MOSFET for large current, further heat dissipation has been demanded.

このような要求に応えて、リードフレームを、２本づつ相対向する２辺から導出された少なくとも４本のリードが、樹脂パッケージ内部で一体化されて主パッドを構成するとともに、別の２本のリードが、この主パッドから離間して導出され、この主パッドにＭＯＳＦＥＴのドレイン電極を接続すると共に、別の２本のリードにソースおよびゲートをそれぞれ接続した半導体装置が提案されている（特許文献２）。
この構造によれば、オン抵抗の低減を図ることは可能となる。 In response to such a demand, at least four leads derived from two opposite sides of the lead frame are integrated in the resin package to constitute the main pad, and another two lead frames are formed. A semiconductor device has been proposed in which a lead is spaced apart from the main pad, the drain electrode of the MOSFET is connected to the main pad, and a source and a gate are connected to the other two leads, respectively (patent) Reference 2).
According to this structure, it is possible to reduce the on-resistance.

しかしながら、半導体チップの大型化は高まる一方であり、最近では１．２ｍｍ程度の大型チップも提案されており、所望の強度を得るためには、樹脂パッケージにおける樹脂厚が必要となり、この樹脂厚が半導体装置の小型化薄型化を阻む原因となっていた。   However, the increase in size of semiconductor chips is increasing, and recently, a large chip of about 1.2 mm has been proposed, and in order to obtain a desired strength, the resin thickness in the resin package is required. This has been a cause of hindering miniaturization and thinning of semiconductor devices.

特開２０００−１４５４３３公報JP 2000-145433 A 米国特許第５６２５２２６号明細書US Pat. No. 5,625,226

本発明は前記実情に鑑みてなされたもので、大型チップの使用に際しても小型でかつオン抵抗の低いＭＯＳＦＥＴを形成することのできる半導体装置を提供することを目的とする。   The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device that can form a small MOSFET with low on-resistance even when a large chip is used.

上記課題を解決するため、本発明の半導体装置は、樹脂パッケージと、前記樹脂パッケージ内部で、一体化され、チップ搭載部を構成する少なくとも２本の主リードと、前記チップ搭載部に搭載された半導体チップと、前記半導体チップの表面でそれぞれ電極に接続された第１および第２の表面リードとを含み、前記主リードおよび前記第１および第２の表面リードが、前記樹脂パッケージの底面と同一面上を外方にまっすぐに伸長するようにしたことを特徴とする。   In order to solve the above-described problems, a semiconductor device according to the present invention is mounted on a resin package, at least two main leads that are integrated inside the resin package and constitute a chip mounting portion, and the chip mounting portion. A semiconductor chip; and first and second surface leads connected to electrodes on the surface of the semiconductor chip, respectively, wherein the main lead and the first and second surface leads are the same as the bottom surface of the resin package It is characterized by extending straight on the surface outward.

この構成によれば、前記主リードおよび前記第１および第２の表面リードが、前記樹脂パッケージの底面と同一面上をまっすぐに伸長するように構成されているため、薄型化が可能であり、アウターリードすなわち、樹脂パッケージ外への導出部分を短くすることができ、実装面積の低減、およびオン抵抗の低減をはかることができる。またチップの大型化に際しても、樹脂封止後にリードを折り曲げる必要がなく、リードの成形工程において、樹脂の抜けが生じたりすることがないため、樹脂厚を薄くしても抜けやクラックが生じることなく、薄型で信頼性の高い半導体装置を提供することができる。   According to this configuration, since the main lead and the first and second surface leads are configured to extend straight on the same surface as the bottom surface of the resin package, it is possible to reduce the thickness. The outer lead, that is, the lead-out portion to the outside of the resin package can be shortened, so that the mounting area can be reduced and the on-resistance can be reduced. In addition, even when the chip size is increased, it is not necessary to bend the lead after sealing the resin, and the resin will not come off in the lead molding process. In addition, a thin and highly reliable semiconductor device can be provided.

また本発明の半導体装置は、前記主リードは前記チップ搭載部の１辺から導出されるものを含む。
この構成によれば、プリント基板への実装が容易で安定で信頼性の高い半導体装置を形成することができる。
本発明の半導体装置は、前記主リードは前記チップ搭載部の１辺全体にわたり導出された複数本のリードである。
この構成によれば、より接触抵抗を低減することができ、オン抵抗の低減を図ることができる。 In the semiconductor device of the present invention, the main lead may be derived from one side of the chip mounting portion.
According to this configuration, it is possible to form a stable and highly reliable semiconductor device that can be easily mounted on a printed circuit board.
In the semiconductor device of the present invention, the main lead is a plurality of leads led out over the entire side of the chip mounting portion.
According to this configuration, the contact resistance can be further reduced, and the on-resistance can be reduced.

また本発明の半導体装置は、前記主リードは前記チップ搭載部の相対向する２辺から２本づつ導出されたものを含む。
この構成によれば、安定で信頼性の高い半導体装置を形成することができる。 In the semiconductor device according to the present invention, the main leads may be derived from two opposite sides of the chip mounting portion.
According to this configuration, a stable and highly reliable semiconductor device can be formed.

また本発明の半導体装置は、前記主リードおよび表面リードは前記チップ搭載部の相対向する２辺のうちの１辺から３本、他の１辺側から２本導出されたものを含む。
この構成によれば、対称でないため、実装工程においてあるいはプリント基板への搭載時における誤接続を防ぐことができる。 The semiconductor device of the present invention includes one in which the main lead and the surface lead are derived from one of two opposing sides of the chip mounting portion and two from the other one side.
According to this configuration, since it is not symmetrical, it is possible to prevent erroneous connection in the mounting process or when mounting on the printed circuit board.

また本発明の半導体装置は、前記主リードは前記樹脂パッケージの中心に対して非対称となるように構成されたものを含む。
この構成によれば、対称でないため、実装工程においてあるいはプリント基板への搭載時における誤接続を防ぐことができる。 The semiconductor device of the present invention includes one in which the main lead is configured to be asymmetric with respect to the center of the resin package.
According to this configuration, since it is not symmetrical, it is possible to prevent erroneous connection in the mounting process or when mounting on the printed circuit board.

また本発明の半導体装置は、前記主リードは相対向する側で幅が異なるように構成されたものを含む。
この構成によれば、対称でないため、実装工程においてあるいはプリント基板への搭載時における誤接続を防ぐことができる。 The semiconductor device of the present invention includes a semiconductor device configured such that the main leads have different widths on opposite sides.
According to this configuration, since it is not symmetrical, it is possible to prevent erroneous connection in the mounting process or when mounting on the printed circuit board.

また本発明の半導体装置は、前記主リードの少なくとも１本が樹脂パッケージ内部で不連続部を構成する
この構成によれば、不連続部が熱歪を緩和し、ダイパッドの平坦性を阻むことなく、平坦で高精度のリードフレームを維持することができ、実装が容易となる上、信頼性の高いものとなる。また樹脂封止工程における熱によって歪を生じることもない。この不連続部としては、切断部、切り込み（歪除去部）等が適用可能である。また、リードフレーム自体は対称でないため、実装工程において誤接続を防ぐことができる。 In the semiconductor device according to the present invention, at least one of the main leads constitutes a discontinuous portion inside the resin package. According to this configuration, the discontinuous portion relaxes thermal distortion and does not hinder the flatness of the die pad. In addition, a flat and highly accurate lead frame can be maintained, which facilitates mounting and increases reliability. Further, no distortion occurs due to heat in the resin sealing step. As this discontinuous portion, a cut portion, a cut (distortion removal portion), or the like can be applied. Further, since the lead frame itself is not symmetrical, erroneous connection can be prevented in the mounting process.

また本発明の半導体装置は、前記主リードは前記樹脂パッケージの中心線に対して外部導出領域においては対称であるようにしたものを含む。
この構成によれば、この半導体装置が実装されるプリント基板の配線は変更することなく、信頼性の向上を図ることができる。 The semiconductor device according to the present invention includes a semiconductor device in which the main lead is symmetrical in the external lead-out region with respect to the center line of the resin package.
According to this configuration, it is possible to improve the reliability without changing the wiring of the printed board on which the semiconductor device is mounted.

本発明の半導体装置によれば、薄くて大きい半導体チップを用いる場合にも、オン抵抗が低く、薄型でかつ、信頼性の高い半導体装置を提供することが可能となる。   According to the semiconductor device of the present invention, even when a thin and large semiconductor chip is used, it is possible to provide a semiconductor device that has low on-resistance, is thin, and has high reliability.

以下、本発明の実施の形態について、図面を参照しつつ詳細に説明する。
（実施の形態１）
図１（ａ）乃至（ｃ）は、本発明の実施の形態１におけるＭＯＳＦＥＴ（半導体装置）を示す上面図、Ａ−Ａ断面図、側面図である。この半導体装置は、ＭＯＳＦＥＴを構成する半導体チップ６をフラットタイプリードを備えたリードフレーム１０に載置し、樹脂パッケージ１に封止した面実装型の半導体装置を構成するものである。すなわち、この半導体装置は、樹脂パッケージ１と、前記樹脂パッケージ１内部で、一体化され、チップ搭載部２ｄを構成する３本の主リード２ａ、２ｂ、２ｃと、前記チップ搭載部２ｄに搭載された半導体チップ６と、前記半導体チップ６の表面で半導体チップのソース電極に接続された第１および第２の表面リード３ａ、３ｂと、ゲートに接続された第３の表面リード４とを含み、前記主リード２ａ、２ｂ、２ｃおよび前記第１乃至第３の表面リード３ａ、３ｂ、４が前記樹脂パッケージの底面と同一面上をまっすぐに伸長するようにしたことを特徴とする。 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
1A to 1C are a top view, a cross-sectional view taken along line AA, and a side view showing a MOSFET (semiconductor device) according to the first embodiment of the present invention. This semiconductor device constitutes a surface mount type semiconductor device in which a semiconductor chip 6 constituting a MOSFET is mounted on a lead frame 10 having flat type leads and sealed in a resin package 1. That is, the semiconductor device is integrated with the resin package 1 and the three main leads 2a, 2b, and 2c constituting the chip mounting portion 2d, and the chip mounting portion 2d. A semiconductor chip 6, first and second surface leads 3a and 3b connected to the source electrode of the semiconductor chip on the surface of the semiconductor chip 6, and a third surface lead 4 connected to the gate, The main leads 2a, 2b, 2c and the first to third surface leads 3a, 3b, 4 extend straight on the same surface as the bottom surface of the resin package.

ここでチップ搭載部２ｄは半導体チップ６の裏面全面に形成されたドレイン電極に導電性接着剤を介して固着されており、３本の主リード２ａ、２ｂ、２ｃを介して外部接続される。また第１および第２の表面リード３ａ、３ｂは、前記３本の主リード２ａ、２ｂ、２ｃのうちの２本と樹脂パッケージ１の中心線に対して対称となるように導出されており、ボンディングワイヤ５を介して半導体チップ表面に形成されたソース電極と接続されている。一方第３の表面リード４は、同様に、前記３本の主リード２ａ、２ｂ、２ｃのうちの１本である２ｃと樹脂パッケージ１の中心線に対して対称となるように導出されており、ボンディングワイヤ５を介して半導体チップ表面に形成されたゲート電極と接続されている。   Here, the chip mounting portion 2d is fixed to a drain electrode formed on the entire back surface of the semiconductor chip 6 through a conductive adhesive, and is externally connected through three main leads 2a, 2b, and 2c. The first and second surface leads 3a, 3b are led out symmetrically with respect to two of the three main leads 2a, 2b, 2c and the center line of the resin package 1, It is connected to a source electrode formed on the surface of the semiconductor chip via a bonding wire 5. On the other hand, the third surface lead 4 is similarly derived so as to be symmetric with respect to 2c, which is one of the three main leads 2a, 2b and 2c, and the center line of the resin package 1. The gate electrode formed on the surface of the semiconductor chip is connected via the bonding wire 5.

このリードフレーム１０は銅の条材を、Ｓｎ−２Ｂｉめっき層で被覆したものである。そして各リードの樹脂パッケージ１からの導出部の長さは０．２５ｍｍ、樹脂パッケージは１．６×１．６、高さ０．５８ｍｍ、各リードの板厚は０．１３、リード幅は０．２ｍｍとした。   The lead frame 10 is obtained by coating a copper strip with an Sn-2Bi plating layer. The length of the lead-out portion of each lead from the resin package 1 is 0.25 mm, the resin package is 1.6 × 1.6, the height is 0.58 mm, the thickness of each lead is 0.13, and the lead width is 0 2 mm.

次に、この半導体装置の実装方法について説明する。
まず、このリードフレームの製造方法について説明する。
この方法では、図２に示すように金属製の板状体（銅板）を打ち抜き加工により形状加工し、電解めっきによりＳｎ−２Ｂｉめっき層を形成する。ここでリードフレームは送り穴Hを有するサイドバー１１で複数のユニットＵが接続されている。またパンチによりチップ載置部２ｄがリード面よりも少し上にくるように成形する。これは半導体チップのパッドとリードとの間隔を低減し、ボンディングワイヤをなるべく短くするためである。 Next, a method for mounting the semiconductor device will be described.
First, a method for manufacturing the lead frame will be described.
In this method, as shown in FIG. 2, a metal plate-like body (copper plate) is formed by punching and an Sn-2Bi plating layer is formed by electrolytic plating. Here, the lead frame has a plurality of units U connected by a side bar 11 having a feed hole H. Moreover, it shape | molds so that the chip | tip mounting part 2d may come slightly above a lead surface with a punch. This is to reduce the distance between the pads and leads of the semiconductor chip and shorten the bonding wire as much as possible.

次にこのリードフレームを用いたＭＯＳＦＥＴの実装方法について説明する。   Next, a MOSFET mounting method using this lead frame will be described.

まず図３（a）に示すように、図２に示したリードフレームのチップ載置部２ｄにＭＯＳＦＥＴを構成する半導体チップ６の裏面が搭載されるように固着し、ボンディングワイヤ５によって半導体チップの表面側に形成されたソース電極と第１および第２の表面リードとを接続する。続いて同様にボンディングワイヤ５によって半導体チップの表面側に形成されたゲート電極と第３の表面リード４とをボンディングワイヤ５を介して接続する。   First, as shown in FIG. 3A, the back surface of the semiconductor chip 6 constituting the MOSFET is fixed to the chip mounting portion 2d of the lead frame shown in FIG. The source electrode formed on the surface side is connected to the first and second surface leads. Subsequently, the gate electrode formed on the surface side of the semiconductor chip and the third surface lead 4 are similarly connected via the bonding wire 5 by the bonding wire 5.

この後、図３（ｂ）に示すように、エポキシ樹脂を用いて樹脂封止を行い半導体装置を形成する。   Thereafter, as shown in FIG. 3B, resin sealing is performed using an epoxy resin to form a semiconductor device.

そして最後に図３（ｃ）に示すように、各リードをサイドバー１１から切除するとともに、樹脂パッケージ１からの突出長が所定の長さとなるように切断し、フラットタイプのリードを備えた面実装型半導体装置を得ることが出来る。   Finally, as shown in FIG. 3 (c), each lead is cut out from the side bar 11 and cut so that the protruding length from the resin package 1 becomes a predetermined length, thereby providing a flat type lead. A mounted semiconductor device can be obtained.

かかる構成によれば、前記主リードおよび前記第１乃至第３の表面リードが、前記樹脂パッケージ１の底面と同一面上をまっすぐに伸長するように構成されているため、薄型化が可能である。また、アウターリードすなわち、樹脂パッケージ外への導出部分を短くすることができ、実装面積の低減、およびオン抵抗の低減をはかることができる。   According to such a configuration, the main lead and the first to third surface leads are configured to extend straight on the same surface as the bottom surface of the resin package 1, and thus can be thinned. . In addition, the outer lead, that is, the lead-out portion to the outside of the resin package can be shortened, so that the mounting area can be reduced and the on-resistance can be reduced.

また半導体チップ裏面全体に接続された３本の主リードが導出されているため、ドレイン端子の接触抵抗が大幅に低減されるとともに、特にフラットタイプのリードであるため放熱性もすぐれたものとなる。ソース端子についても２本の表面リードに接続されているため低抵抗化を図ることができる。   In addition, since three main leads connected to the entire back surface of the semiconductor chip are led out, the contact resistance of the drain terminal is greatly reduced, and the heat dissipation is also excellent because of the flat type lead. . Since the source terminal is also connected to the two surface leads, the resistance can be reduced.

またチップの大型化に際しても、樹脂封止後にリードを折り曲げる必要がなく、リードの成形工程において、樹脂の抜けが生じたりすることがないため、樹脂厚を薄くしても抜けやクラックが生じることなく、薄型で信頼性の高い半導体装置を提供することができる。   In addition, even when the chip size is increased, it is not necessary to bend the lead after sealing the resin, and the resin will not come off in the lead molding process. In addition, a thin and highly reliable semiconductor device can be provided.

樹脂パッケージの底面と同一面上に、リードが突出して形成されているため、安定して実装することができる。従って、プリント基板などへの実装に際し、接触不良のない半導体装置を提供することが可能となる。このように本実施の形態によれば、安定な外部端子構造を形成することが可能となる。   Since the leads protrude from the same surface as the bottom surface of the resin package, the resin package can be mounted stably. Accordingly, it is possible to provide a semiconductor device free from contact failure when mounted on a printed circuit board or the like. Thus, according to the present embodiment, a stable external terminal structure can be formed.

また、半導体チップの搭載時にも、チップ載置部は３本の主リードで支持されているため、平坦性を良好に維持することができ、位置ずれもなく、確実で信頼性の高いボンディングを可能にする。また、樹脂封止後、樹脂パッケージ底面と同一表面上でリードを切断するため、半導体装置としての変形もない。   In addition, even when a semiconductor chip is mounted, the chip mounting portion is supported by the three main leads, so that the flatness can be maintained satisfactorily, and there is no misalignment and reliable bonding with high reliability is achieved. enable. Further, since the leads are cut on the same surface as the bottom surface of the resin package after resin sealing, there is no deformation as a semiconductor device.

また、本発明のリードフレームにおいては、前記リード表面に形成されるＳｎ−Ｂｉめっき層は、配線パターンを半田と共晶を形成し易い金などの金属で構成すれば、プリント基板などへの実装に際し、良好にボンディングを行うことが可能となる。
さらに、本実施の形態のリードフレームは、打ち抜き加工に代えて、フォトリソグラフィ工程を経て、高精度で信頼性の高いリードフレームを容易に形成することが可能となる。 In the lead frame of the present invention, the Sn-Bi plating layer formed on the lead surface can be mounted on a printed circuit board or the like if the wiring pattern is made of a metal such as gold that can easily form a eutectic with solder. In this case, bonding can be performed satisfactorily.
Furthermore, the lead frame of this embodiment can easily form a highly accurate and highly reliable lead frame through a photolithography process instead of punching.

（実施の形態２）
次に本発明の実施の形態２について説明する。
本実施の形態の半導体装置では、図４（ａ）乃至（ｃ）に示すように、前記主リード２ａ、２ｂ、２ｃは相対向する２辺のうちの１辺から３本、前記表面リード３ａは他の一辺から導出され、主リードおよび表面リードは前記樹脂パッケージの中心に対して非対称となるように構成された点で前記実施の形態１と異なるもので他は前記実施の形態１と同様に形成されている。ここで図４（ａ）乃至（ｃ）は本発明の半導体装置を示す上面図、Ａ−Ａ断面図、側面図である。 (Embodiment 2)
Next, a second embodiment of the present invention will be described.
In the semiconductor device according to the present embodiment, as shown in FIGS. 4A to 4C, the main leads 2a, 2b, and 2c are three from one of the two opposite sides, and the surface lead 3a. Is derived from the other side, and the main lead and the surface lead are different from those of the first embodiment in that they are configured to be asymmetric with respect to the center of the resin package. Others are the same as in the first embodiment. Is formed. 4A to 4C are a top view, a cross-sectional view taken along line AA, and a side view showing the semiconductor device of the present invention.

製造に際しても同様であり、この場合リードフレームにおいても実装後においてもリードが対称でないため、方向を間違えたりすることがほとんどなくなるため実装効率の向上をはかることができる。   This also applies to the manufacturing process. In this case, since the leads are not symmetric even after mounting in the lead frame, the mounting efficiency can be improved because the direction is hardly changed.

（実施の形態３）
次に本発明の実施の形態３について説明する。
本実施の形態の半導体装置では、図５（ａ）乃至（ｃ）に示すように、前記主リード２ａ、２ｂ、２ｃは前記チップ搭載部２ｄの相対向する２辺のうちの１辺から３本、前記表面リード３Ｓは他の一辺側から導出され、表面リード３Ｓは主リードよりも幅広となるように形成された点で前記実施の形態１と異なるもので他は前記実施の形態１と同様に形成されている。ここでも主リードおよび表面リードは前記樹脂パッケージの中心に対して非対称となるように構成される。ここでも図５（ａ）乃至（ｃ）は本発明の半導体装置を示す上面図、Ａ−Ａ断面図、側面図である。 (Embodiment 3)
Next, a third embodiment of the present invention will be described.
In the semiconductor device of the present embodiment, as shown in FIGS. 5A to 5C, the main leads 2a, 2b, and 2c are 3 to 3 from one side of the chip mounting portion 2d facing each other. The surface lead 3S is led out from the other side, and the surface lead 3S is different from the first embodiment in that the surface lead 3S is formed to be wider than the main lead. It is formed similarly. Again, the main lead and the surface lead are configured to be asymmetric with respect to the center of the resin package. Here, FIGS. 5A to 5C are a top view, a cross-sectional view taken along line AA, and a side view showing the semiconductor device of the present invention.

製造に際しても同様であり、実施の形態２に比べて表面リードが幅広に構成される分ソース電極の取り出し抵抗が大幅に低減される。また実施の形態２と同様、この場合もリードフレームにおいても実装後においてもリードが対称でないため、方向を間違えたりすることがほとんどなくなるため実装効率の向上をはかることができる。   The manufacturing process is the same. Compared with the second embodiment, the lead-out resistance of the source electrode is greatly reduced because the surface lead is formed wider. As in the second embodiment, in this case as well, the leads are not symmetric even after the mounting in the lead frame, so that the mounting direction can be improved because the direction is hardly changed.

（実施の形態４）
次に本発明の実施の形態４について説明する。
本実施の形態の半導体装置では、図６（ａ）乃至（ｃ）に示すように、主リードを幅広の主リード２Ｓと、通常幅の主リード２ｃの２本で構成した点が実施の形態３と異なるのみで他は実施の形態３と同様である。すなわち主リード２Ｓ、２ｃは前記チップ搭載部２ｄの相対向する２辺のうちの１辺から２本、前記表面リード３Ｓは他の一辺側から導出され、表面リード３Ｓは主リードとほぼ同程度の幅広となるように形成されている。ここでは主リードおよび表面リードは前記樹脂パッケージの中心に対して対称となるように構成される。ここで図６（ａ）乃至（ｃ）は本発明の半導体装置を示す上面図、Ａ−Ａ断面図、側面図である。 (Embodiment 4)
Next, a fourth embodiment of the present invention will be described.
In the semiconductor device according to the present embodiment, as shown in FIGS. 6A to 6C, the main lead is composed of two main leads, a wide main lead 2S and a normal width main lead 2c. The third embodiment is the same as the third embodiment except for the third embodiment. That is, the main leads 2S and 2c are led out from one of the two opposite sides of the chip mounting portion 2d, the surface lead 3S is led out from the other side, and the surface lead 3S is almost the same as the main lead. It is formed to be wide. Here, the main lead and the surface lead are configured to be symmetric with respect to the center of the resin package. 6A to 6C are a top view, a cross-sectional view taken along line AA, and a side view showing the semiconductor device of the present invention.

製造に際しても同様であり、実施の形態２に比べて表面リードが幅広に構成される分ソース電極の取り出し抵抗が大幅に低減され、さらには放熱性も向上する。また実施の形態２と同様、この場合もリードフレームにおいても実装後においてもリードが対称でないため、方向を間違えたりすることがほとんどなくなるため実装効率の向上をはかることができる。
（実施の形態５）
次に本発明の実施の形態５について説明する。
本実施の形態の半導体装置では、図７（ａ）乃至（ｃ）に示すように、前記主リードの少なくとも１本が樹脂パッケージ内部で歪除去のための不連続部としてのスリットＳを有するように構成した点で実施の形態１と異なるのみで、他は同様に形成されている。すなわち主リード２ａ、２ｂ、２ｃは前記チップ搭載部２ｄの相対向する２辺のうちの１辺から３本、前記表面リード３ａ、３ｂ、４は他の一辺側から導出され、前記実施の形態１と同様に形成されている。ここでは主リードおよび表面リードは外観上では実施の形態１の半導体装置と同様に、樹脂パッケージの中心に対して対称となるように構成される The manufacturing process is the same as in the case of the second embodiment, and the resistance of the source electrode to be taken out is greatly reduced as compared with the second embodiment, and the heat dissipation is improved. As in the second embodiment, in this case as well, the leads are not symmetric even after the mounting in the lead frame, so that the mounting direction can be improved because the direction is hardly changed.
(Embodiment 5)
Next, a fifth embodiment of the present invention will be described.
In the semiconductor device of the present embodiment, as shown in FIGS. 7A to 7C, at least one of the main leads has a slit S as a discontinuous portion for removing strain inside the resin package. Only the points different from the first embodiment are the same as those in the first embodiment, and the others are formed in the same manner. That is, the main leads 2a, 2b, and 2c are led out from one of two opposing sides of the chip mounting portion 2d, and the surface leads 3a, 3b, and 4 are led out from the other side. 1 is formed. Here, the main lead and the surface lead are configured to be symmetrical with respect to the center of the resin package in the same manner as the semiconductor device of the first embodiment in appearance.

製造に際しても同様であり、実施の形態１に比べて主リードが不連続部を有し歪を吸収することができるため、実装効率の向上をはかることができる。すなわち、この構成によれば、不連続部が熱歪を緩和し、ダイパッドの平坦性を阻むことなく、平坦で高精度のリードフレームを維持することができ、実装が容易となる上、信頼性の高いものとなる。
また樹脂封止工程における熱によって歪を生じることもない。この不連続部としては、切断部、切り込み（歪除去部）等が適用可能である。また、リードフレーム自体は対称でないため、実装工程において誤接続を防ぐことができる。 The same applies to the manufacturing process, and the main lead has a discontinuous portion and can absorb distortion compared to the first embodiment, so that the mounting efficiency can be improved. In other words, according to this configuration, the discontinuous portion can alleviate thermal distortion, and can maintain a flat and high-precision lead frame without hindering the flatness of the die pad, facilitating mounting and reliability. Will be expensive.
Further, no distortion occurs due to heat in the resin sealing step. As this discontinuous portion, a cut portion, a cut (distortion removal portion), or the like can be applied. Further, since the lead frame itself is not symmetrical, erroneous connection can be prevented in the mounting process.

また本発明の半導体装置は、前記主リードは前記樹脂パッケージの中心線に対して外部導出領域においては対称であり、この半導体装置が実装されるプリント基板の配線は変更することなく、信頼性の向上を図ることができる。   Further, in the semiconductor device of the present invention, the main lead is symmetrical in the external lead-out region with respect to the center line of the resin package, and the wiring of the printed circuit board on which the semiconductor device is mounted is not changed and the reliability is improved. Improvements can be made.

なお、前記実施の形態では、ＭＯＳＦＥＴの実装について説明したが、このようなディスクリート素子に限定されることなく、ＩＣやＬＳＩなどにも適用可能であることはいうまでもない。   In the above-described embodiment, the mounting of the MOSFET has been described. However, it is needless to say that the present invention is not limited to such a discrete element but can be applied to an IC, an LSI, or the like.

以上説明してきたように、本発明の半導体装置によれば、オン抵抗の低減を図ることができ、大型の半導体チップに対しても対向可能であるため、スイッチング用のＭＯＳＦＥＴだけでなく、種々のデバイスに適用可能である。   As described above, according to the semiconductor device of the present invention, the on-resistance can be reduced, and even a large-sized semiconductor chip can be opposed to the semiconductor device. Applicable to devices.

本発明の実施の形態１に係る半導体装置を示す図であり、（ａ）は上面図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は正面図である。BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the semiconductor device which concerns on Embodiment 1 of this invention, (a) is a top view, (b) is AA sectional drawing of (a), (c) is a front view. 本発明の実施の形態１に係るリードフレームの要部拡大図である。FIG. 3 is an enlarged view of a main part of the lead frame according to Embodiment 1 of the present invention. 本発明の実施の形態１に係る半導体装置の製造工程図である。It is a manufacturing process figure of the semiconductor device concerning Embodiment 1 of the present invention. 本発明の実施の形態２に係る半導体装置を示す図であり、（ａ）は上面図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は正面図である。It is a figure which shows the semiconductor device which concerns on Embodiment 2 of this invention, (a) is a top view, (b) is AA sectional drawing of (a), (c) is a front view. 本発明の実施の形態３に係る半導体装置を示す図であり、（ａ）は上面図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は正面図である。It is a figure which shows the semiconductor device which concerns on Embodiment 3 of this invention, (a) is a top view, (b) is AA sectional drawing of (a), (c) is a front view. 本発明の実施の形態４に係る半導体装置を示す図であり、（ａ）は上面図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は正面図である。It is a figure which shows the semiconductor device which concerns on Embodiment 4 of this invention, (a) is a top view, (b) is AA sectional drawing of (a), (c) is a front view. 本発明の実施の形態５に係る半導体装置を示す図であり、（ａ）は上面図、（ｂ）は（ａ）のＡ−Ａ断面図、（ｃ）は正面図である。It is a figure which shows the semiconductor device which concerns on Embodiment 5 of this invention, (a) is a top view, (b) is AA sectional drawing of (a), (c) is a front view.

符号の説明Explanation of symbols

１ 樹脂パッケージ
２ 主リード
３ 表面リード
４ 表面リード
５ ボンディングワイヤ
６ 半導体チップ
１０ リードフレーム
１１ サイドバー 1 Resin Package 2 Main Lead 3 Surface Lead 4 Surface Lead 5 Bonding Wire 6 Semiconductor Chip 10 Lead Frame 11 Sidebar

Claims (8)

樹脂パッケージと、
前記樹脂パッケージ内部で、一体化され、チップ搭載部を構成する少なくとも２本の主リードと、
前記チップ搭載部に搭載された半導体チップと、
前記半導体チップの表面でそれぞれ電極に接続された第１および第２の表面リードとを含み、前記主リードおよび前記第１および第２の表面リードが、前記樹脂パッケージの底面と同一面上を外方にまっすぐに伸長するようにした半導体装置。 A resin package;
At least two main leads integrated into the resin package and constituting a chip mounting portion;
A semiconductor chip mounted on the chip mounting portion;
First and second surface leads connected to electrodes on the surface of the semiconductor chip, respectively, and the main lead and the first and second surface leads are on the same plane as the bottom surface of the resin package. A semiconductor device that extends straight in the direction. 請求項１に記載の半導体装置であって、
前記主リードは前記チップ搭載部の１辺から導出される半導体装置。 The semiconductor device according to claim 1,
The main lead is a semiconductor device derived from one side of the chip mounting portion. 請求項２に記載の半導体装置であって、
前記主リードは前記チップ搭載部の１辺全体にわたり導出された複数本のリードである半導体装置。 The semiconductor device according to claim 2,
The semiconductor device, wherein the main lead is a plurality of leads led out over the entire side of the chip mounting portion. 請求項２に記載の半導体装置であって、
前記主リードは前記チップ搭載部の相対向する２辺のうちの１辺から２本、前記表面リードは他の１辺側から導出された半導体装置。 The semiconductor device according to claim 2,
The main leads are two from one side of the two opposite sides of the chip mounting portion, and the surface lead is derived from the other side. 請求項２に記載の半導体装置であって、
前記主リードおよび表面リードは前記樹脂パッケージの中心に対して非対称となるように構成された半導体装置。 The semiconductor device according to claim 2,
The semiconductor device is configured such that the main lead and the surface lead are asymmetric with respect to the center of the resin package. 請求項２に記載の半導体装置であって、
前記主リードまたは表面リードは相対向する側で互いに幅が異なるように構成された半導体装置。 The semiconductor device according to claim 2,
A semiconductor device configured such that the main leads or the surface leads have different widths on opposite sides. 請求項２に記載の半導体装置であって、
前記主リードの少なくとも１本が樹脂パッケージ内部で不連続部を構成するように構成された半導体装置。 The semiconductor device according to claim 2,
A semiconductor device configured such that at least one of the main leads forms a discontinuous portion inside the resin package. 請求項７に記載の半導体装置であって、
前記主リードは前記樹脂パッケージの中心線に対して外部導出領域においては対称である半導体装置。 The semiconductor device according to claim 7,
A semiconductor device in which the main lead is symmetrical in the external lead-out region with respect to the center line of the resin package.
JP2005014018A 2005-01-21 2005-01-21 Semiconductor device Expired - Fee Related JP4849802B2 (en)

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JP2021090074A (en) * 2016-09-27 2021-06-10 パナソニックＩｐマネジメント株式会社 Semiconductor device
JP2020150284A (en) * 2020-06-18 2020-09-17 ローム株式会社 Semiconductor device
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