JPH09205173A - Manufacture of lead frame - Google Patents
Manufacture of lead frameInfo
- Publication number
- JPH09205173A JPH09205173A JP3000896A JP3000896A JPH09205173A JP H09205173 A JPH09205173 A JP H09205173A JP 3000896 A JP3000896 A JP 3000896A JP 3000896 A JP3000896 A JP 3000896A JP H09205173 A JPH09205173 A JP H09205173A
- Authority
- JP
- Japan
- Prior art keywords
- bus bar
- lead frame
- lead
- connecting piece
- inner leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体チップをインナー
リード、バスバ−の下面又は上面に設けるリードフレー
ムの製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a lead frame in which a semiconductor chip is provided on the inner lead or the lower or upper surface of a bus bar.
【0002】[0002]
【従来技術】半導体装置は高機能、高応答性、小型化を
要請され、これに対応し半導体チップの高集積化、半導
体チップの面積率を高める半導体装置の構成、半導体装
置内の配線の短縮等が検討されている。例えば特公平4
−1503号のように半導体チップの上面にリードフレ
ームのインナーリードを絶縁テ−プを介して重ねて設け
たものがある。これでは重ねた分だけ大きな半導体チッ
プを使用でき、また、チップ端子とインナーリードの接
続配線を短くでき、信号応答の高速化やインピ−ダンス
の低減等の作用効果が奏されている。2. Description of the Related Art A semiconductor device is required to have high functionality, high responsiveness, and downsizing, and in response to this, high integration of a semiconductor chip, a structure of a semiconductor device for increasing a semiconductor chip area ratio, and shortening of wiring in the semiconductor device. Etc. are being considered. For example 4
There is a type in which inner leads of a lead frame are provided on the upper surface of a semiconductor chip with an insulating tape interposed therebetween such as No. 1503. This makes it possible to use semiconductor chips as large as they are stacked, and to shorten the connection wiring between the chip terminals and the inner leads, which has the effect of speeding up signal response and reducing impedance.
【0003】[0003]
【この発明が解決しようとする課題】かかる半導体装置
のリードフレームでは絶縁テ−プを貼着するとき、イン
ナーリード、あるいは対向するインナーリードの間に形
成されているバスバ−の平坦度が悪いと絶縁テ−プの貼
着に支障を生じ剥れることがある。また、その後、半導
体チップをインナーリードやバスバ−の下面あるいは上
面に設置する際、接着不良や剥離等の支障を生じ、半導
体装置の信頼を損なうことになる。In the lead frame of such a semiconductor device, when the insulating tape is attached, the inner leads or the bus bars formed between the opposing inner leads have poor flatness. The insulation tape may be stuck and may come off. Further, thereafter, when the semiconductor chip is installed on the lower surface or the upper surface of the inner lead or the bus bar, problems such as defective adhesion and peeling occur, and the reliability of the semiconductor device is impaired.
【0004】本発明はインナーリード及びバスバ−の平
坦度がすぐれ、前記問題のないリードフレームを得るこ
とを目的とする。An object of the present invention is to obtain a lead frame which has excellent flatness of the inner leads and the bus bar and does not have the above problems.
【0005】[0005]
【課題を解決するための手段】本発明の要旨は、インナ
ーリード、バスバ−の下面又は上面に半導体チップを設
置するリードフレームの製造方法において、前記インナ
ーリード、バスバ−の少なくとも一方の中間部を連結片
で連結した状態で打抜き形成し、焼鈍し、その後、前記
中間部の連結片を除去するリードフレームの製造方法に
ある。他の要旨は、前記焼鈍の後、前記中間部の連結片
を除去する前に、半導体チップを設置するインナーリー
ド、バスバ−に両面接着絶縁テープを貼着してから前記
連結片を除去するところにある。The gist of the present invention is to provide a method for manufacturing a lead frame in which a semiconductor chip is mounted on the lower surface or the upper surface of an inner lead or a bus bar, wherein at least one of the inner lead and the bus bar has an intermediate portion. This is a method for manufacturing a lead frame in which a connecting piece is punched and annealed in a state of being connected, and then the connecting piece of the intermediate portion is removed. Another gist is to remove the connecting piece after attaching the double-sided adhesive insulating tape to the inner lead and the bus bar for mounting the semiconductor chip after the annealing and before removing the connecting piece in the intermediate portion. It is in.
【0006】[0006]
【発明の実施の形態】本発明は、リードフレームのイン
ナーリード、バスバ−を打抜き形成する際、少なくとも
一方の中間部を連結片でつないで行うので、当該インナ
ーリード−が細くても、またバスバ−が細く且つ長くて
も変形せず、所定の平坦度を保ったまま形成される。焼
鈍した後に前記中間部の連結片は除去され、ねじれや傾
きがなく形状がすぐれる。而して、当該インナーリー
ド、バスバ−の下面あるいは上面に半導体チップを設置
するために貼着した両面接着絶縁テープは、局部的な剥
れや接着不良を全く生じることなく同一水平面状に密着
される。BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, at the time of punching and forming the inner lead and the bus bar of the lead frame, at least one of the intermediate portions is connected by a connecting piece. Therefore, even if the inner lead is thin, Even if -is thin and long, it is not deformed and is formed while maintaining a predetermined flatness. After annealing, the connecting piece in the middle part is removed, and the shape is excellent without twisting or tilting. Thus, the double-sided adhesive insulating tape adhered for mounting the semiconductor chip on the lower surface or the upper surface of the inner lead or the bus bar is adhered in the same horizontal plane without any local peeling or adhesion failure. It
【0007】また、前記インナーリード、バスバ−の少
なくとも一方の中間部を連結片でつないで形成し、焼鈍
した後、前記連結片を打抜いて除去する前に両面接着絶
縁テープを当該インナーリード、バスバ−に貼着し、次
いで連結片を両面接着絶縁テープとともに打抜き除去す
るようにしても、当該両面接着絶縁テープは平坦度のす
ぐれたインナーリード、バスバ−に接着不良部を生じる
ことなく同様に密に貼着される。In addition, after forming an intermediate portion of at least one of the inner lead and the bus bar by connecting with a connecting piece and annealing, the double-sided adhesive insulating tape is attached to the inner lead before punching and removing the connecting piece. Even if it is adhered to a bus bar and then the connecting piece is punched out together with the double-sided adhesive insulating tape, the double-sided adhesive insulating tape can be used in the same manner without causing defective adhesion on the inner leads and the bus bar. It is stuck tightly.
【0008】[0008]
【実施例】図面において、1はインナーリードで多数形
成され、該インナーリード1群の両側にはこの実施例で
は二股になったバスバ−2が前記インナーリード1の先
端部の前方に延在するごとく形成されている。当該バス
バ−2は動作電源用リ−ド、接地電源用リードとして使
用される。前記インナーリード1群とバスバ−2は、半
導体チップ設置領域3を挟んで対向し設けられている。DESCRIPTION OF THE PREFERRED EMBODIMENTS In the drawings, 1 is a large number of inner leads, and a bifurcated bus bar-2 extends in front of the tip of the inner leads 1 on both sides of the inner lead 1 group. It is formed as follows. The bus bar-2 is used as an operation power supply lead and a ground power supply lead. The group of inner leads 1 and the bus bar-2 are provided so as to face each other with the semiconductor chip mounting region 3 interposed therebetween.
【0009】4はアウターリードで前記インナーリード
1及びバスバ−2に連続し、その境界にはタイバ−5が
形成されている。6はサイドレ−ル、7はガイドホ−
ル、8は樹脂封止時のリードフレームと樹脂との熱膨張
差による変形を吸収するスリットである。An outer lead 4 is continuous with the inner lead 1 and the bus bar-2, and a tie bar 5 is formed at the boundary thereof. 6 is a side rail, 7 is a guide wheel
Reference numerals 8 are slits for absorbing the deformation caused by the difference in thermal expansion between the lead frame and the resin when the resin is sealed.
【0010】これらリードパターンは生産性、形状の均
一性及びコスト面からプレス加工により形成されるが、
インナーリード1は細く強度的にも弱くなり途中で変形
し易く、またバスバ−2はそのリ−ド部が長く同様に変
形し易いので、本発明では少なくとも一方の中間部を連
結片9でつないだ状態でプレス加工で形成する。なお、
この実施例ではインナーリード1、バスバ−2とも中間
部に連結片9を設けている。These lead patterns are formed by pressing in view of productivity, shape uniformity and cost.
Since the inner lead 1 is thin and weak in strength and easily deformed on the way, and the bus bar-2 has a long lead portion and is also easily deformed, at least one intermediate portion is connected by the connecting piece 9 in the present invention. It is formed by press working in the state. In addition,
In this embodiment, a connecting piece 9 is provided in the intermediate portion of both the inner lead 1 and the bus bar-2.
【0011】前記インナーリード1に連結片9を設ける
中間部としてはワイヤ−ボンディング部に近い先端より
内側である箇所が好ましい。バスバ−2に設ける連結片
9の中間部としてはインナーリード1先端の前方に延在
した終端に近い側で、対向したバスバ−2aともつなぐ
箇所が好ましい。It is preferable that the intermediate portion where the connecting piece 9 is provided on the inner lead 1 is located inside the tip close to the wire bonding portion. As an intermediate portion of the connecting piece 9 provided on the bus bar-2, a portion connected to the facing bus bar-2a on the side near the terminal end extending forward of the tip of the inner lead 1 is preferable.
【0012】前記連結片9の設置箇所は特定するもので
なく中間部であればインナーリード1やバスバ−2の形
状あるいは長さ等により適宜の箇所にし得る。The location of the connecting piece 9 is not specified, but may be an appropriate location depending on the shape or length of the inner lead 1 or the bus bar-2 in the middle.
【0013】リードパターンの形成では加工残留応力が
生じるので、これを解放あるいは低減せしめるように焼
鈍する。その後に前記インナーリード1及びバスバ−2
の中間部を繋いだ連結片9を打抜き除去する。Since a processing residual stress is generated in the formation of the lead pattern, it is annealed so as to release or reduce the residual stress. After that, the inner lead 1 and the bus bar-2
The connecting piece 9 connecting the intermediate portions of is punched out and removed.
【0014】次いで、一点鎖線で示す半導体チップ設置
領域3に両面接着絶縁テ−プが貼着される。当該両面接
着絶縁テープの貼着は、半導体チップを下面に設置する
場合はインナーリード1及びバスバ−の下面になされ
る。また、上面に設置する際はインナーリード1及びバ
スバ−の上面になされる。Then, a double-sided adhesive insulating tape is attached to the semiconductor chip installation region 3 shown by the one-dot chain line. The double-sided adhesive insulating tape is attached to the lower surface of the inner lead 1 and the bus bar when the semiconductor chip is placed on the lower surface. Further, when it is installed on the upper surface, it is provided on the upper surfaces of the inner lead 1 and the bus bar.
【0015】また、前記連結片9の除去に先立って、図
2に示すように前記半導体チップ設置領域3に両面接着
絶縁テ−プ10を貼着し、その後、連結片9を除去して
もよい。Prior to removing the connecting piece 9, a double-sided adhesive insulating tape 10 is attached to the semiconductor chip installation area 3 as shown in FIG. 2, and then the connecting piece 9 is removed. Good.
【0016】[0016]
【発明の効果】本発明は、前述のように少なくとも一方
のインナーリード、バスバ−は中間部を連結片でつない
だ状態で打抜き形成するので、リ−ドねじれや傾きがな
く平坦度がすぐれ、焼鈍後に両面接着絶縁テ−プをイン
ナーリード、バスバ−の下面あるいは上面に密着度よく
貼着でき、剥れや接着不良は全く生じない。As described above, according to the present invention, since at least one of the inner leads and the bus bar is punched and formed in the state where the intermediate portions are connected by the connecting pieces, there is no lead twist or inclination, and the flatness is excellent. After annealing, the double-sided adhesive insulating tape can be adhered to the lower surface or the upper surface of the inner lead or the bus bar with good adhesion and no peeling or adhesion failure occurs.
【0017】また、前記インナーリード、バスバ−の中
間部を連結片で繋いでいるので、製造工程の途中でリ−
ドが変形するようなことがない。かかることから、本発
明によるリードフレームでは半導体チップがインナーリ
ード、バスバ−の下面あるいは上面に貼着した両面接着
絶縁テ−プを介して搭載され、信頼性の高い半導体装置
を製造できる。Further, since the intermediate portion of the inner lead and the bus bar is connected by the connecting piece, the lead is removed during the manufacturing process.
Do not deform. Therefore, in the lead frame according to the present invention, the semiconductor chip is mounted via the inner lead, the double-sided adhesive insulating tape adhered to the lower surface or the upper surface of the bus bar, and a highly reliable semiconductor device can be manufactured.
【図1】本発明の1実施例におけるリードフレームを示
す図。FIG. 1 is a diagram showing a lead frame according to an embodiment of the present invention.
【図2】本発明の他の実施例におけるリードフレームを
示す図。FIG. 2 is a diagram showing a lead frame according to another embodiment of the present invention.
1 インナーリード 2 バスバ− 3 半導体チップ設置領域 4 アウターリード 5 タイバ− 6 サイドレ−ル 7 ガイドレ−ル 8 スリット 9 連結片 10 両面接着絶縁テープ 1 Inner lead 2 Bus bar 3 Semiconductor chip installation area 4 Outer lead 5 Tie bar 6 Side rail 7 Guide rail 8 Slit 9 Connecting piece 10 Double-sided adhesive insulating tape
Claims (2)
面に半導体チップを設置するリードフレームの製造方法
において、前記インナーリード、バスバ−の少なくとも
一方の中間部を連結片で連結した状態で打抜き形成し、
焼鈍し、前記中間部の連結片を除去することを特徴とす
るリードフレームの製造方法。1. A method of manufacturing a lead frame in which a semiconductor chip is mounted on the lower surface or the upper surface of an inner lead or a bus bar, wherein at least one of the inner lead and the bus bar is punched and formed in a state of being connected by a connecting piece. ,
A method of manufacturing a lead frame, which comprises annealing and removing the connecting piece of the intermediate portion.
面に半導体チップを設置するリードフレームの製造方法
において、前記インナーリード、バスバ−の少なくとも
一方の中間部を連結片で連結した状態で打抜き形成し、
焼鈍し、半導体チップを設置するインナーリード、バス
バ−に両面接着絶縁テ−プを貼着して前記中間部の連結
片を除去することを特徴とするリードフレームの製造方
法。2. A method of manufacturing a lead frame in which a semiconductor chip is mounted on the lower surface or the upper surface of an inner lead or a bus bar, in which at least one intermediate portion of the inner lead and the bus bar is punched and formed in a state of being connected by a connecting piece. ,
A method for manufacturing a lead frame, which comprises annealing, and attaching a double-sided adhesive insulating tape to an inner lead and a bus bar on which a semiconductor chip is installed to remove the connecting piece of the intermediate portion.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3000896A JP3094271B2 (en) | 1996-01-23 | 1996-01-23 | Lead frame manufacturing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3000896A JP3094271B2 (en) | 1996-01-23 | 1996-01-23 | Lead frame manufacturing method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09205173A true JPH09205173A (en) | 1997-08-05 |
JP3094271B2 JP3094271B2 (en) | 2000-10-03 |
Family
ID=12291858
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3000896A Expired - Fee Related JP3094271B2 (en) | 1996-01-23 | 1996-01-23 | Lead frame manufacturing method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3094271B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006203039A (en) * | 2005-01-21 | 2006-08-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
-
1996
- 1996-01-23 JP JP3000896A patent/JP3094271B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006203039A (en) * | 2005-01-21 | 2006-08-03 | Matsushita Electric Ind Co Ltd | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
JP3094271B2 (en) | 2000-10-03 |
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