JP2009290302A - A/d converting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an A/D converting circuit capable of selecting improvement in resolution or suppression of increase in power consumption, as the need arises. <P>SOLUTION: Each of inverse gates F and R is arranged in the shape of a square matrix and each inverse gate R in the column direction is connected in the shape of a ring to configure pulse circulating circuits OC1-OC7 for each column. Each terminal of the inverse gate R is connected mutually in the row direction by the inverse gate F of the row direction, and an output terminal of inverse gates F11-F71 located at the last stage in each row is connected to an input terminal of inverse gates R72-R77 located at the next stage of the corresponding column to configure a pulse circulating circuit 2. When an analog voltage signal Vin is impressed on a voltage signal input terminal for analog-to-digital conversion, the inverse gates for causing a pulse signal to circulate at the pulse circulating circuit 2 are switched between seven gates of a single column and all of 49 gates. Thereby, resolution of data obtained by an encoder portion 6 is changed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an A / D conversion circuit that converts an analog voltage signal into binary digital data.

  In Patent Document 1, a pulse circuit (ring delay line or ring oscillator) is configured by connecting an odd number of logic inversion gates such as inverter gates in a ring shape, and the power supply voltage of these logic inversion gates is A / As an analog voltage to be D-converted, the number of times the pulse signal circulates in the pulse circuit is counted during a predetermined A / D conversion time, and the position where the edge of the pulse signal has reached in the pulse circuit is determined. An A / D conversion circuit configured to obtain A / D conversion data of an input analog voltage by encoding is disclosed.

  Since the resolution of the A / D conversion circuit configured as described above is determined by the phase difference generated inside the pulse circuit, the smaller the phase difference, the higher the resolution, and the phase difference constitutes the pulse circuit. This is determined by the delay time for one stage of the logic inversion gate. The delay time of the logic inversion gate is determined by the manufacturing process of the semiconductor integrated circuit, and generally becomes shorter as the process becomes finer. Therefore, the improvement limit of the A / D conversion resolution is defined by the manufacturing process.

Patent Document 2 discloses an oscillation device developed in a matrix form by arranging logic inversion gates constituting the above-described pulse circulation circuit in a matrix. Therefore, if the oscillation device of Patent Document 2 is applied to the A / D conversion circuit of Patent Document 1, it is assumed that the A / D conversion resolution can be further improved beyond the limit specified in the manufacturing process.
JP-A-5-259907 JP 2006-114969 A

However, the pulse circuit configured as in Patent Document 2 consumes a large amount of power because a large number of logic inversion gates operate simultaneously to generate an oscillation output, and the A / D converter circuit is configured using the pulse circuit. In this case, the problem is that the power consumption increases.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an A / D conversion circuit capable of selecting resolution improvement and power consumption increase suppression as necessary.

  According to the A / D conversion circuit according to claim 1, the inversion gates are arranged in an n-order (n is an odd number of 3 or more) square matrix, the inversion gates in the column direction are connected in a ring shape, and the Each terminal of the inverting gate is connected in the row direction by the inverting gate in the row direction, and the output terminal of the inverting gate located at the last stage of each row is connected to the input terminal of the inverting gate located at the next stage of the corresponding column. Configure a pulse circuit. Then, the inversion gates in the row direction are connected in a ring shape as a whole. Data obtained by applying an analog voltage signal to the voltage signal input terminal connected to the power supply terminal of each inverting gate and counting the number of laps of the pulse signal in the column direction of the pulse circulator circuit for a predetermined A / D conversion time The data corresponding to the circulating position of the pulse signal in the pulse circulating circuit is used as the A / D conversion result of the analog voltage signal.

  In this case, the delay time (inversion operation time) of the inversion gate arranged in the column direction is set to be n times the delay time of the inversion gate arranged in the row direction. Then, the control means switches the inversion gate that circulates the pulse signal in the pulse circulation circuit between only n rows (n × n) or all of the inversion gates by the circulation position detection means. Change the resolution of the obtained data. Therefore, if you want to improve the A / D conversion resolution, select all of the pulse circuit to operate, and if high resolution is not required, select only one column to operate the pulse circuit to reduce power consumption. can do.

  According to the A / D conversion circuit of the second aspect, the control means switches the order of the square matrix arrangement in the pulse circuit in odd units via the order switching means. Therefore, for example, by switching the order n to 3, 5, 7, 9,..., The number of inversion gates to be operated can be switched to change the A / D conversion resolution in more detail. However, in this case, it is necessary to change the weighting of the pulse circulation number data counted by the counter and the data obtained by the circulation position detection means.

  According to the A / D conversion circuit of the third aspect, the order switching means is constituted by a combination of a plurality of NAND gates and NOR gates, and the control means gives a switching control signal to the NAND gates to provide the A / D conversion circuit. Change the D conversion resolution. That is, if one of the input terminals of the NAND gate is connected to the intermediate stage in the pulse circuit, whether or not the pulse signal can be output can be controlled by the other input terminal. If the output signals from the plurality of NAND gates are given to the first stage of the pulse circuit through the NOR gates, the order of the pulse circuit can be changed. In this case, two stages of the NAND gate and NOR gate constituting the order switching means constitute a part of the pulse circuit.

(First embodiment)
A first embodiment of the present invention will be described below with reference to FIGS. The pulse phase difference encoding circuit 1 includes a pulse circulation circuit 2, a counter 3, a latch circuit 4, a pulse selector unit (circulation position detection unit) 5, an encoder unit (circulation position detection unit) 6, a data selector 7, and a signal processing circuit 8. It consists of

  The pulse circuit 2 is configured in an n (= 7) order square matrix type based on the oscillation device disclosed in Patent Document 2, and 7 × 7 = 49 inversion gates R11 to R17, R21 to R27. , R31 to R37, R41 to R47, R51 to R57, R61 to R67, R71 to R77, F11 to F17, F21 to F27, F31 to F37, F41 to F47, F51 to F57, F61 to F67, F71 to F77 Has been. In FIG. 1, reference numerals are omitted for the gates arranged in the intermediate portion in order to avoid the complicated illustration (see FIG. 1 of Patent Document 1 for details).

  However, in this embodiment, unlike FIG. 1 of Patent Document 1, the gates R11, R21, R31, R41, R51, R61, R71 and the gates F11, F21, F31, F41, F51, F61, F71 are NAND gates. It consists of All other gates are inverter gates. Each of the inversion gates R and F is arranged in a matrix of seven in the row direction and the column direction, and the gates F11 to F77 arranged in the row direction and the gates R11 to R77 arranged in the column direction are: Each is composed of CMOS gates having the same structure. That is, the delay time Tr of the inverting gates R arranged in the column direction is set to be seven times the delay time Tf of the inverting gates F arranged in the row direction (Tr = 7 × Tf).

Seven gates R11 to R77 arranged in the column direction are connected in a ring shape (seven in series) to form a seven-stage pulse circuit OC1 to OC7, and each gate of each pulse circuit OC1 to OC7 The terminals are connected by gates F12 to F17, F22 to F27, F32 to F37, F42 to F47, F52 to F57, F62 to F67, and F72 to F77.
The input terminals of the gates R11 to R17 at each stage of the pulse circuit OC1 and the input terminals of the gates R72 to R77 and R71 at the next stage of the pulse circuit OC7 are the gates F11, F21, and F31. , F41, F51, F61, and F71.

  For example, the first stage in the pulse circuit OC1: the input terminal of the gate R11 and the second stage (next stage of the first stage) in the pulse circuit OC7: the input terminal of the gate R72 are connected by the NAND gate F11. The seventh stage in the pulse circuit OC1: the input terminal of the gate R17 and the first stage (next stage of the seventh stage) in the pulse circuit OC7: the input terminal of the gate R71 are connected by a NAND gate F71. The output terminal of the gate F71 is connected to the input terminal of the gate F17 via a terminal between the gates R77 and R71 of the pulse circuit OC7, and each of the gates F11 to F77 has a single ring shape. Are connected (in series).

That is, the pulse circuit 2 includes inversion gates F and R arranged in a matrix of seven in the row direction and the column direction, and gates R11 to R77 arranged in the column direction are connected in a ring shape, respectively. A seven-stage pulse circuit OC1 to OC7 is configured for each column. Further, the terminals between the gates R of each stage of each of the pulse circulation circuits OC1 to OC7 are connected by the gates F arranged in the row direction, and the gates F11 to F77 arranged in the row direction are connected in a ring shape. As a whole, the pulse circuit 2 is configured.
Further, although not shown in the drawing because the drawing is complicated, the power supply terminals of these 49 gates are collectively connected to a voltage signal input terminal to which an analog voltage Vin to be A / D converted is applied. The analog voltage Vin is supplied as an operating power source for each gate.

  Then, one input terminal of the NAND gate R71 of the pulse circuit 2 and the other NAND gates R11, R21, R31, R41, R51, R61, F11, F21, F31, F41, F51, F61, and F71 is controlled. Signals PAL and PAH are output from the circuit (control means) 9 to start the oscillation operation (circulation operation of the pulse signal). That is, when only the signal PAL is output, only the pulse circuit OC7 oscillates, and when both the signals PAL and PAH are output, the entire pulse circuit 2 oscillates.

  The counter 3 counts the number of circulations of the pulse signal transmitted in a ring shape in the pulse circuit 2, and the count data is latched by the latch circuit 4 when the signal PB is output by the control circuit 9. That is, the time from when the signal PA is output until the signal PB is output is the A / D conversion time.

  The pulse selector unit 5 generates a signal indicating the position of the pulse signal that circulates in the pulse circuit 2. Therefore, the lattice points of 49 gates constituting the pulse circuit 2 are connected to the input terminal of the pulse selector unit 5. The encoder unit 6 generates digital data corresponding to the output signal from the pulse selector unit 5. Note that the pulse selector unit 5 and the encoder unit 6 are each provided with two selectors and two encoders, as will be described later, in order to cope with switching of the A / D conversion resolution. Then, the data selector 7 selects one of the two systems of data output from the encoder unit 6 based on the signal PAH output from the control circuit 9 and outputs the selected data to the signal processing circuit 8.

  The signal processing circuit 8 synthesizes the digital data from the latch circuit 4 and the digital data from the encoder unit 6 to thereby obtain a phase difference (A / D conversion time) between the pulse signals PA and PB output from the control circuit 9. Binary digital data of the voltage signal Vin converted according to the above is generated and output. In this case, the signal processing circuit 8 aligns the output data of the latch circuit 4 with LSB justification with respect to the data concatenated with the data from the latch circuit 4 as the upper bit side and the data from the encoder 6 as the lower bit side. Subtract. The pulse phase difference encoding circuit 1 and the control circuit 9 constitute an A / D conversion circuit 10.

  FIG. 2 shows the internal configuration of the pulse selector unit 5 and the encoder unit 6. All the 49 lattice points constituting the pulse circuit 2 are connected to the input terminal of the pulse selector 5H. The encoder 6H encodes data indicating which of the 49 lattice points the pulse position (the edge of the pulse signal) has reached. On the other hand, the input terminal of the pulse selector 5L is connected to only seven points that connect the terminals of the gates R71 to R77 constituting the pulse circuit OC7. The encoder 6L has a pulse position of the seven points. Encode the data indicating which is reached. The data selector 7 selects the encoder 6H side when the signal PAH is active, and selects the encoder 6L side when the signal PAH is inactive.

  Next, the operation of this embodiment will be described. When performing A / D conversion with high resolution, the control circuit 9 activates the signals PAH and PAL simultaneously (high), activates the signal PB after a predetermined A / D conversion time, and inputs a voltage signal. The analog voltage Vin applied to the terminal is A / D converted. In this case, since the entire pulse circulation circuit 2 operates, the A / D conversion resolution corresponds to T / 49, where T is one period of the pulse circulation. That is, while the signal applied to the input terminal of the gate R71 is inverted and transmitted to the output terminal, the signal is transmitted to the gates F17 to F11 in the row direction and simultaneously the output terminal of the gate R71, It reaches the input terminal of the gate R72 and the input terminal of the gate F27.

  Further, when high resolution is not required for A / D conversion, the control circuit 9 activates only the signal PAL, and activates the signal PB after the A / D conversion time has elapsed to A / D convert the analog voltage Vin. In this case, since only one pulse circuit OC7 operates in the pulse circuit 2, the A / D conversion resolution corresponds to T / 7.

As described above, according to the present embodiment, the inversion gates F and R are arranged in a square matrix, and the inversion gates R in the column direction are connected in a ring shape to form the pulse circuit OC1 to OC7 for each column. Then, the terminals of the inverting gate R are connected in the row direction by the inverting gate F in the row direction, and the output terminals of the inverting gates F11 to F71 located at the last stage of each row are inverted gates located at the next stage of the corresponding column. The pulse circuit 2 is configured by connecting to the input terminals of R72 to R77.
When the analog voltage signal Vin is applied to the voltage signal input terminal and A / D conversion is performed, only one column of the inverting gate that circulates the pulse signal in the pulse circuit 2 is provided, that is, only the pulse circuit OC7. The resolution of data obtained by the pulse selector unit 5 and the encoder unit 6 is changed by switching between all 49 units, that is, the entire pulse circuit 2. Therefore, when it is desired to improve the A / D conversion resolution, all the pulse circuit 2 is operated, and when high resolution is unnecessary, the pulse circuit 2 is operated only for one column to suppress power consumption. Can be selected.

(Second embodiment)
FIG. 3 shows a second embodiment of the present invention. The same parts as those of the first embodiment are denoted by the same reference numerals, the description thereof is omitted, and different parts will be described below. FIG. 3 is a partial equivalent diagram of FIG. The A / D conversion circuit 11 according to the second embodiment can dynamically change the number of inversion gates connected in a ring shape (corresponding to the order n of the square matrix) in the pulse circuit 12 in odd units. It is composed.

  FIG. 3 shows only OC7 that is one column of the pulse circuit 12, but the pulse circuit OC7 includes an order composed of three NAND gates R7A, R7B, and R7C and one NOR gate R7D. A switching circuit (order switching means) 13 (R7) is added. One input terminal of each of the NAND gates R7A, R7B, and R7C is connected to the output terminal of each of the NAND gate R71 and the inverter gates R73 and R75. Further, the inverter gates R76 and R77 are omitted.

  The output terminals of the NAND gates R7A, R7B, and R7C are connected to the input terminals of the 3-input NOR gate R7D, respectively, and the output terminals of the NOR gate R7D are connected to the input terminals of the NAND gate R71 and the inverter gate F17. Yes. The order switching signals ENB_ × 3, ENB_ × 5, and ENB_ × 7 are given to the other input terminals of the NAND gates R7A, R7B, and R7C by the control circuit 9 (not shown in FIG. 3). Although not specifically shown, order switching circuits 13 (R1 to R6, F1 to F7) configured in the same manner are added to the pulse circuit in each column and each row.

  Corresponding to the above order switching, the pulse selector unit and the encoder unit are also provided with individual pulse selectors and encoders, and the selection switching is performed in the data selector by the order switching signal ENB. Yes. In this case, the two stages of the NAND gates 7RA to 7RC and the NOR gate 7RD of the order switching circuit 13 constitute a part of the pulse circuit 12.

Next, the operation of the second embodiment will be described. The control circuit 9 sets the order switching signals ENB_ × 3, ENB_ × 5, ENB_ × 7 according to which of 3, 5, and 7 the number of stages of the pulse circuit 13 for performing A / D conversion is set. Only one of them is active (high). Similarly to the first embodiment, the signals PAH and PAL are activated to perform A / D conversion according to the required A / D conversion resolution.
For example, when the number of stages of the pulse circuit 12 is set to “3”, the order switching signal ENB_ × 3 is made active. Then, in the pulse circulator circuit OC7, since the pulse signal circulates through the paths of the gates R71, R7A, R7D, it is determined whether to operate in a 3 × 3 matrix type by switching the resolution or to operate only for three columns. You can choose.

  Further, when the number of stages is “7”, if the order switching signal ENB_ × 7 is activated, the pulse circuit circulates along the path of the gates R71 to R75, R7C, and R7D in the pulse circuit OC7. Therefore, as in the first embodiment, it is possible to select whether to operate in a 7 × 7 matrix type or to operate in only one column according to switching of resolution. However, in this case, it is necessary to change the weighting for the data of the number of pulse laps counted by the counter 3 and the pulse position data obtained by the encoder unit.

  As described above, according to the second embodiment, the control circuit 9 switches the order of the square matrix arrangement in the pulse circuit 12 through the order switching circuit 13 in odd units, so that the A / D conversion resolution is more detailed. Can be changed. Then, the order switching circuit 13 is composed of a combination of NAND gates 7RA to 7RC and NOR gate 7RD, and the control circuit 9 gives an order switching signal to the NAND gates 7RA to 7RC to change the A / D conversion resolution. Therefore, the output signal from the NAND gates 7RA to 7RC is given to the first stage of the pulse circuit OC7 via the NOR gate 7RD, and the order of the pulse circuit 12 can be changed.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The number n of gate stages of the pulse circuit is an example, and if it is an odd number of 3 or more, it may be changed as appropriate.
Instead of providing the data selector 7, the signal selection logic and the encoding logic itself may be changed by giving the signal PAH to the pulse selector unit and the encoder unit.

1 is a diagram illustrating a configuration of an A / D conversion circuit according to a first embodiment of the present invention. The figure which shows the internal structure of a pulse selector part and an encoder part FIG. 1 is a partial equivalent diagram of FIG. 1 showing a second embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a pulse phase difference encoding circuit, 2 is a pulse circulation circuit, 3 is a counter, 4 is a latch circuit, 5 is a pulse selector section (circulation position detection means), 6 is an encoder section (circulation position detection means), 9 is a control circuit (control means), 10 and 11 are A / D conversion circuits, 12 is a pulse circuit, 13 is an order switching circuit (order switching means), R7A, R7B and R7C are NAND gates, and R7D is a NOR gate. Indicates.

Claims (3)

An A / D conversion circuit for converting an analog voltage signal into binary digital data,
The inversion gates that invert the input signal and output and change the inversion operation time according to the power supply voltage are arranged in an n-order (n is an odd number of 3 or more) square matrix, and the inversion gates in the column direction ring for each column. Inverted gates connected to each other in the row and connected in the row direction by the inverted gates in the row direction, and the output terminal of the inverted gate located at the last stage of each row is located at the next stage of the corresponding column A pulse circuit configured to be connected to the input terminal of
A voltage signal input terminal to which the voltage signal is applied, connected to a power supply terminal of each inversion gate;
A counter that counts the number of times the pulse signal circulates the pulse circuit, and outputs the count result as digital data;
A circulating position detecting means for detecting a circulating position of the pulse signal in the pulse circulating circuit based on an output signal from the inversion gate, and generating digital data corresponding to the circulating position;
When a predetermined A / D conversion time has elapsed from the time when the pulse circulation operation of the pulse circulation circuit is started, the digital data counted by the counter is the upper bit, and the digital data generated by the circulation position detection means And a control means for outputting an A / D conversion result having a lower bit as
The control means switches whether the number of inversion gates that circulate a pulse signal in the pulse circuit is only for one row of n or all of (n × n), and the circuit position detection means An A / D conversion circuit characterized by changing the resolution of the obtained data. Order switching means for switching the order of the square matrix arrangement in the pulse circuit in odd units;
2. The A / D conversion circuit according to claim 1, wherein the control means changes the A / D conversion resolution by giving a switching control signal to the order switching means. The order switching means is composed of a combination of a plurality of NAND gates and NOR gates,
3. The A / D conversion circuit according to claim 2, wherein the control means changes the A / D conversion resolution by giving a switching control signal to the NAND gate.

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