JP4706042B2 - Macro cell circuit - Google Patents

Description

  The present invention relates to a macro cell circuit, and relates to a macro cell circuit in which a target circuit can be easily designed and a plurality of functions can be realized.

Conventionally, a pseudo-random number generation circuit has been used for error detection processing and encryption processing in a data transmission apparatus. Patent Document 1 below discloses an example of a pseudo-random number generation circuit used for encryption processing.
JP 11-224183 A

  When the conventional pseudo random number generation circuit as described above is to be implemented as an LSI, it is necessary to design a circuit pattern of the pseudo random number generation circuit by wiring the gate and FF cells in combination, which is troublesome. there were. Further, the designed cell has a single function, and there is a problem that the circuit pattern must be corrected even when a similar function is to be realized.

  An object of the present invention is to solve the above-mentioned problems of the prior art, and to provide a macro cell circuit which can easily design a target circuit and can realize a plurality of functions.

The macro cell circuit of the present invention includes an input logical product gate circuit to which a signal is input from an external input terminal, an exclusive OR gate circuit to which an output of the logical product gate circuit is input, and the exclusive OR gate circuit. A D-type flip-flop circuit having an output as an input; a first output AND gate circuit to which an output of the D-type flip-flop circuit is input and output to a first external output terminal; and the exclusive OR gate circuit And a second output logical product gate circuit that outputs to the second external output terminal.
The macro cell circuit is also characterized in that a function setting signal output from a register circuit that sets the function of each macro cell circuit is input to the other input of the input AND gate circuit. In the macro cell circuit described above, the first output logical product gate circuit is also characterized in that two logical product gate circuits are connected in parallel.

  The signal processing circuit of the present invention has a cell connection circuit in which a plurality of the macro cell circuits are connected in cascade, and a plurality of input terminals connected to the second external output terminals of the respective macro cell circuits of the cell connection circuit. The main features include an exclusive OR gate tree circuit and a register circuit that sets the function of each macro cell circuit by outputting a setting signal to the AND gate circuit.

Further, the signal processing circuit described above is characterized in that two macro cell circuits at the final stage of the cell connection circuit are used and a load driven by the external output terminal of the macro cell at the final stage is shared. Further, the signal processing circuit described above is characterized in that the macro cell circuits are arranged in a lattice shape and cascaded in a W shape.
In the signal processing circuit described above, the function setting signal is set so that the signal processing circuit functions as at least two of a PN generator, a scrambler, and a convolution operation circuit. .

The signal processing circuit in which the macro cell circuits of the present invention are connected in cascade is easy to design because the design is completed simply by arranging a plurality of the same macro cell circuits and performing the desired wiring, and the designed signal processing circuit is Since a plurality of functions can be realized, there is an effect that the necessity of changing the design is reduced.
In addition, by setting a function setting signal that sets a desired function of each macro cell circuit in the register circuit, a plurality of necessary functions such as a PN generator, a scrambler, and a convolution operation circuit can be dynamically switched. Since the circuit can be realized, the circuit scale can be reduced.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

  The macro cell circuit according to the first embodiment of the present invention will be described below. FIG. 1 is a block diagram showing a configuration of a macro cell circuit of the present invention. The macro cell circuit 20 includes an FF (flip flop) 27, and an output of a 3-input EOR (exclusive OR) gate circuit 24 is connected to a D input terminal of the FF 27.

  The three inputs of the EOR gate circuit 24 are connected to the outputs of AND (logical product) gate circuits 21, 22, and 23, respectively, and the inputs of the AND gate circuits 21, 22, and 23 are respectively shown in the figure. Connected to the external connection terminal. The output of the EOR gate circuit 24 is also connected to the AND gate circuit 26, and the other input of the AND gate circuit is connected to the output of the AND gate circuit 25. The output of the AND gate circuit is connected to the external connection terminal OUT_EOR.

  The output terminal Q of the FF 27 is connected to the two AND gate circuits 30 and 31, and the other inputs of the two AND gate circuits 30 and 31 are connected to the AND gates 29 and 28, respectively. The outputs of the two AND gate circuits 30 and 31 are connected to external connection terminals OUT1 and OUT2, respectively. The reset terminal S and the clock terminal CLK of the FF 27 are connected to the external connection terminals ESET and CLK, respectively.

  FIG. 2 is an explanatory diagram showing the function of each terminal of the macro cell circuit of the present invention. The data input terminal IN1 is used, for example, as an input terminal for inputting a signal from the preceding macro cell. The external data input terminal SW_F is used, for example, when inputting a signal from the outside. The GLFSR feedback signal input terminal SW_G is used, for example, to input the output signal of the last macro cell constituting the shift register.

  The data output terminal OUT1 and the data output terminal OUT2 are signal output terminals to the macro cell at the next stage, and the delay of the signal can be reduced by driving the load to be divided by the two terminals. The parity operation circuit output terminal OUT_EOR is used, for example, to output a signal of each stage of the shift register to the parity operation circuit. A clock signal is input from the outside to the clock input terminal CLK. A reset signal is input to the register reset terminal ESET when the system is initialized.

  Configuration signals (configuration defining signals) are input to the six terminals below the data input control terminal CTR_SW_IN1 in FIG. The configuration signal is output from a configuration register, which will be described later, and defines the operation function of the cell. Normally, 1 is input to the output global enable terminal G_EN_OUT.

  FIG. 3 is a block diagram showing a configuration of a signal processing circuit using the macro cell circuit of the present invention. In FIG. 3, a plurality of blocks marked with BCnn (n is a number) are the macro cell circuits 20 shown in FIG. 1, and the names of the input / output terminals of the blocks are described in the upper part of FIG. Note that terminals such as configuration signals are omitted. For example, the data output terminal OUT1 of BC00 is connected to the data input terminal IN1 of BC01, and the parity operation circuit output terminal OUT_EOR of BC00 is connected to the input terminal EORIN0 of the EOR tree circuit 40.

  From BC00 to BC16, the output terminal OUT1 of BCnn is connected to the input terminal IN1 of BC (nn + 1), and a shift register circuit can be configured. The parity operation circuit output terminal OUT_EOR is connected to the input terminal EORINn of the EOR tree circuit 40, respectively. The output terminal PARITY of the EOR tree circuit 40 is connected to the data input terminals IN1 of BC00 and BC17.

  Two cells, BC16A and BC16B, are provided in parallel as the final stage of the shift register. The data output terminal OUT1 of BC15 is connected to IN1 of BC16A, OUT2 is connected to IN1 of BC16B, the data output terminal OUT1 of BC16A is connected to SW_G of BC13 to BC16B, and the data output terminal OUT2 of BC16A is BC09 to BC12 The data output terminal OUT1 of BC16B is connected to SW_G of BC05 to BC08, and the data output terminal OUT2 of BC16B is connected to SW_G of BC00 to BC04, respectively. By providing two BC16A and BC16B in parallel, the load for driving the SW_G terminal of each cell circuit from the last stage of the shift register is halved, and high-speed operation is possible.

  BC17 is a cell used as an output buffer circuit or the like. The output terminal PARITY of the EOR tree circuit 40 is connected to the data input terminal IN1 of BC17, the data output terminal OUT2 of BC16A is connected to SW_G of BC17, and the data output terminal OUT1 is output to the outside.

  FIG. 4 is a circuit diagram showing a configuration of an exclusive OR gate tree circuit of the signal processing circuit of the present invention. The input terminals EORIN1 to EORIN8 are each input to a three-stage EOR gate tree circuit, and the output of the third-stage EOR gate circuit is connected to the external terminal CONV_I and the input terminal of the fourth-stage 3-input EOR gate circuit. ing.

  The input terminals EORIN9 to EORIN16 are each input to a three-stage EOR gate tree circuit, and the output of the third-stage EOR gate circuit is connected to the external terminal CONV_Q and the input terminal of the fourth-stage 3-input EOR gate circuit. It is connected. Further, the input terminal EORIN0 is connected to the input terminal of the fourth-stage 3-input EOR gate circuit, and the output of the 3-input EOR gate circuit is connected to the external terminal PARITY.

  FIG. 5 is a plan view showing the cell arrangement of the signal processing circuit of the present invention. The macro cell circuit (BC00 to BC17) shown in FIG. 1 is a set with the corresponding configuration register circuit 42, and 19 pieces with the W-shaped (Meander shape) are placed side by side so as to be adjacent in the numerical order as shown in the figure. Has been placed. The input / output terminal names of the cells are shown in the lower part of FIG. Although the OUT_EOR terminal of each cell is omitted, each cell is connected to the EOR tree circuit 40.

  The configuration register circuit 42, which is a register circuit that sets the function of each macro cell circuit by outputting a configuration signal (configuration defining signal) to the AND gate circuits 21, 22, 23, 25, 28, 29, In the register circuit, as shown in the figure, all the input terminals of the five configuration register circuits are connected in parallel. The decoder 41 receives an address signal and outputs a write bit position designation signal in the five register circuits 42. A function is set by writing configuration signal data corresponding to each cell to the configuration register circuit from the outside according to the function to be constructed at the time of initial setting.

  Each of the configuration register circuits 42 can also be configured by an 8-bit shift register circuit. In this case, for example, five shift register circuits are connected in series, and the function is set by writing configuration signal data corresponding to each cell to the shift register circuit from the outside according to the function to be constructed at the time of initial setting. To do. The decoder circuit 41 is not necessary, but the total cell area is increased by changing the register to a shift register.

  FIG. 6 is a block diagram showing a functional configuration of the signal processing circuit of the present invention. In this figure, the cells are shown in a simplified manner, but the center circle in the block of cells is the 3-input EOR circuit 24, and the lower part is the output. A square with a number in the block indicates FF27, and the number corresponds to “nn” of BCnn in FIG. BC02 to BC07 are omitted. Although only one BC16 is shown, it is functionally the same as the circuit of FIG. The connection in FIG. 6 shows the connection when all the configuration signals are set to 1.

  FIG. 7 is a block diagram showing connections when a GLFSR (Galoise linear feedback shift register) type PN (pseudo-random number) generator is configured by the signal processing circuit of the present invention. In this case, only BC01 to BC17 are used, and BC00 and EOR gate tree circuit 40 are not used. Of the signals connected from the data output terminal OUT1 of BC16 to the SW_G terminal of each cell, the configuration signal is set so that only the signal of the necessary cell is input to the EOR gate circuit based on the generator polynomial. In BC17, it is set to output the signal of the SW_G terminal.

  FIG. 8 is a block diagram showing connections when a FLFSR (Fibonacci linear feedback shift register) type PN generator is configured by the signal processing circuit of the present invention. In this case, BC00 to BC17 and the EOR gate tree circuit 40 are used. The output signal PARITY of the EOR gate tree circuit 40 is connected to the FF 27 of BC00, and a shift register circuit is configured by BC00 to BC16. Then, a configuration signal is set so that only the OUT_EOR signal of a necessary cell is input to the EOR gate tree circuit 40 based on the generator polynomial. In BC17, it is set to output the signal of the SW_G terminal.

  FIG. 9 is a block diagram showing connections when a scrambler is constituted by the signal processing circuit of the present invention. Input data is input to BC00 and BC17. Then, OUT_EOR output from BC 00 to BC 16 connected in series and constituting the shift register is input to the EOR gate tree circuit 40. The output signal PARITY of the EOR gate tree circuit 40 is input to BC17, and is exclusive ORed with the input signal at BC17.

  FIG. 10 is a block diagram showing connections when a convolution circuit is constituted by the signal processing circuit of the present invention. Input data is input to BC00 and BC09. Then, OUT_EOR output from BC00 to BC08 and BC09 to BC16 that are connected in series and constitute the shift register is input to the EOR gate tree circuit 40. A convolution signal is output from the output signals CONV_I and CONV_Q of the EOR gate tree circuit 40.

  Although the embodiments have been described above, the following modifications may be considered in the present invention. In the embodiment, an example in which a set of macro cells and configuration registers are arranged in a grid is disclosed, but only macro cells may be arranged in a grid and a configuration signal may be supplied from outside the macro cell area.

It is a block diagram which shows the structure of the macrocell circuit of this invention. It is explanatory drawing which shows the function of each terminal of the macrocell circuit of this invention. It is a block diagram which shows the structure of the signal processing circuit which uses the macrocell circuit of this invention. It is a circuit diagram which shows the structure of the exclusive OR gate tree circuit of the signal processing circuit of this invention. It is a top view which shows cell arrangement | positioning of the signal processing circuit of this invention. It is a block diagram which shows the function structure of the signal processing circuit of this invention. It is a block diagram which shows the connection at the time of comprising a GLFSR type | mold PN generator with the signal processing circuit of this invention. It is a block diagram which shows the connection at the time of comprising a FLFSR type PN generator with the signal processing circuit of this invention. It is a block diagram which shows the connection at the time of comprising a scrambler with the signal processing circuit of this invention. It is a block diagram which shows the connection at the time of comprising a convolution circuit with the signal processing circuit of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 20 ... Macrocell circuit 21-23, 25, 26, 28-31 ... AND gate circuit 24 ... EOR gate circuit 27 ... Flip-flop

Claims (7)

An input AND gate circuit to which a signal is input from an external input terminal;
An exclusive OR gate circuit to which the output of the AND gate circuit is input; and
A D-type flip-flop circuit having the output of the exclusive OR gate circuit as an input;
A first output AND gate circuit that receives the output of the D-type flip-flop circuit and outputs the output to a first external output terminal;
A macro cell circuit comprising: a second output logical product gate circuit that receives the output of the exclusive OR gate circuit and outputs the output to a second external output terminal.   2. The macro cell circuit according to claim 1, wherein a function setting signal output from a register circuit for setting a function of each macro cell circuit is input to the other input of the input AND gate circuit.   2. The macro cell circuit according to claim 1, wherein the first output AND gate circuit includes two AND gate circuits connected in parallel. A cell connection circuit in which a plurality of the macro cell circuits according to claim 1 are connected in cascade;
An exclusive OR gate tree circuit having a plurality of input terminals respectively connected to the second external output terminals of the macro cell circuits of the cell connection circuit;
A signal processing circuit comprising: a register circuit that sets a function of each macro cell circuit by outputting a setting signal to the AND gate circuit.   5. The signal processing circuit according to claim 4, wherein two macro cell circuits at the final stage of the cell connection circuit are used, and a load driven by an external output terminal of the macro cell at the final stage is shared.   6. The signal processing circuit according to claim 5, wherein the macro cell circuits are arranged in a lattice shape and cascaded in a W shape. 5. The signal processing circuit according to claim 4, wherein the signal processing circuit functions as at least two of a PN generator, a scrambler, and a convolution operation circuit by setting the function setting signal.

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