JP2009290173A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device such that area of arrangement of an antenna element and a capacitor element is set wide and electrostatic capacity is hard to be formed between the antenna element and the capacitor element. <P>SOLUTION: The semiconductor device 1 has a semiconductor substrate 2 where a semiconductor element 8 is formed. The semiconductor device includes the antenna element 4 receiving or transmitting an electromagnetic wave, and a first capacitor element 28 and a second capacitor element 31 connected to the antenna element 4. The antenna element 4 is formed on the side of a nonactive surface 2b of the semiconductor substrate 2, and the first capacitor element 28 and the second capacitor element 31 are formed on the side of an active surface 2a of the semiconductor substrate 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a semiconductor device, and particularly relates to an arrangement of an antenna element and a capacitor element.

2. Description of the Related Art In recent years, chip size packages have been adopted for semiconductor devices mounted on electronic devices in order to improve portability and functions of various portable electronic devices. Patent Document 1 discloses a semiconductor device used in an electronic device having a function of transmitting and receiving signals between electronic devices using electromagnetic waves. According to this, the semiconductor device includes an induction element (hereinafter referred to as an antenna element) and a capacitance element (hereinafter referred to as a capacitor element), and the antenna element and the capacitor element are selected so as to have an appropriate impedance. Then, by arranging the antenna element and the capacitor element so as to overlap each other, the area where the inductive element can be used and the area where the capacitive element can be used have been increased.

JP 2006-286857 A

When the antenna element and the capacitor element are arranged so as to overlap each other, the antenna element and the capacitor element are separated by arranging an insulating film between the antenna element and the capacitor element. Therefore, there is a possibility that an electrostatic capacity is formed between the antenna element and the capacitor element via the insulating film. This capacitance is an element other than the antenna element and the capacitor element in the designed circuit, and there is a possibility that the impedance differs from an appropriate setting due to this capacitance. Therefore, there has been a demand for a structure in which the area where the antenna element and the capacitor element are arranged can be set wide, and a structure that can make it difficult to form a capacitance between the antenna element and the capacitor element. .

SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A semiconductor device according to this application example is a semiconductor device having a semiconductor substrate on which an active element is formed, and includes an antenna element that receives or transmits electromagnetic waves, and a capacitor element that is connected to the antenna element. The element is formed on one side of the semiconductor substrate, and the capacitor element is formed on the other side of the semiconductor substrate.

According to this semiconductor device, a circuit including an antenna element and a capacitor element is formed, and an active element drives this circuit, so that an electromagnetic wave having a specific frequency can be received or transmitted. Since the antenna element and the capacitor element are arranged on different surfaces of the semiconductor substrate, the area for arranging the antenna element and the capacitor element is wider than when the antenna element and the capacitor element are formed side by side on the same surface. Can be set. A semiconductor substrate is disposed between the antenna element and the capacitor element. Therefore, compared with the case where the antenna element and the capacitor element are formed on the same surface side of the semiconductor substrate, it is possible to make it difficult to form a capacitance between the antenna element and the capacitor element.

[Application Example 2]
In the semiconductor device according to the application example, a plurality of the capacitor elements are formed, at least one of the capacitor elements is arranged in parallel with the antenna element, and at least one of the capacitor elements is connected to the antenna element and the active element It is characterized by being arranged in series with the element.

According to this semiconductor device, it is possible to configure a circuit that resonates with respect to a predetermined frequency by the antenna element and the capacitor element. When this semiconductor device is arranged as a receiving device or a transmitting device, the optimum impedance between the two devices can be set by selecting and arranging the impedance of the circuit in each device. Therefore, since transmission power loss can be reduced, signals can be transmitted and received efficiently.

[Application Example 3]
In the semiconductor device according to the application example, the capacitor element is formed on an active surface side on which the active element is formed.

According to this semiconductor device, the capacitor element is formed on the active surface side. Since at least one of the capacitor elements is connected to the active element, the wiring between the capacitor element and the active element can be shortened. Therefore, since the area occupied by the wiring on the semiconductor substrate can be reduced, the area on the semiconductor substrate can be designed efficiently.

[Application Example 4]
In the semiconductor device according to the application example, the semiconductor device is used by being mounted on a circuit board, and a terminal connected to the circuit board is disposed on the active surface side.

According to this semiconductor device, the terminal is disposed on the active surface side, and this terminal is connected to the circuit board and mounted. At this time, the capacitor element is formed on the active surface side, and the antenna element is disposed on the other surface side with respect to the active surface side. Therefore, since the antenna element is formed on the surface opposite to the circuit board, when two semiconductor devices are used, the antenna element of one semiconductor device and the antenna element of the other semiconductor device are arranged close to each other. Can do.

[Application Example 5]
In the semiconductor device according to the application example described above, a capacitor formation preventing film is disposed between the antenna element and the semiconductor substrate.

According to this semiconductor device, since the antenna element and the semiconductor substrate can be separated by the capacitance formation preventing film, it is difficult to form the capacitance. Therefore, an electric circuit that operates as designed can be obtained.

[Application Example 6]
In the semiconductor device according to the application example, the antenna element is a loop antenna.

According to this semiconductor device, since the antenna element is a loop antenna, a circuit capable of efficiently transmitting a signal can be formed by combining with the capacitor element.
When the antenna element is a spiral coil, an inductive element is required in addition to the antenna element.
In addition to the spiral coil and the capacitor element, it is necessary to form an inductive element on the semiconductor substrate. Therefore, the area occupied by the spiral coil is reduced. As a result, a circuit that can transmit signals more efficiently can be formed by forming a loop antenna when formed on a semiconductor substrate having a predetermined area than when forming a spiral coil.

In the present embodiment, a characteristic semiconductor device of the present invention and an example of manufacturing the semiconductor device will be described with reference to FIGS. In the drawings used for the following description, the scales are different for each layer and each member so that each layer and each member can be recognized on the drawing.

(Semiconductor device)
Hereinafter, embodiments will be described with reference to the drawings. FIG. 1 is a schematic perspective view showing a semiconductor device. FIG. 1A is a view from the antenna element side, and FIG. 1B is a view from the pump side mounted on the substrate. As shown in FIG. 1, the semiconductor device 1 is formed in a plate shape that is long in one direction. The longitudinal direction is taken as the X direction, and the direction perpendicular to the X direction is taken as the Y direction. And
The thickness direction of the semiconductor device 1 is defined as the Z direction. The semiconductor device 1 includes a semiconductor substrate 2 made of silicon or the like. The size of the semiconductor substrate 2 may be designed according to the size of the element to be formed. In this embodiment, for example, the length in the X direction is set to 6 mm and the length in the Y direction is set to 4 mm. A capacitance formation prevention film 3 is disposed on the Z direction side of the semiconductor substrate 2, and the capacitance formation prevention film 3.
An antenna element 4 having a shape lacking a part of a substantially square is formed on the top. When the electromagnetic wave reaches the antenna element 4, the antenna element 4 functions as a loop antenna. The capacitance formation preventing film 3 is disposed between the antenna element 4 and the semiconductor substrate 2 to electrically insulate the antenna element 4 and the semiconductor substrate 2 from each other. The interval is set to a predetermined interval. And it makes it difficult for the antenna element 4 and the semiconductor substrate 2 to function as a capacitance, thereby preventing formation of an undesigned capacitor.

The stress relaxation layer 5 is disposed on the opposite side of the semiconductor substrate 2 from the Z direction, and bumps 6a, 6b, 6c, 6d as substantially hemispherical terminals are disposed at the four corners on the stress relaxation layer 5. Yes. The bumps 6a, 6b, 6c, and 6d are the same bump 6, respectively. As a material for forming the capacitance formation preventing film 3 and the stress relaxation layer 5, a material that is insulative and can be easily formed into a predetermined shape is preferable. Examples of the forming material include polyimide resin, silicon-modified polyimide resin, epoxy resin, silicon-modified epoxy resin, phenolic resin, acrylic resin, benzocyclobutene (BCB), polybenzoxazole (PBO).
An insulating resin material such as PolyBenzOxazole) can be used. Any of these insulating resin materials can be used alone or as a mixture. In this embodiment, for example, a polyimide resin is employed. The thicknesses of the capacitance formation preventing film 3 and the stress relaxation layer 5 can be set in the range of several μm to 20 μm.

A solder resist film 7 is formed on the upper side of the stress relaxation layer 5 at a place other than the place where the bumps 6 are arranged. When the semiconductor device 1 is mounted on a circuit board and used, the semiconductor device 1 can flow current to the circuit board via the bumps 6. An active element (not shown) such as a transistor or a diode is formed on the surface of the semiconductor substrate 2 on which the bumps 6 are disposed, and this surface is referred to as an active surface 2a. The surface opposite to the active surface 2a is a surface on which no active element is formed, and this surface is referred to as an inactive surface 2b.

2A and 2B are schematic plan views showing the configuration of the semiconductor device. 2A is a view from the antenna element side, and FIG. 2B is a view from the pump side mounted on the circuit board. 2C is a schematic cross-sectional view taken along line AA ′ of FIG. 2B, and FIGS. 2B and 2C show a state where the solder resist film 7 is not disposed. As shown in FIG. 2, a semiconductor element 8 as an active element is formed on the active surface 2 a of the semiconductor substrate 2.
The semiconductor element 8 is configured by circuits such as an analog front end and a signal processing circuit. The analog front end includes a capacitor, a resistor, a transistor, and the like, and circuits such as a frequency filter circuit and a matching circuit are arranged on the analog front end. The signal processing circuit is a circuit for processing a signal output from the analog front end.

A passivation film 9 made of silicon oxide, silicon nitride or the like is formed on the active surface 2a. Since the semiconductor substrate 2 is protected by the passivation film 9, the occurrence of current leakage and the erosion of the semiconductor substrate 2 due to oxygen and moisture are prevented. A wiring 10 and a wiring 11 are formed on the passivation film 9 in the X direction of the semiconductor element 8.
The wiring 11 is connected to the semiconductor element 8. A wiring 12 is formed on the passivation film 9 on the side opposite to the X direction of the semiconductor element 8 and in the Y direction, and the wiring 12 is connected to the semiconductor element 8. Similarly, a second lower electrode 14 is formed on the passivation film 9 via the wiring 13 in the direction opposite to the X direction of the semiconductor element 8 and in the direction opposite to the Y direction. Furthermore, a wiring 15 is formed on the side opposite to the X direction of the second lower electrode 14 and on the side opposite to the Y direction.
A wiring 16 is formed on the direction side. Accordingly, the wiring 13, the second lower electrode 14, the wiring 15,
The wiring 16 is electrically connected.

A first lower electrode 18 is formed on the passivation film 9 via the wiring 17 on the side opposite to the X direction of the semiconductor element 8 and between the wiring 12 and the wiring 13. Further, the first lower electrode 1
8 is formed on the side opposite to the X direction, and the wiring 19 is electrically separated from the wiring 12, the wiring 16, and the first lower electrode 18.

Active surface 2a and wirings 10, 11, 12, 13, 15, 16, 17 formed on active surface 2a
, 19, the second lower electrode 14, and the first lower electrode 18, the stress relaxation layer 5 is disposed on the side opposite to the Z direction. The stress relaxation layer 5 is disposed so that both ends of the active surface 2a in the X direction and a part of the wirings 10, 11, 12, 15, 19 are exposed. A slope 5a is formed at the end of the stress relaxation layer 5 in the X direction, and a slope 5b is formed at the end opposite to the X direction.

A wiring 20 is arranged from the wiring 10 to the lower surface 5c of the stress relaxation layer 5 through the inclined surface 5a.
A bump 6a is disposed on the wiring 20 on the lower surface 5c. Similarly, the wiring 11
Wiring 23 is arranged from slope 5a to lower surface 5c of stress relaxation layer 5 through slope 5a. A bump 6b is disposed on the wiring 23 on the lower surface 5c. Further, the wiring 12 and the wiring 1
A wiring 24 and a wiring 25 are arranged from 5 to the lower surface 5c of the stress relaxation layer 5 through the slope 5b. On the lower surface 5c, bumps 6d are arranged on the wiring 24, and bumps 6c are arranged on the wiring 25.

A wiring 26 is arranged from the wiring 19 to the lower surface 5c of the stress relaxation layer 5 through the inclined surface 5b.
A first upper electrode 27 is formed on the lower surface 5c at a location facing the first lower electrode 18, and the first
The upper electrode 27 and the wiring 26 are electrically connected. The first lower electrode 1 across the stress relaxation layer 5
8 and the first upper electrode 27 are arranged to form a first capacitor element 28 as a capacitor element.

A second upper electrode 29 is formed on the lower surface 5 c so as to face the second lower electrode 14, and the second upper electrode 29 and the first upper electrode 27 are electrically connected by the wiring 30. By disposing the second lower electrode 14 and the second upper electrode 29 with the stress relaxation layer 5 interposed therebetween, a second capacitor element 31 as a capacitor element is formed.

In the semiconductor substrate 2 and the capacitor formation preventing film 3, a through electrode 32 is provided at a location facing the wiring 16.
The through electrode 32 is connected to the wiring 16 and one end of the antenna element 4. Similarly, in the semiconductor substrate 2 and the capacitor formation preventing film 3, the through electrode 3 is provided at a location facing the wiring 19.
3 is formed, and the through electrode 33 is connected to the wiring 19 and one end of the antenna element 4.

Wiring 10, 11, 12, 13, 15, 16, 17, 19, 20, 23, 24, 25, 2
6, first lower electrode 18, first upper electrode 27, second lower electrode 14, second upper electrode 29, through electrode 32
, 33 can be formed of a conductive material alone or in the form of a composite material.
As this forming material, copper (Cu), gold (Au), silver (Ag), titanium (Ti), tungsten (W), titanium tungsten (TiW), titanium nitride (TiN), nickel (Ni
), Nickel vanadium (NiV), chromium (Cr), aluminum (Al), palladium (Pd), or the like. Also, the wirings 10, 11, 12, 13, 15, 16,
17, 19, 20, 23, 24, 25, 26, the first lower electrode 18, the first upper electrode 27, the second lower electrode 14, and the second upper electrode 29 have a single-layer structure made of these conductive materials or A multilayer structure may be used. In the present embodiment, for example, the wirings 10, 11, 12, 13, 15, 16
, 17 and 19 are made of aluminum (Al). And wiring 20,
23, 24, 25, 26, the first lower electrode 18, the first upper electrode 27, the second lower electrode 14, the second upper electrode 29, and the through electrodes 32, 33 are made of titanium nitride or titanium tungsten and copper. (Cu) is employed.

FIG. 3A is a circuit diagram of the semiconductor device. As shown in FIG. 3A, the semiconductor device 1 is used by being connected to a driving device 34 as a circuit board. The driving device 34 is connected to the semiconductor element 8 through four paths. One of the paths is a path connected to the semiconductor element 8 from the driving device 34 via the bumps 6 a, the wiring 20, and the wiring 10. In addition, a path connected to the semiconductor element 8 from the driving device 34 via the bump 6b, the wiring 23, and the wiring 11 and a connection from the driving device 34 to the semiconductor element 8 via the bump 6d, the wiring 24, and the wiring 12 are provided. A route is formed. Furthermore, a path connected to the semiconductor element 8 from the driving device 34 via the bump 6c, the wiring 25, and the wirings 15 and 13 is formed. Of the four paths, the path passing through the wiring 10 is a path for supplying power, and the path passing through the wiring 11 and the wiring 12 is used as a path for inputting and outputting signals. A route passing through the wiring 15 is a route used as a ground wire.

The semiconductor element 8 is connected to the first capacitor element 28 via the wiring 17. The first capacitor element 28 includes the first lower electrode 18 and the first upper electrode 27. The first capacitor element 28 is connected in series with the antenna element 4 via the wiring 26, the wiring 19, and the through electrode 33. Further, the first capacitor element 28 is connected to the second capacitor element 3 via the wiring 30.
1 is connected. The second capacitor element 31 is connected to the antenna element 4 through the through electrode 32 and the wiring 16. Therefore, the second capacitor element 31 is connected in parallel with the antenna element 4. Further, the second capacitor element 31 is connected to the ground lines of the wiring 13 and the wiring 15.

The semiconductor device 1 is used as a transmitter or a receiver. For example, when the semiconductor device 1 is used as the transmitter 35, the receiver 36 is provided with a semiconductor device 37 similar to the semiconductor device 1, a drive device 38 as a circuit board for driving the semiconductor device 37, and the like. The semiconductor device 37 includes an antenna element 39, a first capacitor element 40 and a second capacitor element 41 as a capacitor element, and a semiconductor element 42. The circuit configuration of these elements is the same as that of the semiconductor device 1. The antenna element 39 can receive the electromagnetic wave transmitted by the antenna element 4. On the contrary, the antenna element 4 can receive the electromagnetic wave transmitted by the antenna element 39.

FIG. 3B is a graph showing frequency characteristics of transmission power loss. In FIG. 3B, the horizontal axis indicates the frequency 45 of the signal to be transmitted and received, and the frequency 45 increases from the left side to the right side. The vertical axis represents the transmission power loss 46, and the transmission power loss 46 decreases from the lower side toward the upper side. The transmission power loss 46 is a value calculated by calculating the difference in power of the signal received by the receiver from the power of the signal transmitted by the transmitter, and further dividing by the power of the signal transmitted. Indicates the ratio of power lost. And the transmission power loss curve 4
Reference numeral 7 denotes a transmission power loss 46 at each frequency 45. As shown by the transmission power loss curve 47, the low frequency region 45a where the frequency 45 is low is a stable region with a large transmission power loss 46. Then, when the frequency 45 is increased, the first loss changing region 45b changes so that the transmission power loss 46 becomes smaller. In the first loss change region 45b, the transmission power loss 46 decreases as the frequency 45 increases. And the transmission power loss 46 becomes the smallest at the resonance frequency 45c. Furthermore, when the frequency 45 is made higher than the resonance frequency 45c, the second loss change region 4 in which the transmission power loss 46 increases as the frequency 45 increases.
5d. The high frequency region 45e having a frequency 45 higher than that of the second loss changing region 45d is a stable region with a large transmission power loss 46.

That is, the transmission power loss 46 can be reduced by driving the frequency 45 in the vicinity of the resonance frequency 45c. At this time, the impedance between the semiconductor device 1 and the semiconductor device 37 can be optimized. The impedance of the semiconductor device 1 is set by adjusting the inductance value of the antenna element 4 and the capacitance values of the first capacitor element 28 and the second capacitor element 31. Similarly, the impedance of the semiconductor device 37 is set by adjusting the inductance value of the antenna element 39 and the capacitance values of the first capacitor element 40 and the second capacitor element 41. Then, by adjusting the impedance of the semiconductor device 1 and the impedance of the semiconductor device 37, the impedance condition with the smallest transmission power loss 46 can be set.

FIG. 3C is a schematic diagram for explaining the positional relationship between the semiconductor device for transmission and the semiconductor device for reception. As shown in FIG. 3C, the semiconductor device 1 and the semiconductor device 37 are arranged to face each other. The antenna element 4 of the semiconductor device 1 transmits the electromagnetic wave 48, and the antenna element 39 of the semiconductor device 37 receives the electromagnetic wave 48. The antenna element 4 is formed on the surface opposite to the driving device 34 with respect to the semiconductor substrate 2, and the semiconductor device 37 has the same structure. Therefore, the antenna element 4 and the antenna element 39 can be located in close proximity. Since the electromagnetic wave 48 transmitted by the antenna element 4 has a higher magnetic flux density as it is closer to the antenna element 4, the antenna element 39 can receive the electromagnetic wave 48 at a place where the magnetic flux density is higher. Therefore, the semiconductor device 1 and the semiconductor device 37 can efficiently transmit and receive signals by the electromagnetic wave 48.

(Method for manufacturing semiconductor device)
Next, a manufacturing method for manufacturing the above-described semiconductor device 1 will be described with reference to FIGS. FIG. 4 is a flowchart showing a manufacturing process of a semiconductor device, and FIGS. 5 and 6 are schematic diagrams for explaining a manufacturing method of the semiconductor device. In the manufacturing method according to the present embodiment, actually, a plurality of semiconductor devices 1 are collectively formed on the same silicon wafer (silicon substrate), and then diced (cut) by a dicing device to be separated into pieces. In this way, the method for obtaining the semiconductor device 1 is shown, but for the sake of easy understanding, only the manufacturing process of one semiconductor device 1 is shown in a simplified manner.

Step S1 corresponds to a capacitor formation step, and is a step of forming a stress relaxation layer, a capacitor element, and the like on the active surface. Next, the process proceeds to step S2. Step S <b> 2 corresponds to a through electrode forming step, and is a step of forming a through electrode from the active surface to the inactive surface of the semiconductor substrate after forming a capacitance formation preventing film on the inactive surface. Next, the process proceeds to step S3. Step S3
Corresponds to an antenna formation step and is a step of forming an antenna element on the capacitor formation preventing film. Next, the process proceeds to step S4. Step S4 corresponds to a connection element formation step, and is a step of forming bumps on the wiring formed in the stress relaxation layer. This completes the manufacturing process for manufacturing the semiconductor device.

Next, a method for manufacturing a semiconductor device will be described in detail with reference to FIGS. 5 and 6 in association with the steps shown in FIG. FIG. 5A to FIG. 5E are diagrams corresponding to the capacitor forming process in step S1. FIG. 5A is a schematic plan view of the semiconductor substrate viewed from the active surface, and FIG.
b) is a schematic side view of a semiconductor substrate. As shown in FIGS. 5A and 5B, the semiconductor substrate 2 has a passivation film 9 and a semiconductor element 8 formed on the active surface 2a, and further, wirings 10, 11, 12, 13, 15, 16, 17, 19, the second lower electrode 14, and the first lower electrode 18 are formed.

The passivation film 9 is an inorganic insulating film such as silicon oxide or silicon nitride, and is formed using a CVD method (chemical vapor deposition method), vapor deposition, sputtering, or the like. Semiconductor element 8 and wiring 10
, 11, 12, 13, 15, 16, 17, and 19 are formed by a known semiconductor element manufacturing process, and a description thereof is omitted. In forming the second lower electrode 14 and the first lower electrode 18, a titanium tungsten film and a copper film are laminated in this order on the semiconductor substrate 2 on which the passivation film 9 is formed using a sputtering method. Next, a solution containing a resist film material is applied by spin coating, and then solidified by drying. Then, the resist film is patterned by exposing and developing to remove and remove a part of the resist film. Next, the exposed copper film is removed by etching, and the resist film covering the copper film is removed by peeling. As a result, the second lower electrode 14 and the first lower electrode 18 are formed. Further, the second lower electrode 14 and the first lower electrode 18 may be thickened by using an electroplating method.

On the non-active surface 2b side, the semiconductor substrate 2 is attached and supported on a support plate 49 made of a glass plate using an adhesive that can be peeled off by irradiation with ultraviolet light. This support plate 49 is W
This is a part of what is called SS (WaferSupport System), and a predetermined process such as a polishing process, a dry etching process, or a wet etching process is performed on the semiconductor substrate 2 with the semiconductor substrate 2 attached to the support plate 49. It has come to be.
By applying such a low peel force support system to the flow process of a silicon substrate that has already been processed into a thin plate, the stability and certainty of the process can be ensured.

Next, as shown in FIG. 5C, the semiconductor substrate 2 on which the passivation film 9 is formed.
The material solution for the stress relaxation layer 5 is applied by spin coating or the like. Subsequently, the material liquid of the stress relaxation layer 5 is solidified by drying and baking. Next, the slope 5a and the slope 5b are formed in the stress relaxation layer 5 by exposure and development. At this time, the slopes 5a and 5b can be formed by adjusting the exposure conditions for exposure.

Next, as shown in FIG. 5D, wirings 20, 23, 24, 25, 26, and 30, a first upper electrode 27, and a second upper electrode 29 are formed. A titanium tungsten film and a copper film are laminated in this order on the semiconductor substrate 2 on which the stress relaxation layer 5 has been formed by sputtering. Next, a solution containing a resist film material is applied by spin coating, and then dried to solidify the resist film. Then, the resist film is patterned by peeling off and removing a part of the resist film by exposure and development. Next, the exposed copper film is removed by etching, and the resist film covering the copper film is removed by peeling. As a result, the wirings 20 and 2
3, 24, 25, 26, 30 and the first upper electrode 27 and the second upper electrode 29 are formed. further,
Wiring 20, 23, 24, 25, 26, 30, first upper electrode 27, second using electroplating method
The upper electrode 29 may be thickened.

Next, as shown in FIG. 5E, a solder resist film 7 is formed. The material solution of the solder resist film 7 is applied using a spin coat method. Then, patterning is performed by exposure and development. The solder resist film 7 where the bumps 6 are to be arranged is removed by patterning, and the wirings 20, 23, 24, and 25 are exposed.

FIG. 6A and FIG. 6B are diagrams corresponding to the through electrode forming process in step S2. 6A is a schematic plan view of the semiconductor substrate viewed from the inactive surface side, and FIG. 6B is a schematic side view of the semiconductor substrate. As shown in FIGS. 6A and 6B, the support plate 49 is peeled off from the inactive surface 2b side of the semiconductor substrate 2, and the support plate 49 is attached to the surface on which the solder resist film 7 is formed. . Next, after applying the solution containing the material of the capacitance formation prevention film 3 using a spin coat method, the capacitance formation prevention film 3 is solidified by drying.

Next, a mask (not shown) made of a resist film is formed on the capacitor formation preventing film 3. A solution containing a resist film material is applied by spin coating, and then solidified by drying. Then, by performing exposure and development and patterning, the resist film where the through electrodes 32 and 33 are formed is removed. Subsequently, holes 50 and 51 are formed in the semiconductor substrate 2 and the capacitor formation preventing film 3 by using a dry etching method. The hole 50 is a hole for forming the through electrode 32, and the hole 51 is a hole for forming the through electrode 33. The method of forming the holes 50 and 51 is not limited to the dry etching method, and may be performed by a wet etching method, a method of making holes by irradiating laser light, or a combination of these methods. You may select according to the magnitude | size and depth of the holes 50 and 51. FIG.

Next, an insulating film 52 is formed on the inner walls of the holes 50 and 51. Through the insulating film 52, the through electrode 32,
Generation of current leakage from 33 to the semiconductor substrate 2 is prevented. The insulating film 52 is an inorganic insulating film such as silicon oxide or silicon nitride, and is formed using a CVD method, vapor deposition, sputtering, or the like. Note that the insulating film 52 provided in the portions facing the holes 50 and 51 in the wiring 16 and the wiring 19 is removed by dry etching or laser processing. Then, by forming the insulating film 52 only on the side wall of the holes 50 and 51, when the through electrode 32 and the through electrode 33 are formed, the through electrode 32 and the wiring 16 and the through electrode 33 and the wiring are formed. 19 can be connected to each other.

Next, a metal film is formed on the capacitance formation preventing film 3 and on the inner wall of the insulating film 52 by CVD, vapor deposition, sputtering, or the like. In the present embodiment, for example, a titanium nitride film or a titanium tungsten alloy film is formed. Thereafter, a method of forming a metal film by forming a copper film by laminating on this film is adopted. Subsequently, an electroplating process is performed on the capacitance formation preventing film 3 and the inner wall of the insulating film 52. A conductive material for forming the through electrodes 32 and 33 is disposed inside the holes 50 and 51 by the electroplating process. Then, the wiring 16 exposed at the bottom of the hole 50 and the through electrode 32 are electrically connected, and the wiring 19 exposed at the bottom of the hole 51 and the through electrode 33 are electrically connected. Further, the formation method of the through electrodes 32 and 33 is not limited to the above-described electrolytic plating method, and a method of embedding a conductive paste, molten metal, metal wire, or the like may be used. In the present embodiment, the holes 50 and 51 are filled with a conductive material, and the through electrodes 32 and 33 are filled.
The through electrodes 32 and 33 are formed in the thickness direction of the substrate along at least the inner walls of the holes 50 and 51 without being completely filled, and the wiring 16 and the through electrodes 32 are electrically connected. The wiring 19 exposed at the bottom of the hole 51 and the through electrode 33 may be electrically connected.

FIG. 6C and FIG. 6D are diagrams corresponding to the antenna formation process in step S3. FIG. 6C is a schematic plan view of the semiconductor substrate viewed from the inactive surface side, and FIG. 6D is a schematic cross-sectional view of the semiconductor substrate. As shown in FIGS. 6C and 6D, the antenna element 4 is formed on the capacitance formation preventing film 3. First, a titanium tungsten film and a copper film are laminated and formed in this order on the capacitor formation preventing film 3 by sputtering. Next, a solution containing a resist film material is applied by spin coating, and then dried to solidify the resist film. Then, the resist film is patterned by exposing and developing to remove and remove a part of the resist film. Next, the exposed copper film is removed by etching, and the resist film covering the copper film is removed by peeling. As a result, the antenna element 4 is formed. Further, the antenna element 4 may be thickened by using an electroplating method. One end of the antenna element 4 is connected to the through electrode 32 and the other end of the antenna element 4 is connected to the through electrode 33.

FIG. 6E is a diagram corresponding to the connection terminal forming step of step S4. First, the support plate 49
Is peeled off from the inactive surface 2 b of the semiconductor substrate 2. Then, the solder balls made of lead-free solder are transferred onto the wirings 20, 23, 24, and 25 where the solder resist film 7 has been removed to form bumps 6. The bump 6 may be formed by printing a paste made of lead-free solder, a method of forming by solder plating, or the like. With the above steps, the manufacturing process for manufacturing the semiconductor device is completed.

As described above, the present embodiment has the following effects.
(1) According to this embodiment, the antenna element 4 is disposed on the non-active surface 2b side, and the capacitor elements of the first capacitor element 28 and the second capacitor element 31 are disposed on the active surface 2a side. Therefore, compared with the case where the antenna element 4 and the capacitor element are formed side by side on the same surface, the area where the antenna element 4 and the capacitor element are arranged can be set wider. A semiconductor substrate 2 is disposed between the antenna element 4 and the capacitor element. Therefore,
Compared with the case where the antenna element 4 and the capacitor element are formed on the same surface side of the semiconductor substrate 2, it is possible to make it difficult to form a capacitance between the antenna element 4 and the capacitor element.

(2) According to this embodiment, the antenna element 4, the first capacitor element 28, and the second capacitor element 31 can constitute a circuit that resonates at the resonance frequency 45c. And
When the semiconductor device 1 is arranged as a receiving device or a transmitting device, the optimum impedance between the two devices can be set by selecting and arranging the impedance of the circuit in each device. Therefore, signals can be transmitted and received efficiently.

(3) According to the present embodiment, the first capacitor element 28 and the second capacitor element 31 are formed on the active surface 2a. Since the first capacitor element 28 and the second capacitor element 31 are connected to the semiconductor element 8, the first capacitor element 28 and the second capacitor element 31 are compared with the case where the first capacitor element 28 and the second capacitor element 31 are disposed on the non-active surface 2b. 28 and second capacitor element 3
1 can shorten the wiring between the semiconductor element 8. Therefore, since the area occupied by the wiring on the semiconductor substrate can be reduced, the area on the semiconductor substrate can be designed efficiently.

(4) According to the present embodiment, the bumps 6 are arranged on the active surface 2a side, and the bumps 6 are connected to the circuit board and mounted. The antenna element 4 is disposed on the non-active surface 2b. Accordingly, since the antenna element 4 is formed on the surface opposite to the circuit board, when two semiconductor devices 1 are used, the antenna element 4 of one semiconductor device 1 and the antenna element 39 of the other semiconductor device 37 are connected. Can be placed close together.

(5) According to the present embodiment, it is possible to prevent the capacitance formation prevention film 3 from forming a capacitance between the antenna element 4 and the semiconductor substrate 2. Therefore, an electric circuit that operates as designed can be obtained.

(6) According to this embodiment, since the antenna element 4 is a loop antenna, a circuit capable of efficiently transmitting a signal can be formed by combining with the first capacitor element 28 and the second capacitor element 31. . When the antenna element 4 is a spiral coil, an inductive element is required in addition to the antenna element 4, and it is necessary to form the inductive element on the semiconductor substrate in addition to the spiral coil and the capacitor element. Therefore, the area occupied by the spiral coil is reduced. As a result, when the semiconductor substrate 2 having a predetermined area is formed, a circuit capable of transmitting signals more efficiently can be formed when the loop antenna is formed than when the spiral coil is formed.

(7) According to this embodiment, the antenna element 4 is arranged along the outer periphery of the semiconductor substrate 2. Therefore, since the area surrounded by the antenna element 4 can be set wide, the electromagnetic wave 48 can be transmitted and received efficiently.

The present embodiment is not limited to the above-described embodiment, and various changes and improvements can be added. A modification will be described below.
(Modification 1)
In the embodiment described above, the first capacitor element 28 and the second capacitor element 31 are arranged at positions facing the antenna element 4. However, the antenna element 4 is made smaller so that the first capacitor element 28 and the second capacitor element 31 are made smaller. You may arrange | position in the place which does not oppose the antenna element 4. FIG.
FIG. 7A is a schematic plan view showing a modification of the semiconductor device. As shown in FIG. 7A, the semiconductor device 54 includes the semiconductor substrate 2 on which the semiconductor element 8 is formed, and an antenna element 55 is disposed at a location facing the semiconductor element 8. The semiconductor device 54 includes a first capacitor element 56 and a second capacitor element 57 as capacitor elements, and the first capacitor element 56 and the second capacitor element 57 are opposite to a place surrounded by the antenna element 55. Located in different places.

When the antenna element 55 outputs an electromagnetic wave, the electromagnetic wave is formed in the vicinity of the antenna element 55, and the magnetic flux density becomes high at a place surrounded by the antenna element 55. When the electromagnetic wave passes through the first capacitor element 56 or the second capacitor element 57, an eddy current is formed at the electrode of the capacitor element by the electromagnetic wave. And the energy of electromagnetic waves becomes small and the transmission power loss becomes large. In this modification, since the capacitor element is not arranged at a place where the magnetic flux density is high, it is possible to make it difficult to reduce the energy of the electromagnetic wave to be output.

(Modification 2)
In the embodiment, the first capacitor element 28 and the second capacitor element 31 are arranged on the active surface 2a side of the semiconductor substrate 2, and the antenna element 4 is arranged on the non-active surface 2b side. Not limited to this, the antenna element 4 may be disposed on the active surface 2a side. FIG. 7B is a schematic cross-sectional view showing a modification of the semiconductor device. As shown in the semiconductor device 58 of FIG. 7B, a capacitor element 62 is formed by laminating a lower electrode 59, an insulating film 60, and an upper electrode 61 in this order on the inactive surface 2b side of the semiconductor substrate 2. May be. Then, on the active surface 2a side, an insulating film 63 and an antenna element 6 are provided.
4. The stress relaxation layer 65 is laminated and disposed in this order. Furthermore, the wiring 66 may be disposed on the lower surface of the stress relaxation layer 65 and the bump 6 may be disposed on the lower surface of the wiring 66. Also in this case, since the capacitor element 62 and the antenna element 64 are disposed on different surfaces, the area occupied by the antenna element 64 can be set wide. Furthermore, the capacitor element 62 and the antenna element 64
Since the semiconductor substrate 2 is disposed between the capacitor element 62 and the antenna element 64, it is difficult to form a capacitance between the capacitor element 62 and the antenna element 64.

(Modification 3)
In the embodiment, the first capacitor element 28, the second capacitor element 31, and the bump 6 are disposed on the active surface 2a side of the semiconductor substrate 2, and the antenna element 4 is disposed on the non-active surface 2b side. However, the present invention is not limited to this, and the antenna element 4 and the bump 6 may be disposed on the non-active surface 2b side. FIG.
) Is a schematic cross-sectional view showing a modification of the semiconductor device. As shown in the semiconductor device 67 of FIG. 7C, a capacitor element 62 is formed by stacking a lower electrode 59, an insulating film 60, and an upper electrode 61 in this order on the active surface 2a side of the semiconductor substrate 2. Also good. The insulating film 63, the antenna element 64, and the stress relaxation layer 65 are laminated in this order on the non-active surface 2b side. Furthermore, the wiring 66 may be disposed on the lower surface of the stress relaxation layer 65 and the bump 6 may be disposed on the lower surface of the wiring 66. Also in this case, since the capacitor element 62 and the antenna element 64 are disposed on different surfaces, the area occupied by the antenna element 64 can be set wide. Furthermore, since the semiconductor substrate 2 is disposed between the capacitor element 62 and the antenna element 64, it is difficult to form a capacitance between the capacitor element 62 and the antenna element 64.

(Modification 4)
In the embodiment, the antenna element 4 is disposed on the upper surface of the capacitance formation preventing film 3 and the antenna element 4 is exposed. However, a protective film may be disposed to cover the antenna element 4. The protective film may be made of the same material as that of the capacitor formation preventing film 3, and the antenna element 4 can be hardly changed by oxygen and moisture.

(Modification 5)
In the above embodiment, the circuit of the semiconductor device 1 and the circuit of the semiconductor device 37 are the same circuit, but this is not restrictive. Even in the case where the circuit of the semiconductor device 1 is different from the circuit of the semiconductor device 37, an optimum impedance may be set between the circuit of the semiconductor device 1 and the circuit of the semiconductor device 37. Also in this case, transmission power loss can be reduced.

(Modification 6)
In the embodiment, the antenna element 4 is formed in a substantially square shape, but may be formed in a circular shape or a polygonal shape. The shape may function as long as it functions as a loop antenna, and is preferably designed in accordance with the shape of the semiconductor device.

(Modification 7)
In the embodiment, after forming the passivation film 9 on the active surface 2a, the wirings 10, 11, 12, 13, 15, 16, 17, 19 and the second lower electrode 14 are formed on the passivation film 9.
A first lower electrode 18 was formed. Not only this but wiring 10, 11, 12, 13 on the active surface 2a.
, 15, 16, 17, 19, the second lower electrode 14, and the first lower electrode 18 may be formed, and then the passivation film 9 may be disposed. At this time, by patterning the passivation film 9, electrical connection between the wirings to be connected becomes possible.

1 is a schematic perspective view showing a semiconductor device. (A) And (b) is a schematic plan view which shows the structure of a semiconductor device, (c) is a schematic cross section which shows the structure of a semiconductor device. (A) is a circuit diagram of a semiconductor device, (b) is a graph showing frequency characteristics of transmission power loss, and (c) is a diagram for explaining the positional relationship between a semiconductor device for transmission and a semiconductor device for reception. Pattern diagram. 6 is a flowchart showing a manufacturing process of a semiconductor device. The schematic diagram for demonstrating the manufacturing method of a semiconductor device. The schematic diagram for demonstrating the manufacturing method of a semiconductor device. In connection with the modification, (a) is a schematic plan view showing a semiconductor device, and (b) and (c) are schematic cross-sectional views showing the semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,37,54,58,67 ... Semiconductor device, 2a ... Active surface, 2 ... Semiconductor substrate, 3 ... Capacitance formation prevention film, 4, 39, 55, 64 ... Antenna element, 6 ... Bump as terminal, 8 ... Semiconductor element as active element, 28, 40, 56... First capacitor element as capacitor element, 31, 41, 57... Second capacitor element as capacitor element, 34, 38... Drive device as circuit board, 48. Electromagnetic wave, 62 ... capacitor element.

Claims (6)

A semiconductor device having a semiconductor substrate on which an active element is formed,
An antenna element for receiving or transmitting electromagnetic waves;
A capacitor element connected to the antenna element;
The antenna device is formed on one surface side of the semiconductor substrate, and the capacitor element is formed on the other surface side of the semiconductor substrate. The semiconductor device according to claim 1,
A plurality of the capacitor elements are formed,
At least one of the capacitor elements is arranged in parallel with the antenna element;
At least one of the capacitor elements is arranged in series connection between the antenna element and the active element. The semiconductor device according to claim 2,
The semiconductor device according to claim 1, wherein the capacitor element is formed on an active surface side where the active element is formed. The semiconductor device according to claim 3,
The semiconductor device is used by being mounted on a circuit board,
A terminal for connecting to the circuit board is disposed on the active surface side. The semiconductor device according to claim 4,
A semiconductor device, wherein a capacitance formation preventing film is disposed between the antenna element and the semiconductor substrate. The semiconductor device according to claim 5,
The semiconductor device, wherein the antenna element is a loop antenna.

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