JP2009289975A - Semiconductor device, and method for manufacturing thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To process a memory cell having a MONOS type gate electrode and each gate electrode of normal MOS transistors at the same time. <P>SOLUTION: In a gate electrode G in a memory cell region, a gate insulation film 4, a trap film 5, a block film 6 and an electrode film 7 are laminated on a silicon substrate 1. In a gate electrode GP in a peripheral circuit region, a gate insulation film 4, a polycrystalline silicon film 9 and an electrode film 7 are laminated on the silicon substrate 1. In the polycrystalline silicon film 9, a silicon nitride film 10 and a silicon oxide film 11 are formed on a lower layer side and an upper layer side, respectively, without directly contacting each other. In gate collective processing, the silicon oxide film 11 is used as a stopper in etching the electrode film 7, the silicon nitride film 10 is used as a stopper in processing the block film 6, the polycrystalline silicon film 9 is used as a stopper in processing the trap film 5, and thereby the silicon substrate 1 can be prevented from being damaged. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a memory cell employing a MONOS (metal oxide nitride oxide semiconductor) structure and a method for manufacturing the same.

  As a semiconductor device having a memory cell adopting a MONOS structure, for example, there is a NAND flash memory. However, a transistor formed in a peripheral circuit region requires a threshold control or the like, so that a polycrystalline silicon film is interposed through a gate insulating film. It is preferable that a conductive film such as the above is provided (see Patent Document 1).

However, due to the difference in the film stack structure between the memory cell region and the peripheral circuit region, the processing conditions may not match when processing the gate electrodes of both transistors, and the surface of the semiconductor substrate Occurrence of defects such as drowning is expected, making it difficult to process and form all at once. For this reason, in order not to cause problems such as substrate digging, it is necessary to take measures such as processing the gate electrode by separately processing the memory cell region and the peripheral circuit region, which generally increases the cost. There was a problem.
JP 2004-79624 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which gate electrodes can be processed all at once even when the memory cell region and the peripheral circuit region have different film stacking structures. And

A method for manufacturing a semiconductor device according to one embodiment of the present invention includes a gate insulating film forming step of forming a gate insulating film on an upper surface of a semiconductor substrate in which a memory cell region and a peripheral circuit region are set, and the memory cell region of the semiconductor substrate. A gate intermediate film forming step in which a trap insulating film and a block insulating film are stacked on the upper surface of the peripheral circuit region, and a silicon film is formed on the upper surface of the peripheral circuit region via the gate insulating film; Forming an electrode film on the upper surface of the block insulating film and the silicon film; forming an etching mask pattern on the upper surface of the electrode film; and using the mask pattern as a mask, the electrode film and the block insulating film The trap insulating film and the silicon film are etched together to form a gate electrode and a peripheral edge of the memory cell transistor. An etching step for forming a gate electrode of the circuit transistor, and in the step of forming the gate intermediate film, the first insulating film and the second insulating film are separated from each other from the lower layer side in the silicon film. Forming,
In the etching step, a first step of etching the electrode film and the silicon film under the electrode film to expose the block insulating film and the second insulating film, and the block insulating film and the second insulating film Etching the film and the silicon film under the second insulating film to expose the trap film and the first insulating film; and etching the trap insulating film and the first insulating film A third step of exposing the gate insulating film in the memory cell region and the silicon film under the first insulating film; and a fourth step of exposing the gate insulating film in the peripheral circuit region by etching the silicon film. The steps are performed sequentially.

  The semiconductor device of one embodiment of the present invention includes a semiconductor substrate in which a memory cell region and a peripheral circuit region are set, a gate insulating film formed on an upper surface of the semiconductor substrate, and a memory cell region of the semiconductor substrate. The gate electrode of the memory cell transistor having a structure in which a trap film, a block film, and an electrode film are stacked on the gate insulating film, and the gate electrode of the memory cell transistor are collectively processed in the peripheral circuit region of the semiconductor substrate. A polycrystalline silicon film and the electrode film are formed on the gate insulating film, and at least a silicon nitride film and a silicon oxide film are separated from each other from the lower layer side in the polycrystalline silicon film. And a gate electrode of a peripheral circuit transistor that is provided one layer at a time.

  According to the present invention, gate electrodes can be processed in a lump even when the memory cell region and the peripheral circuit region have different film stacking structures.

  Hereinafter, an embodiment in which the present invention is applied to a NAND flash memory device adopting a MONOS structure will be described with reference to FIGS. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1A shows a partial layout pattern of the memory cell region, and FIG. 1B is a plan view showing transistors in the peripheral circuit portion. In FIG. 1A, a plurality of STIs (shallow trench isolation) 2 as element isolation regions are formed at predetermined intervals along the Y direction in FIG. 1 on a silicon substrate 1 as a semiconductor substrate. 3 are formed separately in the X direction in FIG. In addition, word lines WL of the memory cell transistors are formed at predetermined intervals along the X direction in FIG. 1 orthogonal to the active region 3. A selection gate line SGL1 of a pair of selection gate transistors is formed along the X direction in FIG. Bit line contacts CB are formed in the active region 3 between the pair of selection gate lines SGL1. A gate electrode G of the memory cell transistor is formed on the active region 3 intersecting with the word line WL, and a gate electrode SG of the selection gate transistor is formed on the active region 3 intersecting with the selection gate line SGL1.

  In FIG. 1B, the transistor TrP formed in the peripheral circuit portion is provided in a portion where the STI 2 is formed in the silicon substrate 1 so as to leave the active region 3a in a rectangular shape. In the active region 3a, a gate electrode GP is formed across the active region 3a, and source / drain regions formed by diffusing impurities are provided on both sides thereof. Contact plugs (not shown) are formed in the source / drain regions and the gate electrode GP.

  2 (a) and 2 (b) are cross-sectional views taken along section lines AA and BB in FIG. 2A shows a memory cell transistor Trm in the memory cell region centered on the gate electrode G portion in the active region 3, and FIG. 2B shows a transistor TrP in the peripheral circuit portion. A schematic cross-sectional view in the middle of the process shows a stage in the process of forming the gate electrodes G and GP.

As shown in FIGS. 2A and 2B, the gate insulating film 4 is formed on the silicon substrate 1, and the gate electrodes G and GP are formed thereon. The gate electrode G has a configuration in which a trap insulating film 5, a block insulating film 6, and an electrode film 7 are stacked on the gate insulating film 4. In this case, for example, a silicon nitride film (SiN) is used as the trap insulating film 5, and a material made of a metal oxide such as alumina (Al ₂ O ₃ ) is used as the block insulating film 6. . Further, as the electrode film 7, a polycrystalline silicon film is mainly used and a metal layer or a silicide layer is laminated on the lower or upper part.

  Such a structure of the gate electrode G is called a so-called MONOS (metal-oxide-nitride-oxide-semiconductor) structure. A silicon oxide film 8 is embedded between adjacent gate electrodes G so as to insulate and isolate the gates. Source / drain regions 1 a are formed in the surface layer of the silicon substrate 1 on both sides of the gate electrode G.

  On the other hand, the gate electrode GP is formed by laminating a polycrystalline silicon film 9 and an electrode film 7 a made of the same material as the above-described electrode film 7 on the gate insulating film 4. In this case, the polycrystalline silicon film 9 has a film configuration in which a silicon nitride film 10 as a first insulating film is interposed on the lower layer side and a silicon oxide film 11 as a second insulating film is interposed on the upper layer side. ing. The silicon nitride film 10 and the silicon oxide film 11 are provided so as to function as an etching stopper, which will be described later, and are formed to have a thickness more than the minimum necessary for the etching stopper, for example, about 2 nm.

  The silicon nitride film 10 and the silicon oxide film 11 are formed in the polycrystalline silicon film 9 so as to be separated from each other so that the films do not contact each other. A spacer 8 a made of the same material as that of the silicon oxide film 8 is formed on the side wall of the gate electrode GP. In the surface layer of the silicon substrate 1 on both sides of the gate electrode GP, a source / drain region 1b and a high concentration impurity diffusion region 1c for forming an LDD structure are formed.

  Since the above configuration is adopted, the polycrystalline silicon film 9 of the peripheral circuit transistor has an extremely thin silicon nitride film 10 and a silicon oxide film 11 with a film thickness of about 2 nm interposed therebetween while obtaining a manufacturing effect to be described later. By adopting a configuration, it is possible to suppress the increase in the resistance value and prevent the electrical characteristics from being adversely affected.

Next, the manufacturing process of the said structure is demonstrated with reference to FIGS. 3 to 11 are sectional views corresponding to the portions shown in FIGS. 2 (a) and 2 (b), respectively.
First, as shown in FIGS. 3A and 3B, a silicon oxide film is formed over the entire surface of the silicon substrate 1 as a gate insulating film 4. Subsequently, a polycrystalline silicon film 9 is formed on the entire upper surface of the gate insulating film 4, and the polycrystalline silicon film 9 is left in the peripheral circuit portion (see FIG. 3B) by photolithography to leave the other portion ( The polycrystalline silicon film 9 shown in FIG. 3A showing the memory cell region is removed by etching.

At this time, the polycrystalline silicon film 9 is a first insulating film in a state in which nitrogen (N ₂ ) gas is partially introduced at the time of film formation and the polycrystalline silicon film 9 a is interposed above the gate insulating film 4. A silicon nitride film 10 is formed with a film thickness of about 2 nm, and oxygen (O ₂ ) gas is introduced into the upper layer through a polycrystalline silicon film 9b to form a silicon oxide film 11 as a second insulating film. It is formed with a thickness of about 2 nm, and the remaining polycrystalline silicon film 9c is formed thereon. As a result, the polycrystalline silicon film 9 is formed as an internal layer with the silicon nitride film 10 on the lower layer side and the silicon oxide film 11 on the upper layer side separated by the polycrystalline silicon film 9b.

  In the formation of the polycrystalline silicon film 9, the following method can be adopted in addition to the above method. That is, the polycrystalline silicon film 9a is formed to a film thickness for forming the silicon nitride film 10, and in this state, the surface of the polycrystalline silicon film 9a is temporarily nitrided to form the silicon nitride film 10. Thereafter, the polycrystalline silicon film 9b is formed again to a film thickness for forming the silicon oxide film 11, and in this state, the surface of the polycrystalline silicon film 9b is once oxidized to form the silicon oxide film 11. Further, the above structure can be obtained by forming the polycrystalline silicon film 9c to a predetermined thickness. In addition to polycrystalline silicon, amorphous silicon can be used as a material.

Next, as shown in FIGS. 4A and 4B, a silicon nitride film (SiN) is formed as a trap film 5 and an alumina film (Al ₂ O ₃ ) is formed as a block film 6 on the entire surface. . These trap film 5 and block film 6 are for forming the MONOS structure of the memory cell transistor.

  Subsequently, as shown in FIGS. 5A and 5B, a resist 12 is applied so as to cover the upper surface of the block film 6 in the memory cell region by photolithography and to expose the upper surface of the block film 6 in the peripheral circuit region. Pattern. Then, the block film 6 and the trap film 5 in the peripheral circuit region are removed by etching using the resist 12 as a mask. In this case, the etching process may employ a method such as RIE (reactive ion etching) or wet etching.

  Next, after removing the resist, as shown in FIGS. 6A and 6B, a sputtering method or a CVD (chemical vapor deposition) method is performed on the entire upper surface of the silicon substrate 1 on which the gate intermediate film is formed as described above. Thus, the electrode film 7 is formed. As the electrode film 7, for example, a metal film, a polycrystalline silicon film, a polycrystalline silicon film including a silicide layer, a laminated film of these, or the like can be formed.

  Next, as shown in FIGS. 7A and 7B, a resist 13 is applied to the upper surface of the electrode film 7 and patterned by photolithography. In the memory cell region, patterning is performed with a line-and-space pattern so as to form a word line connecting the upper part of the gate electrode G of the memory cell transistor, and in the peripheral circuit region, the gate electrode GP formed independently for each transistor. The resist 13a is patterned so as to have the following shape.

  Subsequently, an etching process is performed by the RIE method using the resists 13 and 13a as masks to form gate electrodes G and GP. In this case, the etching process is performed by changing and controlling the etching conditions for each stage so as to proceed in four stages as follows. However, the etching process is continuously performed while being accommodated in the chamber of the same etching apparatus. is there.

  First, in the first stage, as shown in FIGS. 8A and 8B, an etching process is performed under conditions for etching the electrode film 7. At this time, under the conditions for etching the electrode film 7, in the memory cell region shown in FIG. 8A, when the upper surface of the block film 6 is exposed, the block film 6 serves as a stopper to stop the etching. Further, in the peripheral circuit region shown in FIG. 8B, the polycrystalline silicon film 9c under the electrode film 7 may be etched, and the second insulating film interposed in the polycrystalline silicon film 9 is used. A certain silicon oxide film 11 serves as a stopper to stop etching.

  In the second stage, as shown in FIGS. 9A and 9B, an etching process is performed under conditions for etching the block film 6, that is, the alumina film. At this time, in the memory cell region shown in FIG. 9A, the block film 6 is etched into a pattern using the resist 13 as a mask, and then the etching stops when the trap film 5, that is, the silicon nitride film is exposed. In the peripheral circuit region shown in FIG. 9B, the silicon oxide film 11 is etched, and the polycrystalline silicon 9b under the silicon oxide film 11 is etched, and the etching is performed when the silicon nitride film 10 is exposed. Stop.

  If the polycrystalline silicon film 9b is not reliably etched even if etching is performed under the etching process conditions of the block film 6 in the second stage etching process, when the etching of the block film 6 is completed, By switching to the etching conditions for the crystalline silicon film 9b, the polycrystalline silicon film 9b can be reliably removed so that the silicon nitride film 10 is exposed.

  In the third stage, as shown in FIGS. 10A and 10B, an etching process is performed under conditions for etching the trap film 5, that is, the silicon nitride film. At this time, in the memory cell region shown in FIG. 10A, the trap film 5 is etched into a pattern using the resist 13 as a mask, and then the etching is stopped when the gate insulating film 4 is exposed. Similarly, in the peripheral circuit region shown in FIG. 10B, the etching is stopped when the silicon nitride film 10 as the first insulating film is etched and the polycrystalline silicon film 9a under the silicon nitride film 10 is exposed. .

  In the fourth stage, as shown in FIGS. 11A and 11B, an etching process is performed under conditions for etching the polycrystalline silicon film 9a. At this time, in the memory cell region shown in FIG. 11A, since the gate insulating film 4 is not etched, the state of being not etched is maintained. On the other hand, in the peripheral circuit region shown in FIG. 11B, the etching is stopped when the polycrystalline silicon film 9a is etched and the gate insulating film 4 is exposed.

  When a series of etching processes over the above four steps are completed, the gate electrodes G and GP are collectively processed in the memory cell region and the peripheral circuit region, respectively. At this time, since the polycrystalline silicon film 9 is etched in the final etching process, the gate insulating film 4 can be used as a stopper to prevent the etching from progressing. It is possible to prevent the surface of the material from being dug or damaged. In particular, since the surface of the silicon substrate 1 corresponding to the source / drain regions in the peripheral circuit region can be prevented from being damaged by the etching process in the fourth stage, it is possible to prevent the electrical characteristics from being adversely affected.

  Thereafter, as shown in FIG. 2, impurities are introduced into the surface layer of the silicon substrate 1 in the memory cell region and the peripheral circuit region by ion implantation to form source / drain regions 1a and 1b, respectively. Subsequently, a silicon oxide film 8 is buried between the gate electrodes G in the memory cell region, and the silicon oxide film 8 formed at the same time around the gate electrode GP in the peripheral circuit region is subjected to spacer processing, whereby a spacer 8a is formed. Is formed. Impurities are implanted at a high concentration by ion implantation using this spacer 8a as a mask, and a high concentration impurity region 1c is formed outside the source / drain region 1b in the peripheral circuit region to form an LDD (lightly doped drain) structure. Form. Further, a NAND flash memory device is formed through a wafer post-processing process.

  According to the present embodiment as described above, the configuration of the gate electrode GP of the transistor in the peripheral circuit region is a configuration in which the silicon nitride film 10 and the silicon oxide film 11 are interposed in the polycrystalline silicon film 9. When gate processing is performed on the gate electrode G of the memory cell transistor and the gate electrode GP of the transistor in the peripheral circuit region, the etching process is simultaneously performed without damaging the surface layer portion of the silicon substrate 1 serving as the source / drain region. You can do it. As a result, the etching process can be performed once, the number of photolithography processes can be reduced, and the process can be shortened, and the processing cost can be reduced as a whole.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
The first insulating film and the second insulating film formed in the polycrystalline silicon film are not limited to one layer, and a plurality of layers can be provided. In this case, the resistance to the etching process can be secured while preventing the resistance value in the polycrystalline silicon film from increasing by forming a plurality of layers instead of increasing the film thickness.

  The thickness of the first and second insulating films is preferably about 0.5 to 2.5 nm, more preferably about 1 to 2 nm, and most preferably about 1.5 to 2 nm. Any film thickness that functions as an etching stopper without increasing the resistance value of the polycrystalline silicon film 9 may be used.

As the first insulating film formed in the polycrystalline silicon film, a film made of another material can be used as long as it functions as a stopper under the etching conditions of the block film 6.
As the second insulating film formed in the polycrystalline silicon film, a film made of another material can be used as long as it functions as a stopper under the etching conditions of the electrode film 7 and the polycrystalline silicon film 9, for example, carbon ( C) A film or the like can also be used.

As the block film, a metal oxide film such as alumina is used. Alternatively, a mixed crystal film such as silicon aluminate or a composite film in which a silicon oxide film is laminated on alumina can be used.
In addition, the present invention can be applied to a NOR type flash memory device.

1 is a schematic plan view showing a part (a) of a memory cell region of a NAND flash memory device and a layout pattern (b) of transistors in a peripheral circuit according to a first embodiment of the present invention; (A), (b) is sectional drawing of the part shown by the cutting lines AA and BB in FIG. 1, respectively. Schematic cross-sectional view at one stage of the manufacturing process (Part 1) Schematic cross-sectional view at one stage of the manufacturing process (Part 2) Schematic cross-sectional view at one stage of the manufacturing process (Part 3) Schematic cross-sectional view at one stage of the manufacturing process (Part 4) Schematic cross-sectional view at one stage of the manufacturing process (Part 5) Schematic sectional view at one stage of the manufacturing process (No. 6) Schematic cross-sectional view at one stage of the manufacturing process (Part 7) Schematic cross-sectional view at one stage of the manufacturing process (No. 8) Schematic cross-sectional view at one stage of the manufacturing process (No. 9)

Explanation of symbols

  In the drawings, 1 is a silicon substrate (semiconductor substrate), 2 is STI, 3 and 3a are active regions, 4 is a gate insulating film, 5 is a trap film, 6 is a block film, 7 is an electrode film, and 9 is a polycrystalline silicon film. Reference numeral 10 denotes a silicon nitride film (first insulating film), and 11 denotes a silicon oxide film (second insulating film).

Claims (5)

A gate insulating film forming step of forming a gate insulating film on the upper surface of the semiconductor substrate in which the memory cell region and the peripheral circuit region are set;
A trap insulating film and a block insulating film are stacked on the upper surface of the memory cell region of the semiconductor substrate via the gate insulating film, and a silicon film is formed on the upper surface of the peripheral circuit region via the gate insulating film. A gate intermediate film forming step;
An electrode film forming step of forming an electrode film on the upper surface of the block insulating film and the silicon film;
A mask pattern for etching is formed on the upper surface of the electrode film, and the electrode film, the block insulating film, the trap insulating film, and the silicon film are collectively etched using the mask pattern as a mask to form a memory cell transistor. An etching process for forming a gate electrode and a gate electrode of a peripheral circuit transistor,
In the gate intermediate film forming step, the silicon film is formed in the film by separating the first insulating film and the second insulating film from the lower layer side,
In the etching step,
Etching the electrode film and the silicon film under the electrode film to expose the block insulating film and the second insulating film;
A second step of etching the block insulating film, the second insulating film, and the silicon film under the second insulating film to expose the trap film and the first insulating film;
Etching the trap insulating film and the first insulating film to expose the gate insulating film and the silicon film under the first insulating film in the memory cell region;
A method of manufacturing a semiconductor device, comprising sequentially performing a fourth step of etching the silicon film to expose the gate insulating film in the peripheral circuit region. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first insulating film is a silicon nitride film. In the manufacturing method of the semiconductor device according to claim 1 or 2,
The method for manufacturing a semiconductor device, wherein the second insulating film is a silicon oxide film. In the manufacturing method of the semiconductor device in any one of Claims 1 thru | or 3,
The method for manufacturing a semiconductor device, wherein the first insulating film and the second insulating film are set to have a thickness of 2.5 nm or less. A semiconductor substrate in which a memory cell region and a peripheral circuit region are set, and
A gate insulating film formed on the upper surface of the semiconductor substrate;
A gate electrode of a memory cell transistor formed in the memory cell region of the semiconductor substrate and having a trap film, a block film and an electrode film stacked on the gate insulating film;
The polycrystalline silicon film and the electrode film are formed in the peripheral circuit region of the semiconductor substrate by batch processing with the gate electrode of the memory cell transistor, and the polycrystalline silicon film is laminated on the gate insulating film. A semiconductor device comprising: a gate electrode of a peripheral circuit transistor in which at least one silicon nitride film and silicon oxide film are interposed from each other while being separated from each other in the film.

Images