JP2009283798A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has strong resistance against stress to be added to a lower part of an electrode pad when performing bonding, and facilitates arrangement of wiring. <P>SOLUTION: At least two adjacent corners among four corners of the electrode pad 4 to be formed on a multilayer wiring layer 2 formed on the semiconductor substrate 1 are supported from below by supports 5a, 5b which penetrate the multilayer wiring layer 2 to reach the semiconductor substrate 1, a plurality of beams 6a, 6b, 6c are connected between the supports 5a and 5b, and members 7a, 7b, 7c, 7d are connected between the beams 6a and 6b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a multilayer wiring structure.

  In recent years, in a semiconductor device having a multilayer wiring structure, the wiring interval is narrowed due to the miniaturization of wiring, and signal delay due to parasitic capacitance between wirings has become a problem. Therefore, in order to reduce the parasitic capacitance between wirings, it is known to use a low dielectric constant film such as a hydrocarbon-based or fluorocarbon-based organic insulating film instead of a general silicon oxide film as an interlayer insulating film. . Such a low dielectric constant film generally has a relative dielectric constant of about 2.3 to 2.5, which is about 40 to 50% lower than a general silicon oxide film.

In general, the low dielectric constant film does not necessarily have sufficient adhesion to the wiring, and the moisture resistance is not necessarily sufficiently high. For this reason, a low dielectric constant film is used in the lower layer portion of the multilayer wiring layer where fine wiring is formed, and a general silicon oxide film having excellent adhesion and moisture resistance is used in the upper layer portion where the wiring interval is relatively wide. Often used.
JP 2004-282000 A

By the way, an electrode pad (bonding pad) is formed on the multilayer wiring structure and is electrically connected to any wiring of the multilayer wiring layer.
However, when a wire is bonded to the electrode pad, there is a problem that stress is applied below the electrode pad, causing deformation or disconnection of the wiring.

  In response to the above problems, the present inventors have proposed a semiconductor device that relieves stress under an electrode pad during wire bonding or the like by a structure that reaches the support substrate through the multilayer wiring layer and supports the electrode pad. (Japanese Patent Application No. 2006-999665).

However, when a structure that can sufficiently alleviate the application of stress to the wiring is used, there is a problem that it is difficult to arrange the wiring.
In view of the above points, the present inventors have an object to provide a semiconductor device having high strength and easy wiring arrangement.

  In order to achieve the above object, the following semiconductor device is provided. The semiconductor device includes a substrate, a multilayer wiring layer formed on the substrate, an electrode pad formed on the multilayer wiring layer, and passes through the multilayer wiring layer to reach the substrate. Of the corners, at least two pillars supporting at least two adjacent corners from below, a plurality of beams connected between the pillars, and a member connected between the beams.

  It is possible to provide a semiconductor device having a multi-layered wiring structure that has high strength and easy wiring arrangement.

Hereinafter, the present embodiment will be described in detail with reference to the drawings.
FIG. 1 is a cross-sectional configuration diagram showing a semiconductor device of the present embodiment.
FIG. 2 is a plan view of the semiconductor device of the present embodiment. 2 is a cross-sectional view taken along the line AA in FIG. 2 (however, in FIG. 2, the electrode pad and the underlying interlayer insulating film are not shown).

  The semiconductor device includes a semiconductor substrate 1, a multilayer wiring layer 2 formed on the semiconductor substrate 1, and an electrode pad 4 formed on the multilayer wiring layer 2 via an interlayer insulating film 3. Further, as shown in FIGS. 1 and 2, there are columns 5 a, 5 b, 5 c and 5 d that penetrate the multilayer wiring layer 2 and reach the semiconductor substrate 1 and support the four corners of the electrode pad 4 from below.

Further, beams 6a, 6b, 6c for connecting the columns 5a, 5b and beams 6d for connecting the columns 5a, 5d are provided.
Furthermore, the semiconductor device of the present embodiment includes members 7a, 7b, 7c, and 7d that connect the beams 6a and 6b.

  Thus, in the semiconductor device of the present embodiment, the beams 6a and 6b are supported by the members 7a, 7b, 7c and 7d, and therefore the columns 5a, 5b, 5c and 5d and the beams 6a, 6b, 6c and 6d are supported. The strength can be increased as compared with the case of only the case. In addition, since such a structure is formed only in the lower part around the electrode pad 4, a large space for arranging the wiring can be taken, and the wiring can be easily arranged.

  Further, by making the widths of the members 7a, 7b, 7c, and 7d equal to or less than the width w (see FIG. 2) of the beams 6a, 6b, 6c, and 6d, it is possible to further increase the wiring arrangement possible area. it can.

  In the above, the pillars 5a, 5b, 5c, 5d are formed below the four corners of the electrode pad 4 in order to increase the strength, but at least two adjacent corners of the four corners of the electrode pad 4 are formed. It only has to be supported from below. For example, only the columns 5a and 5b in FIG.

In the above, in order to increase the strength, the three beams 6a, 6b, and 6c are connected between the columns 5a and 5b. However, at least two beams are sufficient.
The details of the semiconductor device of this embodiment will be described below with reference to FIGS.

As shown in FIG. 1, an element isolation region 12 that defines an element formation region 11 is formed in the semiconductor substrate 1. As the semiconductor substrate 1, for example, a silicon substrate is used.
A gate electrode 14 is formed on the element formation region 11 via a gate insulating film 13.

  In the semiconductor substrate 1 on both sides of the gate electrode 14, a low concentration diffusion layer (not shown) that forms a shallow region of the extension source / drain structure is formed. A sidewall insulating film 15 is formed on the side wall portion of the gate electrode 14. In the semiconductor substrate 1 on both sides of the gate electrode 14 on which the sidewall insulating film 15 is formed, a high concentration diffusion layer (not shown) constituting a deep region of the extension source / drain structure is formed. The low concentration diffusion layer and the high concentration diffusion layer constitute a source / drain diffusion layer 16 having an extension source / drain structure.

Thus, a MOSFET (Metal-Oxide Semiconductor Field Effect Transistor) having the gate electrode 14 and the source / drain diffusion layer 16 is formed. An interlayer insulating film 17 made of, for example, a silicon oxide (SiO ₂ ) film is formed on the semiconductor substrate 1 on which such a MOSFET is formed. An interlayer insulating film 18 is formed on the interlayer insulating film 17. A material having a relatively low relative dielectric constant is used for the interlayer insulating film 18. More specifically, for example, a material having a relative dielectric constant smaller than 3.0 is used. Examples of such a material include SiLK (registered trademark), which is an organic insulating material manufactured by Dow Chemical Company. The reason for using a material having a relatively low relative dielectric constant is to realize high-speed operation by reducing the parasitic capacitance between the wirings.

  In the interlayer insulating films 17 and 18, for example, tungsten (W) is buried in contact holes reaching the source / drain diffusion layers 16, thereby forming conductive plugs (not shown).

  In the interlayer insulating film 18, for example, wiring (not shown) made of copper (Cu) is formed. The wiring is electrically connected to the source / drain diffusion layer 16 through a conductive plug embedded in the interlayer insulating films 17 and 18.

  On the interlayer insulating film 18, interlayer insulating films 21, 22, and 23 are sequentially formed. Each interlayer insulating film 21, 22, 23 is formed with a wiring and a conductive plug that electrically connects the wiring to a lower wiring, but is not shown. For the interlayer insulating films 21, 22, and 23, for example, the same material as that of the interlayer insulating film 18 is used.

  In the interlayer insulating film 21 and the interlayer insulating film 23, beams 6a and 6b are formed to connect the columns 5a and 5b. Members 7a, 7b, 7c, and 7d are formed so as to connect the beams 6a and 6b. In the present embodiment, the members 7a, 7b, 7c, and 7d are stacked in a staircase shape so as to partially overlap each other, and are configured to connect the columns 5a and 5b.

Interlayer insulating films 24, 25, and 26 are sequentially stacked on the interlayer insulating film 23, and wirings 24a and 25a (see FIG. 2 for the wiring 26a formed in the interlayer insulating film 26) are shown in each layer. Conductive plugs that are not to be formed are formed. The interlayer insulating film 26 is formed with a beam 6c for connecting the columns 5a and 5b. For example, a silicon oxide film or a silicon oxycarbide (SiOC) film is used for the interlayer insulating films 24, 25, and 26. The interlayer insulating films 24, 25, and 26 made of such materials have a relatively high dielectric constant, but have high adhesion, high moisture resistance, and relatively high mechanical strength.

  An electrode pad 4 is formed on the interlayer insulating film 26 via the interlayer insulating film 3. Conductive plugs (not shown) are formed in the interlayer insulating film 3 and electrically connect the underlying wiring and the electrode pads 4.

  As described above, the beams 6a, 6b and the members 7a, 7b, 7c, 7d are provided in the vicinity of the interlayer insulating films 18, 21, 22, 23 having a relatively low relative dielectric constant and a relatively low mechanical strength. desirable. This is because it is desirable to reinforce the interlayer insulating films 18, 21, 22, and 23. However, members corresponding to the members 7a, 7b, 7c, and 7d may be provided on the interlayer insulating films 24, 25, and 26 made of a material having a relatively high relative dielectric constant to reinforce between the beams 6b and 6c. .

Hereinafter, a method for manufacturing the semiconductor device of the present embodiment will be described.
FIG. 3 is a cross-sectional configuration diagram illustrating a method for manufacturing a semiconductor device according to the present embodiment.
The same components as those in FIGS. 1 and 2 are denoted by the same reference numerals.

  First, as shown in FIG. 3, an element isolation region 12 that defines an element formation region 11 is formed on a semiconductor substrate 1 by, for example, an STI (Shallow Trench Isolation) method. As the semiconductor substrate 1, for example, a silicon substrate is used.

  Next, a gate electrode 14 is formed on the element formation region 11 via a gate insulating film 13. Then, for example, dopant impurities are introduced into the semiconductor substrate 1 on both sides of the gate electrode 14 by ion implantation using the gate electrode 14 as a mask. As a result, a low concentration diffusion layer (not shown) constituting a shallow region of the extension source / drain structure is formed.

  Next, for example, a silicon oxide film (not shown) is formed on the entire surface of the semiconductor substrate 1, and a sidewall insulating film 15 made of a silicon oxide film is formed on the side wall portion of the gate electrode 14 by anisotropic etching. To do. Then, dopant impurities are introduced into the semiconductor substrate 1 on both sides of the gate electrode 14 using the sidewall insulating film 15 as a mask. Thereby, a high concentration diffusion layer (not shown) constituting a deep region of the extension source / drain structure is formed. Thus, the source / drain diffusion layer 16 having the extension source / drain structure is constituted by the low concentration diffusion layer and the high concentration diffusion layer.

  Next, an interlayer insulating film 17 made of, for example, a silicon oxide film is formed on the entire surface of the semiconductor substrate 1 by, for example, a plasma CVD (Chemical Vapor Deposition) method. The film thickness of the interlayer insulating film 17 is not particularly limited, but is preferably about 100 nm to 500 nm in consideration of various physical properties such as dielectric constant, strength, and thermal characteristics.

  Next, an interlayer insulating film 18 is formed on the entire surface of the interlayer insulating film 17 by, eg, spin coating. As the material of the interlayer insulating film 18, a material having a relatively small relative dielectric constant is used. More specifically, a material having a relative dielectric constant smaller than 3.0 (for example, the aforementioned SiLK) is used. The film thickness is not particularly limited, but is preferably about 50 nm to 300 nm in consideration of various physical properties such as dielectric constant, strength, and thermal characteristics.

  Next, contact holes reaching the source / drain diffusion layers 16 are formed in the interlayer insulating films 17 and 18. Then, a barrier film (not shown) made of, for example, tantalum nitride (TaN) with a film thickness of 50 nm is formed on the entire surface of the interlayer insulating film 18 by, eg, sputtering. Next, a conductive film (not shown) made of tungsten having a thickness of 1 μm is formed on the entire surface of the barrier film by, eg, CVD. Thereafter, the conductive film is polished by, for example, CMP (Chemical Mechanical Polishing) until the surface of the interlayer insulating film 18 is exposed. Thus, a conductive plug (not shown) in which the conductive film is embedded in the contact hole is formed.

  Next, SiLK is further formed on the entire surface of the interlayer insulating film 18 by, eg, spin coating, and the interlayer insulating film 18 is stacked thereon. The film thickness at this time is formed under the same conditions as the lower interlayer insulating film 18, for example.

  Next, a trench for wiring is formed in the interlayer insulating film 18 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of the interlayer insulating film 18 by, for example, electroplating. Next, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 18 is exposed. In this way, wiring (not shown) is formed. The wiring is electrically connected to the source / drain diffusion layer 16 through a conductive plug.

Next, the interlayer insulating film 21 is formed on the entire surface of the interlayer insulating film 18 by, eg, spin coating. The interlayer insulating film 21 is formed under the same conditions as when the interlayer insulating film 18 is formed.
4 is a top view of the semiconductor device of FIG. 3 taken along line BB.

  After the interlayer insulating film 21 is formed, a conductive plug groove and a beam groove are simultaneously formed in the interlayer insulating film 21 by using a photolithography technique. Then, a conductive film made of copper (not shown) is formed on the entire surface of interlayer insulating film 18 by, for example, electroplating, and the conductive film is formed by, for example, CMP until the surface of interlayer insulating film 21 is exposed. Grind. Thus, the beams 6a and 6e and the conductive plug 21a as shown in FIG. 4 are formed simultaneously. The beams 6a and 6e and the conductive plug 21a are disposed with a space for a column formed below the four corners of the electrode pad in a later step.

In the case where the electroplating method is used, although not shown, first, a barrier metal and a seed Cu film are formed using a sputtering method. Then, by electroplating on seed Cu film, for example, by adjusting the current density in the range of about ^{1mA / cm 2 ~30mA / cm 2} , to form a conductive film made of copper.

  Next, SiLK is further formed on the entire surface of the interlayer insulating film 21 by, eg, spin coating, and the interlayer insulating film 21 is stacked thereon. The film thickness at this time is formed, for example, under the same conditions as the lower interlayer insulating film 21.

FIG. 5 is a top view of the semiconductor device of FIG. 3 taken along line CC.
After the interlayer insulating film 21 is stacked, a groove for wiring and a groove for a member connecting the beams are simultaneously formed in the interlayer insulating film 21 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of interlayer insulating film 21 by, for example, electroplating under the above-described conditions. Thereafter, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 21 is exposed. Thus, the members 7a and 7e and the wiring 21b as shown in FIG. 5 are formed simultaneously. In addition, the members 7a and 7e and the wiring 21b are arranged with a space for a column formed below the four corners of the electrode pad in a later step.

Next, an interlayer insulating film 22 is formed on the entire surface of the interlayer insulating film 21 under the same conditions as the interlayer insulating film 21, for example, by spin coating.
6 is a top view of the semiconductor device of FIG. 3 taken along the line DD.

  After the interlayer insulating film 22 is formed, a groove for a conductive plug and a groove for a member connecting the beams are simultaneously formed in the interlayer insulating film 22 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of the interlayer insulating film 22 by, for example, electroplating under the above-described conditions. Thereafter, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 22 is exposed. Thus, the members 7b and 7f and the conductive plug 22a as shown in FIG. 6 are formed at the same time. The members 7b and 7f are arranged so as to partially overlap the members 7a and 7e formed in the lower interlayer insulating film 21 as shown in FIG.

  Next, SiLK is further formed on the entire surface of the interlayer insulating film 22 by, eg, spin coating, and the interlayer insulating film 22 is stacked. The film thickness at this time is formed under the same conditions as the lower interlayer insulating film 22, for example.

FIG. 7 is a top view of the semiconductor device of FIG. 3 taken along line EE.
After the interlayer insulating film 22 is stacked, a groove for wiring and a groove for a member connecting the beams are simultaneously formed in the interlayer insulating film 22 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of the interlayer insulating film 22 by, for example, electroplating under the above-described conditions. Thereafter, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 22 is exposed. Thus, the members 7c and 7g and the wiring 22b as shown in FIG. 7 are formed simultaneously. The members 7c and 7g are arranged so as to partially overlap the lower-layer members 7b and 7f as shown in FIG.

Next, an interlayer insulating film 23 is formed on the entire surface of the interlayer insulating film 22 under the same conditions as the interlayer insulating film 22, for example, by spin coating.
FIG. 8 is a top view of the semiconductor device of FIG. 3 taken along line FF.

  After the interlayer insulating film 23 is formed, a groove for a conductive plug and a groove for a member for connecting the beams are simultaneously formed in the interlayer insulating film 23 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of the interlayer insulating film 23 by, for example, electroplating under the above-described conditions. Thereafter, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 23 is exposed. Thus, the members 7d and 7h and the conductive plug 23a as shown in FIG. 8 are formed at the same time. The members 7d and 7h are arranged so as to partially overlap the members 7c and 7g formed on the lower interlayer insulating film 22, and space for columns to be formed below the four corners of the electrode pad in a later process. Place it empty.

  Next, SiLK is further formed on the entire surface of the interlayer insulating film 23 by, eg, spin coating, and the interlayer insulating film 23 is stacked thereon. The film thickness at this time is formed, for example, under the same conditions as the lower interlayer insulating film 23.

FIG. 9 is a top view of the semiconductor device of FIG. 3 taken along line GG.
After the interlayer insulating film 23 is stacked, a wiring groove and a beam groove are simultaneously formed in the interlayer insulating film 23 by using a photolithography technique. Then, a conductive film (not shown) made of copper is formed on the entire surface of the interlayer insulating film 23 by, for example, electroplating under the above-described conditions. Thereafter, the conductive film is polished by, for example, CMP until the surface of the interlayer insulating film 23 is exposed. Thus, the beams 6b and 6f and the wiring 23b as shown in FIG. 9 are formed simultaneously. The beams 6b and 6f and the wiring 23b are arranged with a space for a column to be formed below the four corners of the electrode pad in a later step.

In this manner, a structure in which the beams 6a and 6b as shown in FIG. 3 are connected by the members 7a, 7b, 7c, and 7d arranged in a step shape is obtained.
Thereafter, an interlayer insulating film 24 made of, for example, a silicon oxide film or a silicon oxycarbide film is formed on the entire surface of the interlayer insulating film 23 by, eg, plasma CVD. The film thickness of the interlayer insulating film 24 is not particularly limited, but is preferably about 100 nm to 500 nm in consideration of various physical properties such as dielectric constant, strength, and thermal characteristics.

  Although the interlayer dielectric film 24 made of such a material has a relatively high dielectric constant, it has high adhesion and moisture resistance and relatively high mechanical strength. The upper layer of the multilayer wiring structure has a relatively wide wiring interval, so even if a material with a relatively high relative dielectric constant is used, the parasitic capacitance between the wirings does not become excessively large, and serious signal delay may occur. Absent. Note that when the interlayer insulating film 24 made of a silicon oxide film or a silicon oxycarbide film is formed by plasma CVD, the Young's modulus of the interlayer insulating film 24 is relatively large, about 60 to 70 GPa.

A wiring 24a and a conductive plug (not shown) are also formed on the interlayer insulating film 24 by the same process as described above.
Subsequently, the interlayer insulating film 25 is formed under the same conditions as the interlayer insulating film 24, and the wiring 25a and a conductive plug (not shown) are formed.

  Thereafter, the interlayer insulating film 26 is formed under the same conditions as the interlayer insulating film 24, and the wiring 26a as shown in FIG. 2 and a conductive plug (not shown) are formed. In the interlayer insulating film 26, the beam 6c is formed simultaneously with the wiring 26a, as in the process shown in FIG.

  Thus, no member is connected between the beams 6b and 6c. This is because the interlayer insulating films 24, 25, and 26 are formed using a material having a relatively high mechanical strength. However, members 7a, 7b, 7c and 7d may be formed as between the beams 6a and 6b.

Next, a process of forming the columns 5a, 5b, 5c, 5d as shown in FIGS. 1 and 2 will be described.
FIG. 10A to FIG. 10D are cross-sectional configuration diagrams of the semiconductor device in each process of forming the support column.

  As shown in FIG. 10A, a photoresist film 30 is formed on the entire surface of the interlayer insulating film 26 by spin coating. Next, as shown in FIG. 10-2, using the photolithography technique, openings 31 are formed in the photoresist film 30 at positions corresponding to the four corners of the electrode pad to be formed in a later step. Then, using the photoresist film 30 in which the opening 31 is formed as a mask, the opening 32 reaching the semiconductor substrate 1 is formed in the interlayer insulating films 17, 18, 21, 22, 23, 24, 25, and 26.

  Thereafter, the photoresist film 30 is peeled off, and a conductive film 33 made of, for example, copper is formed on the entire surface of the semiconductor device by, for example, electroplating, as shown in FIG. Next, the conductive film 33 is polished by CMP until the surface of the interlayer insulating film 26 is exposed, so that the pillars 5a and 5b as shown in FIG. 10-4 are formed.

Next, a process for forming the electrode pad 4 will be described.
FIG. 11 is a cross-sectional configuration diagram of the semiconductor device in the step of forming electrode pads.
After forming the pillars 5a and 5b, in order to insulate the electrode pad 4 from the pillars 5a and 5b, the beam 6c, etc., as shown in FIG. 11, silicon oxide is formed on the entire surface of the semiconductor device by, for example, plasma CVD. An interlayer insulating film 3 made of a film or a silicon oxycarbide film is formed. The film thickness of the interlayer insulating film 3 is not particularly limited, but is preferably about 100 nm to 1000 nm in consideration of various physical properties such as dielectric constant, strength, and thermal characteristics.

  Subsequently, a conductive plug (not shown) is formed in the interlayer insulating film 3 for electrical connection with a lower layer wiring using a photolithography technique, a sputtering method, a CVD method, a CMP method, or the like. Thereafter, a conductive film (not shown) is formed on the entire surface of the interlayer insulating film 3 by, for example, sputtering, and patterned to form the electrode pad 4 as shown in FIG.

FIG. 12 is a diagram showing the relationship between the structure embedded in the multilayer wiring layer below the electrode pad and the stress applied to the components below the electrode pad.
The horizontal axis represents the area ratio of the columns 5a, 5b, 5c, 5d (see FIG. 2) with respect to the area of the electrode pad 4. The vertical axis represents the maximum value (maximum stress) of the stress applied to the component existing below the electrode pad 4.

In FIG. 12, a rhombus plot shows the relationship between the maximum stress and the area ratio in the semiconductor device of the present embodiment shown in FIGS.
As a comparative example, the case where one column is embedded in the multilayer wiring layer (Comparative Example 1) is indicated by a circled plot, the case where four columns are provided and no beam is provided (Comparative Example 2) is indicated by a triangular plot, A case where four columns are provided and two beams are provided (Comparative Example 3) is shown by a rectangular plot.

  As shown in the figure, by providing the members 7a, 7b, 7c, and 7d that connect and support the beams 6a and 6b as in the semiconductor device of the present embodiment, than the configurations of Comparative Examples 1 to 3. The stress applied to the components existing below the electrode pad 4 is reduced.

  As described above, according to the semiconductor device of this embodiment, even when pressure is applied from above the electrode pad 4 during bonding or the like, it is possible to suppress a large stress from being applied to the components existing below the electrode pad 4. Can do.

  For this reason, even when an interlayer insulating film having a relatively low mechanical strength is used in a part of the multilayer wiring structure, it is possible to prevent a strong stress from being applied to the components of the semiconductor device, and reliability A semiconductor device with a high level can be provided. Further, as shown in FIG. 1, the members 7 a, 7 b, 7 c, and 7 d are also connected between the columns 5 a and 5 b, so that even when a force from an oblique direction is applied to the electrode pad 4 during bonding, the semiconductor Deformation of the device can be prevented. Thereby, the stress added to components, such as the wiring which exists under the electrode pad 4, can be relieved.

Although the semiconductor device of the present embodiment has been described above, various modifications are possible without being limited to the above description.
For example, in the above description, the case where the members that support the space between the beams are arranged stepwise as shown in FIG. 1 is not limited to this, and may be as follows.

FIG. 13 and FIG. 14 are examples of arrangement of members that support between the beams.
Constituent elements other than the members are the same as those in FIG.
In the example of FIG. 13, members 40 a, 40 b, 40 c, and 40 d are arranged in a wall shape and supported between the beams 6 a and 6 b, and have a structure that is resistant to vertical stress from the electrode pad 4.

  In the example of FIG. 14, members 41a and 41b that connect to the columns 5a and 5b are arranged on the beam 6a, and members 41c, 41d, 41e, and 41f are stacked in a staircase shape from each, and the member 41g is connected to the upper beam 6b. Like to do. As a result, the structure is resistant to both stress from an oblique direction and stress in the vertical direction.

In the above description, the case where the same material is used for the wiring and the beam, the column, and the member connected between the beams has been described as an example. However, a material different from that for the wiring and the beam, the column, or the member may be used.
In the above description, the case where the beams and members are formed by electroplating is described as an example, but the present invention is not limited to this. For example, it may be formed by a CVD method, an electroless plating method, a spin coating method, or the like.

  In the above description, the case where copper is used as the material of the beam, column, or member has been described as an example, but the present invention is not limited to this. For example, a metal such as tungsten, aluminum (Al), or nickel (Ni) may be used, or a nitride such as tantalum nitride may be used. Further, diamond, fullerene, carbon nanotube, or the like may be used.

  In the above description, the case where SiLK is used as the material of the lower interlayer insulating film (interlayer insulating films 18, 21, 22, 23) has been described as an example, but the present invention is not limited to this. For example, an SOG (Spin On Glass) film may be used. Further, a silicon oxycarbide film formed by a CVD method may be used. As a material for such a silicon oxycarbide film, Black Diamond (registered trademark) manufactured by Applied Materials may be used. Further, a low dielectric constant FSG (Fluorinated Silicate Glass) film, MSQ (Methyl Hydrogen Silsesquioxane) film, HSQ (Hydrogen Silsesquioxane) film, FSQ (Fluorinated Hydrogen Silsesquioxane) film, or the like may be used.

Further, as the lower interlayer insulating film, the following film formed by a coating method may be used.
For example, an HSQ film using an insulating film material manufactured by Dow Corning Silicone is used. It is also possible to use a wholly aromatic aryl ether film using ALCAP-E (registered trademark), which is an insulating film material manufactured by Asahi Kasei Corporation. It is also possible to use an aryl ether film using FLARE (registered trademark) which is an insulating film material manufactured by Honeywell. It is also possible to use a benzocyclobutene (BCB) film using an insulating film material manufactured by Dow Chemical Company. It is also possible to use an FSQ film using an insulating film material provided by Fujitsu Limited or Trichemical Co. It is also possible to use an inorganic or organic MSQ film using LKD-T200 (registered trademark), which is an insulating film material made by JSR Corporation. It is also possible to use an inorganic or organic MSQ film using HOSP (registered trademark) which is an insulating film material manufactured by Honeywell. It is also possible to use an inorganic porous HSQ film using porous HSQ which is an insulating film material manufactured by Dow Corning Silicone. It is also possible to use an organic porous aryl ether film using ALS-400 (registered trademark), which is an insulating film material manufactured by Sumitomo Chemical Co., Ltd. It is also possible to use an inorganic or organic SiH-based porous film using IPS (registered trademark) which is an insulating film material manufactured by Catalytic Chemical Co., Ltd. It is also possible to use an inorganic or organic SiOCH (oxidized hydrocarbon silicon) film using Nanoglass-E (registered trademark) which is an insulating film material manufactured by Honeywell. It is also possible to use an inorganic or organic porous MSQ film using LKD-T400 (registered trademark), which is an insulating film material manufactured by JSR Corporation. It is also possible to use an inorganic porous silica film using ALCAP-S (registered trademark), which is an insulating film material manufactured by Asahi Kasei Corporation. It is also possible to use an organic porous aryl ether film using porous SiLK which is an insulating film material manufactured by Dow Chemical. It is also possible to use an organic porous aryl ether film using porous FLARE which is an insulating film material manufactured by Honeywell. In any case, the dielectric constant of the interlayer insulating film formed is 3.0 or less.

  Further, as the lower interlayer insulating film, an inorganic porous silica film using silica aerogel, which is an insulating film material manufactured by Kobe Steel, Ltd. may be formed by high-pressure drying. Also in this case, the relative dielectric constant of the formed interlayer insulating film is 3.0 or less.

Further, as the lower interlayer insulating film, the following film formed by the CVD method may be used.
For example, an interlayer insulating film may be formed by CVD using BCB manufactured by Dow Chemical Co. as a raw material. Alternatively, an interlayer insulating film made of an inorganic or organic SiOCH film may be formed by a CVD method using Black Diamond manufactured by Applied Materials as a raw material. Alternatively, an interlayer insulating film made of an inorganic or organic SiOCH film may be formed by CVD using Coral (registered trademark) manufactured by Novellus Systems. Further, an interlayer insulating film made of an inorganic or organic SiOCH film may be formed by a CVD method using Aurora (registered trademark) manufactured by ASM Co., Ltd. as a raw material. Alternatively, an HOSP manufactured by Honeywell may be used as a raw material to form an interlayer insulating film made of an inorganic or organic MSQ coating film by a CVD method. In any case, the dielectric constant of the interlayer insulating film formed is 3.0 or less.

Regarding the above embodiment, the following additional notes are disclosed.
(Appendix 1) a substrate,
A multilayer wiring layer formed on the substrate;
An electrode pad formed on the multilayer wiring layer;
At least two pillars penetrating the multilayer wiring layer and reaching the substrate, and supporting at least two adjacent corners from below among the four corners of the electrode pad;
A plurality of beams connected between the columns;
Members connected between the beams;
A semiconductor device comprising:

(Additional remark 2) The said member is connected between the said support | pillars while being connected between the said beams, The semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 3) The width | variety of the said member is below the width of the said beam, The semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.

(Additional remark 4) The said member is formed with the same material as the wiring of the said multilayer wiring layer, The semiconductor device as described in any one of Additional remark 1 thru | or 3 characterized by the above-mentioned.
(Supplementary Note 5) The semiconductor device according to any one of Supplementary Notes 1 to 4, wherein the support column, the beam, and the member are insulated from a wiring, a conductive plug, and the electrode pad.

(Supplementary Note 6) The multilayer wiring layer includes a first insulating layer having a first relative dielectric constant and a second insulating layer having a second relative dielectric constant lower than the first relative dielectric constant.
The semiconductor device according to any one of appendices 1 to 5, wherein the beam and the member are provided in the vicinity of the second insulating layer.

(Supplementary note 7) The semiconductor device according to any one of supplementary notes 1 to 6, wherein the member is provided in each wiring layer between the beams and supports the beam.
(Additional remark 8) The said member is formed in the step shape between the said beams, The semiconductor device as described in any one of Additional remark 1 thru | or 7 characterized by the above-mentioned.

  (Supplementary note 9) The semiconductor device according to any one of supplementary notes 1 to 8, wherein the member is formed in a wall shape between the beams.

It is a section lineblock diagram showing a semiconductor device of this embodiment. It is a top view of the semiconductor device of this Embodiment. It is a cross-sectional block diagram explaining the manufacturing method of the semiconductor device of this Embodiment. It is a top view in the BB line of the semiconductor device of FIG. FIG. 4 is a top view taken along line CC of the semiconductor device of FIG. 3. FIG. 4 is a top view of the semiconductor device of FIG. 3 taken along line DD. FIG. 4 is a top view of the semiconductor device of FIG. 3 taken along line EE. FIG. 4 is a top view of the semiconductor device of FIG. 3 taken along line FF. FIG. 4 is a top view of the semiconductor device of FIG. 3 taken along line GG. FIG. 3 is a cross-sectional configuration view of a semiconductor device in each step of forming a support (No. 1). It is a cross-sectional block diagram of the semiconductor device in each process which forms a support | pillar (the 2). It is a cross-sectional block diagram of the semiconductor device in each process which forms a support | pillar (the 3). It is a cross-sectional block diagram of the semiconductor device in each process which forms a support | pillar (the 4). It is a section lineblock diagram of a semiconductor device in a process of forming an electrode pad. It is a figure which shows the relationship between the structure embedded in the multilayer wiring layer under an electrode pad, and the stress added to the component under the electrode pad. It is the example of arrangement | positioning of the member which supports between beams (the 1). It is the example of arrangement | positioning of the member which supports between beams (the 2).

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Multilayer wiring layer 3, 17, 18, 21, 22, 23, 24, 25, 26 Interlayer insulating film 4 Electrode pad 5a, 5b Post 6a, 6b, 6c Beam 7a, 7b, 7c, 7d Member 11 Element Formation region 12 Element isolation region 13 Gate insulating film 14 Gate electrode 15 Side wall insulating film 16 Source / drain diffusion layer

Claims (5)

A substrate,
A multilayer wiring layer formed on the substrate;
An electrode pad formed on the multilayer wiring layer;
At least two pillars penetrating the multilayer wiring layer and reaching the substrate, and supporting at least two adjacent corners from below among the four corners of the electrode pad;
A plurality of beams connected between the columns;
Members connected between the beams;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the member is connected between the beams and connected between the columns.   The semiconductor device according to claim 1, wherein a width of the member is equal to or less than a width of the beam.   4. The semiconductor device according to claim 1, wherein the member is formed of the same material as the wiring of the multilayer wiring layer. 5.   5. The semiconductor device according to claim 1, wherein the support column, the beam, and the member are insulated from wiring, a conductive plug, and the electrode pad. 6.

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