JP2009283524A - Semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer in which unused space in a margin of a semiconductor wafer is reduced when disposing semiconductor chips with the same slender shape on the semiconductor wafer. <P>SOLUTION: This semiconductor wafer is produced by disposing semiconductor chips 3a and 4a with the same slender shape on a semiconductor wafer 10a in such a manner that an array of the semiconductor chips 3a aligned in the same orientation is arranged in the center part of the semiconductor wafer 10a to form a first group, and semiconductor chips 4a are disposed in an orientation perpendicular to the orientation of semiconductor chips 3a in an upper and lower margins of the first group, wherein the semiconductor chips 4a are disposed so that a longer side of each semiconductor chip 4a is adjacent to shorter sides of the semiconductor chips 3a. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer, and more particularly to a semiconductor wafer in which a plurality of semiconductor chips having short sides and long sides are regularly arranged.

  Some semiconductor devices, such as solid-state imaging devices used in scanners and copying machines, have a ratio of the size in the long side direction to the size in the short side direction (aspect ratio) of 50 or more. There is a long and narrow one. When such a semiconductor device is formed on a semiconductor wafer, there is a demand for a method of efficiently arranging the semiconductor devices so that the number of semiconductor chips that can be taken from one semiconductor wafer is as large as possible.

  FIG. 1 shows a chip arrangement shown in FIG. As another example, a chip arrangement as shown in FIGS. 2 and 3 may be used. Here, a case where a silicon wafer having a diameter of 200 mm is used will be described as an example.

  As shown in FIGS. 1 to 3, a plurality of semiconductor chips 2a to 2c are formed on semiconductor wafers 1a to 1c, respectively. At this time, each semiconductor chip has one or more rows arranged in a lattice shape according to the aspect ratio (ratio of the long side size of the semiconductor chip divided by the short side size). For example, the semiconductor chips 2a shown in FIG. 1 have an aspect ratio of about 100 (long side size is about 80 mm) and are arranged in a row on the semiconductor wafer 1a. The semiconductor chips 2b shown in FIG. 2 have an aspect ratio of about 70 (long side size is about 50 mm), and are arranged in two rows on the semiconductor wafer 1b. Similarly, the semiconductor chips 2c shown in FIG. 3 have an aspect ratio of about 50 (long side size is about 35 mm), and are arranged in three rows on the semiconductor wafer 1c.

  The semiconductor chip formed on the semiconductor wafer needs to be separated for each chip. As a method for separating the semiconductor wafer into semiconductor chips, dicing is generally used. Dicing is a method of cutting a semiconductor wafer by moving a blade that rotates at high speed along a line from which a semiconductor chip is cut out.

  When chips are separated by conventional dicing, the cutting lines must be linear on the semiconductor wafer. Therefore, as shown in FIGS. 1 to 3, the individual semiconductor chips are arranged in a lattice pattern on the semiconductor wafer. There must be. Depending on the size and shape of the semiconductor chip, the layout of the semiconductor chip is restricted, and there are many unused portions (hatched portions in FIGS. 1 to 3) where a complete semiconductor chip cannot be formed at the peripheral edge of the wafer. . As a result, the number of chips obtained from one semiconductor wafer is reduced and the production efficiency is poor.

  A technique for solving this problem is described in Patent Document 2. FIG. 4 shows an arrangement view of the semiconductor chip 21 of the document on the silicon wafer 20. A horizontal separation line between the semiconductor chips 21 is an etching separation line 22 by anisotropic etching, and a vertical separation line indicated by a broken line is a dicing line 23 by dicing. According to Patent Document 2, each semiconductor chip 21 is separated in one direction by dicing and separated in the other direction by etching, so that the degree of freedom of chip arrangement in the silicon wafer 20 is increased. That is, the etching separation line 22 is formed by shifting in the long side direction of the semiconductor chip 21, and the semiconductor chip 21 is arranged so that the unused portion of the silicon wafer 20 is reduced. Increasing the number of chips.

Further, Patent Document 3 discloses a chip arrangement in which a plurality of types of IC chips 12 to 14 having different sizes are arranged on the same semiconductor wafer 11. FIG. 5 shows the chip arrangement. IC chips of the same size are arranged in a horizontal row, and IC chips of different sizes are arranged in a horizontal row in the upper or lower row of the row so that various sizes of IC chips are placed on one semiconductor wafer. The production efficiency is increased and the production efficiency is increased by small-lot production of various products.
JP 2003-324060 (FIG. 2) JP2003-72090 (FIG. 6) JP-A-10-256479 (FIG. 1)

  When an elongated semiconductor chip having an aspect ratio of about 100 (long side size is about 80 mm) is arranged on a semiconductor wafer, when separating the chips by dicing using a blade, the semiconductor chip is shifted in the long side direction. And the unused portion on the semiconductor wafer cannot be reduced.

  In Patent Document 2 (FIG. 4), the semiconductor chips are shifted in the long side direction, but there are still many unused portions. In Patent Document 3 (FIG. 5), the same size semiconductor chips are arranged in a horizontal row. However, as in Patent Document 2, they are merely shifted in one direction.

  In the present invention, elongated and identically shaped semiconductor chips are arranged with the direction rotated by 90 degrees at the peripheral edge of the wafer. That is, the semiconductor wafer of the present invention includes a first group including a plurality of semiconductor chips aligned in the same direction, and a semiconductor chip arranged in a direction different by 90 degrees from the direction of the semiconductor chips included in the first group. A second group including the first group, and the first group and the second group are adjacent to each other.

  By rotating the arrangement direction of the semiconductor chips by 90 degrees with respect to the arrangement direction of the semiconductor chips in the central portion at the peripheral portion of the semiconductor wafer, the unused portion of the peripheral portion of the wafer can be reduced as compared with the conventional one. The number of chips obtained from the semiconductor wafer can be increased.

(First embodiment)

  FIG. 6 shows a chip arrangement on the semiconductor wafer according to the first embodiment of the present invention. Here, a case where a silicon wafer having a diameter of 200 mm is used will be described as an example.

  As shown in FIG. 6, a plurality of semiconductor chips 3a and 4a are formed on a semiconductor wafer 10a. The semiconductor chips 3a and 4a have the same shape. At this time, the layout of the semiconductor chips 3a and 4a formed on the semiconductor wafer 10a differs depending on the chip size and the aspect ratio. For example, the semiconductor chips 3a and 4a shown in FIG. 6 have an aspect ratio of about 100 (long side size is about 80 mm). First, as in the conventional example, a plurality of semiconductor chips 3a are arranged in one row in the left and right (X direction) at the center of the semiconductor wafer 10a. The semiconductor chips 3a are aligned in the same direction, arranged such that the long sides are adjacent to each other and the short sides are aligned in the X direction. The group of these semiconductor chips 3a becomes the first group.

  A semiconductor chip cannot be disposed in the peripheral portion in the same direction as the semiconductor chip 3a. Therefore, at least one semiconductor chip 4a is arranged in the peripheral portion in a direction rotated by 90 degrees with respect to the direction of the semiconductor chip 3a. The semiconductor chip 4a is arranged so that its long side is adjacent to the short side of the semiconductor chip 3a. A plurality of semiconductor chips 4a may be arranged so that unused portions of the semiconductor wafer 10a are reduced as much as possible. In this example, two semiconductor chips 4a are arranged side by side above and below the first group. This group of semiconductor chips 4a becomes the second group. The hatched portion is an unused portion that finally remains.

When the semiconductor chip has an aspect ratio of about 70 (long side size is about 50 mm), it may be arranged as shown in FIG. In FIG. 7, the semiconductor chips 3b ₁ , 3b ₂ , 4b ₁ and 4b ₂ all have the same shape. First, two rows of a plurality of semiconductor chips 3b ₁ aligned in the same direction are arranged vertically in the center of the semiconductor wafer 10b. The two rows entire semiconductor chip 3b ₁ is the first group. Next, the semiconductor chips 3b ₂ aligned in the same direction as the semiconductor chip 3b ₁ are arranged in a line shifted in the Y direction on the left and right (X direction) peripheral portions that cannot be arranged in two rows. This group of semiconductor chip 3b ₂ is the third group. Next, in the same orientation as the semiconductor chip 3b ₁ to the periphery of the upper and lower can not be placed a semiconductor chip (Y direction), placing the semiconductor chip 4b ₁ in a direction rotated 90 degrees with respect to the semiconductor chip 3b ₁ orientation. In this long side size, the two semiconductor chips 4b ₁ is the short side each other can be arranged side by side so as to be adjacent. This group of semiconductor chips 4b ₁ is the second group. Next, the peripheral portion of the remaining vertical (Y-direction), the semiconductor chip 4b ₂ which is aligned in the same direction as the semiconductor chip 4b _1, is arranged offset in the X direction with respect to the semiconductor chip 4b _1. In this example, _two semiconductor chips 4b2 are arranged. This group of semiconductor chips 4b ₂ is the fourth group.

Further, the semiconductor chips 3c ₁ , 3c ₂ , 3c ₃ , 4c ₁ and 4c ₂ shown in FIG. 8 are all the same shape and have an aspect ratio of about 50 (long side size is about 35 mm). Again, the central portion of the semiconductor wafer 10c, placing a row of multiple semiconductor chips 3c ₁ which is aligned in the same direction and three columns. This is the first group. Two rows of semiconductor chips 3c ₂ aligned in the same direction as the semiconductor chip 3c ₁ are arranged on the left and right (X direction) peripheral portions. This is the third group. Further, one row of the semiconductor chips 3c ₃ aligned in the same direction as the semiconductor chip 3c ₁ is arranged on the left and right (X direction) peripheral portions. This is the fifth group. The fifth group is arranged such that the position of the short side is shifted up and down (Y direction) with respect to the third group, but the position of the short side is shifted up and down (Y direction) with respect to the first group. Either or not. Two rows of semiconductor chips 4c ₁ arranged in a direction rotated 90 degrees with respect to the direction of the semiconductor chip 3c ₁ are arranged on the upper and lower (Y direction) peripheral portions of the first group. This is the second group. Further, one row of the semiconductor chips 4c ₂ aligned in the same direction as the semiconductor chip 4c ₁ is arranged on the upper and lower (Y direction) peripheral portions. This is the fourth group.

  As described above, when the semiconductor chips arranged on the semiconductor wafer are separated for each chip, since the cutting lines intersect, the cutting lines can be selectively formed as in laser dicing or etching. It is preferable to use a technique. Since the dicing using a blade can be used for straight portions where the cutting lines do not intersect, dicing may be performed in combination.

  According to the above-described embodiment, the semiconductor chip is arranged in a direction rotated by 90 degrees with respect to the direction of the semiconductor chip in the central part in the peripheral part that cannot be aligned in the same direction as the semiconductor chip arranged in the central part. Yes. The number of semiconductor chip groups, the number of arrays, and the number of columns may be appropriately determined so that unused portions of the semiconductor wafer are reduced. In order to separate the semiconductor chip for each chip, a technique capable of selectively forming a cutting line such as laser dicing or etching may be used. Therefore, unused portions on the semiconductor wafer can be reduced, and more semiconductor chips can be produced from a single semiconductor wafer than in the past.

This is a chip arrangement of a semiconductor wafer disclosed in Patent Document 1. It is a modification of FIG. It is another modification of FIG. This is a chip arrangement of a semiconductor wafer disclosed in Patent Document 2. This is a chip arrangement of a semiconductor wafer disclosed in Patent Document 3. 1 is a chip arrangement of a semiconductor wafer according to a first embodiment of the present invention. It is a modification of chip arrangement of the semiconductor wafer concerning a 1st embodiment of the present invention. It is another modification of chip arrangement of the semiconductor wafer concerning a 1st embodiment of the present invention.

Explanation of symbols

_{3a, 3b 1, 3b 2,} 3c 1, 3c 2, 3c 3 semiconductor chip _{4a, 4b 1, 4b 2,} 4c 1, 4c 2 semiconductor chip 10a, 10b, 10c semiconductor wafer

Claims (4)

A semiconductor wafer in which a plurality of semiconductor chips having a short side and a long side are regularly arranged,
A first group including a plurality of the semiconductor chips aligned in the same direction;
The direction of the semiconductor chips included in the first group includes a second group including the semiconductor chips arranged in a direction rotated by 90 degrees,
A semiconductor wafer arranged such that the first group and the second group are adjacent to each other. The semiconductor wafer according to claim 1,
The first group is disposed in a central portion of the semiconductor wafer,
The second group is a semiconductor wafer disposed on a peripheral edge outside the first group. The semiconductor wafer according to claim 2,
A third group including at least one semiconductor chip aligned in the same direction as the semiconductor chips included in the first group;
The third group is disposed on the peripheral edge so as to be adjacent to the first group,
A semiconductor wafer arranged such that a position of the short side of the semiconductor chip included in the third group is shifted from a position of the short side of the semiconductor device included in the first group. The semiconductor wafer according to claim 3,
A fourth group including at least one semiconductor chip aligned in the same direction as the semiconductor chips included in the second group;
The fourth group is disposed on the peripheral edge so as to be adjacent to the second group,
The semiconductor wafer arrange | positioned so that the position of the said short side of the said semiconductor chip contained in the said 4th group and the position of the said short side of the said semiconductor device contained in the said 2nd group may shift | deviate.

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