KR100998489B1 - High Integrated Phase Memory Device and Method of Manufacturing The Same - Google Patents

Abstract

Disclosed are a highly integrated phase change memory device capable of integrating a larger number of diodes in a limited area, and a method of manufacturing the same. The highly integrated phase change memory device of the present invention includes a semiconductor substrate and an interlayer insulating layer formed on the semiconductor substrate and including a plurality of diodes. The plurality of diodes include first diodes having an upper surface of an inverted triangle shape and second diodes having an upper surface of an equilateral triangle shape, wherein the plurality of diodes include a first diode and a second diode in a column direction and a row direction. Arranged to be alternately arranged.

Phase change, diode, triangle

Description

High Integrated Phase Memory Device and Method of Manufacturing The Same

The present invention relates to a highly integrated phase change memory device and a method of manufacturing the same, and more particularly, to a diode array structure of a highly integrated phase change memory device and a method of manufacturing the same.

As the degree of integration of semiconductor devices is increased, the size and spacing (hereinafter, pitch) of the patterns constituting the circuit are also decreasing. In addition, since a pattern having a line width and / or spacing of 0.1 μm or less is required for a 1 giga DRAM memory device, a 1 gigabyte may be used as a light source currently used, such as a KrF light source (248 nm) or an ArF light source (193 nm). It is difficult to form a pattern applicable to a DRAM device.

In particular, as shown in FIG. 1, in the case of a phase change memory device having one diode contact 10 per 1F × 1F (F: minimum feature size) area, a contact is formed using the KrF or ArF light source as described above. Even more difficult.

In order to form a finer size contact, a light source having a shorter wavelength or a photolithography method has been studied.

However, the development of a new light source has to be accompanied by replacement of exposure equipment, resulting in an increase in manufacturing costs.

Accordingly, an object of the present invention is to provide a highly integrated phase change memory device capable of integrating a larger number of diodes in a limited area and a method of manufacturing the same.

Highly integrated phase change memory device according to an aspect of the present invention for achieving the object of the present invention is formed in a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate, and the interlayer insulating film, has a predetermined interval and have a matrix form An upper surface arranged as includes a plurality of diodes having a triangular shape, wherein the plurality of diodes are arranged such that their upper hypotenuses are parallel to each other.

In addition, a highly integrated phase change memory device according to another aspect of the present invention includes a semiconductor substrate and an interlayer insulating layer formed on the semiconductor substrate and including a plurality of diodes. The plurality of diodes include first diodes having an upper surface of an inverted triangle shape and second diodes having an upper surface of an equilateral triangle shape, wherein the plurality of diodes include a first diode and a second diode in a column direction and a row direction. Arranged to be alternately arranged.

In addition, a method of manufacturing a highly integrated phase change memory device according to still another aspect of the present invention is as follows. First, an interlayer insulating film is formed on the semiconductor substrate, and then a plurality of first diode regions having an inverted triangle shape on the upper surface of the interlayer insulating film are formed at predetermined intervals in the column direction and the row direction. Subsequently, for each of the column direction and the row direction, a second diode region in which an upper surface has an equilateral triangle shape is formed in the interlayer insulating film between the first diodes.

According to the present invention, a diode having a triangular structure on its upper surface is formed by using a double photolithography method. Diodes having a triangular top surface can be arranged so that their upper hypotenuses can be parallel to the upper hypotenuses of adjacent diodes, thereby making the most of the space between the diodes, thereby greatly improving the diode placement efficiency. have.

In addition, by using the double photolithography process, the diodes can be arranged below the exposure limit value.

Therefore, the degree of integration of the phase change memory device can be increased without replacing a new exposure source and exposure equipment.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

2A and 2B are plan views illustrating processes of manufacturing a highly integrated phase change memory device according to an embodiment of the present invention, and FIGS. 3 to 9 are views illustrating a highly integrated phase change memory device according to an embodiment of the present invention. It is sectional drawing for each process for demonstrating a manufacturing method.

First, referring to FIGS. 2A and 3, a semiconductor substrate 100 including an impurity region (not shown) is prepared. An interlayer insulating layer 110 is formed on the semiconductor substrate 100 to have a predetermined thickness. The interlayer insulating layer 110 may include, for example, silicon oxide, and is formed to have a thickness greater than a predetermined thickness by a predetermined thickness. A first photoresist pattern 115 for forming a first diode contact hole is formed on the interlayer insulating layer 110. The first photoresist pattern 115 is, for example, a mask pattern for defining a hole having an upper triangular structure having an inverted triangle shape.

4, the first diode contact hole H1 is formed in the interlayer insulating layer 110 by etching the interlayer insulating layer 110 using the first photoresist pattern 115.

Next, referring to FIG. 5, the selective epitaxial growth layer 115 is formed in a known manner so that the first diode contact hole H1 is sufficiently filled, and then, as shown in FIG. 6, the selective epitaxial growth layer ( 115) is flattened. In this case, the selective epitaxial growth layer 115 may be formed using the n-type impurity region of the semiconductor substrate 100 as a seed to exhibit n-type conductivity. Thus, the first diode region 120 is defined in the interlayer insulating layer 110.

As shown in FIG. 2A, the first diode regions 120 have an inverted triangular structure and are spaced at regular intervals along the row direction. Here, the distance d1 between the bottom side of the first diode region 120 may be an exposure limit value, and the first diode region 120 ′ positioned in the even rows r2 and r4 may have odd rows r1 and r3. It may be located to correspond to the space between the first diode region 120 located in the.

Next, as shown in FIG. 7, the second photoresist pattern 125 for defining the second diode contact hole is formed in a known manner on the interlayer insulating layer 110 in which the first diode region 120 is defined. Here, the second photoresist pattern 125 exposes the interlayer insulating layer 110 between the first diode regions 120 in an equilateral triangle shape. Thereafter, the interlayer insulating layer 110 is etched in the form of the second photoresist pattern 125 to form the second diode contact hole H2.

Referring to FIG. 8, after removing the second photoresist pattern 125 in a known manner, the second selective epitaxial growth layer 130 is formed in a known manner so that the second diode contact hole H2 is filled. do. Since the second selective epitaxial growth layer 130 is also grown by using n-type impurities as a seed, the second selective epitaxial growth layer 130 may have an n-type conductivity.

Next, as shown in FIG. 9, the second selective epitaxial growth layer 130 and the interlayer insulating layer 110 are planarized to form a second diode region 135 between the first diode regions 120.

Here, as shown in FIG. 2B, the second diode region 135 has an equilateral triangle structure and is disposed at regular intervals along the row direction between the first diode regions 120. Like the first diode region 120, the second diode region 135 ′ positioned in the even rows r2 and r4 may have a space between the second diode region 135 positioned in the odd rows r1 and r3. It may be located to correspond. Here, the distance d2 between the bottom side of the second diode region 135 may also be an exposure limit value, and the distance d3 between the first diode region 120 and the second diode region 135 may be the first value. The minimum distance that will not cause an electrical problem between the diode region 120 and the second diode region 135, the distance (d3) is below the exposure limit. In addition, although the upper surface shape of the second diode region 135 is defined as an equilateral triangle in this embodiment, the equilateral triangle herein has the same size as the inverted triangle and does not mean that the three sides have the same length. It can be interpreted as a triangular structure.

That is, in the present embodiment, the first diode region 120 and the second diode region 135 positioned on the same row and the same column are alternately disposed so that hypotenuses of each other are parallel to each other, and in particular, on the same column. The first diode region 120 and the second diode region 135 which are positioned may correspond to vertices or bottom edges.

9, p-type impurities are implanted into the first and second diode regions 120 and 135 to form PN diodes D1 and D2.

According to the present exemplary embodiment, a second diode D2 having an upper triangle in the shape of an equilateral triangle is disposed between the first diode D1 having an inverted triangle on the upper surface by using a double photolithography method. The second diodes D1 and D2 may be spaced apart by a distance less than or equal to the exposure limit value.

In addition, the upper surfaces of the first and second diodes D1 and D2 of the present embodiment are triangular, that is, the first and second diodes D1 and D2 are formed in the form of triangular pillars, respectively. Accordingly, the space between the first diode D1 and the space between the second diode D2 is sufficiently secured, so that a larger number of diodes can be integrated in a limited area.

Experimental Example

In the case of a general phase change memory device, a total of 32 diode contact holes 10 may be disposed in an area of 8F × 4F (see FIG. 1), whereas in the present embodiment, a total of 36 diodes (diode contact holes) are disposed in the same area. Could be placed (see FIG. 2).

Accordingly, in the case of the present embodiment, an arrangement efficiency of 12.5% is improved as compared with the conventional case.

The present invention is not limited to the above embodiment.

In this embodiment, the upper surface of the first diode (or the first diode region) is formed in an inverted triangle structure, and the upper surface of the second diode (or the second diode region) is formed in an equilateral triangle structure, but the present invention is not limited thereto. Of course, it can be configured.

In the drawings and embodiments, exemplary preferred embodiments of the invention have been disclosed, although specific terms are used, these are used only in a general and descriptive sense, and are used to limit the spirit of the invention as defined by the claims which follow. It doesn't happen.

1 is a plan view showing the arrangement of a diode of a typical phase change memory device;

2A and 2B are plan views for each process for explaining a method of manufacturing a highly integrated phase change memory device according to an embodiment of the present invention; and

 3 to 9 are cross-sectional views of respective processes for explaining a method of manufacturing a highly integrated phase change memory device according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

100 semiconductor substrate 110 interlayer insulating film

120: first diode region 135: second diode region

Claims (11)

Semiconductor substrates; An interlayer insulating layer formed on the semiconductor substrate; And A plurality of diodes formed in the interlayer insulating film, the upper surfaces having a predetermined interval and arranged in a matrix form, the plurality of diodes having a triangular shape, The plurality of adjacent diodes are arranged such that their upper hypotenuses are parallel to each other. Semiconductor substrates; And An interlayer insulating layer formed on the semiconductor substrate and including a plurality of diodes, The plurality of diodes includes first diodes having a top surface of an inverted triangle shape and second diodes having a top surface of an equilateral triangle shape, And the plurality of diodes are arranged such that the first diode and the second diode are alternately arranged in a column direction and a row direction. The method of claim 2, And the adjacent first diodes are spaced apart by an interval of an exposure limit. The method according to claim 2 or 3, And the adjacent second diodes are spaced apart by an exposure threshold. The method of claim 2, And the adjacent first and second diodes consecutively arranged in the column direction are arranged such that vertices face each other and vertex sides face each other. The method of claim 2, The first diodes And wherein the selected first diode located in an even row is arranged to correspond to a space between the even row and adjacent first diodes located in an adjacent odd row. The method of claim 6, The second diodes And wherein the selected second diode located in an even row is arranged to correspond to a space between the even row and adjacent second diodes located in an adjacent odd row. Forming an interlayer insulating film on the semiconductor substrate; Forming a plurality of first diode regions having an inverted triangular upper surface in the interlayer insulating layer at predetermined intervals in a column direction and a row direction; And Forming a second diode region in which an upper surface has an equilateral triangle shape in an interlayer insulating film between the first diodes, for each of the column direction and the row direction. The method of claim 8, And forming the first diode region spaced apart from an adjacent first diode region by an exposure limit value. 10. The method according to claim 8 or 9, And forming the second diode region spaced apart from the adjacent second diode region by an exposure limit value. The method of claim 8, After forming the second diode region, And implanting impurities into the first and second diode regions to form a pn diode.

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