JP2009282780A - Formation device of receipt signal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an device and a method for forming a receipt signal for reducing a defect in a conventional technology. <P>SOLUTION: In the device for forming the receipt signal, a processor is subjected to clocking by a processor clock signal, woken up from a stationary state on the basis of an interruption command, processes the command in an operation state, and forms a receipt signal synchronized with the processor clock signal after processing the command or during the processing of the command. At least one of peripheral devices is subjected to clocking by a peripheral device clock signal passing over not synchronized with the processor clock signal, and transmits the interruption command to the processor in synchronization with the peripheral device clock signal. A first logical circuit forms a receipt signal synchronized with the peripheral device clock signal from the receipt signal synchronized with the processor clock signal, and informs that the command has been processed to the peripheral device according to the synchronized receipt signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an apparatus for forming a reception signal in a wheel electronic circuit and a method of using the reception signal.

  Particularly in embedded systems, the processor of the system is typically in a sleep mode or quiescent state (idle state) that conserves energy, from which the processor is woken up by a suspend instruction issued from the system peripherals. The interruption instruction is called an interrupt request in English. After wakeup, the processor processes the interrupt instruction and acknowledges it. In particular, if the peripheral device is clocked with a slower clock than the processor, the peripheral device that issued the suspend command may not receive an acknowledgment and may again send the suspend command to the processor. This wakes up the processor again unnecessarily. This adversely affects the energy consumption of the system.

From the publication DE10127424A1, an electronic circuit is known that asynchronously clocks peripheral devices. An efficient operation can be performed by this electronic circuit. From the publication DD299782A7, synchronization devices for various components in a microprocessor system are known. Another electronic circuit for controlling the energy of the electronic unit is disclosed in the publication EP1785810A1.
DE10127424A1 DD2997982A7

  The object of the present invention is to provide an apparatus and method for forming a reception signal in order to reduce the disadvantages of the prior art.

  This problem is solved by the device according to claim 1 and by the method according to claim 7.

The apparatus of the present invention is a reception signal forming apparatus having a processor, at least one peripheral device, and a first logic circuit,
The processor is clocked by a processor clock signal, wakes up from a quiescent state based on a suspend instruction, processes the suspend instruction in an operational state, and after processing the suspend instruction or during processing of the suspend instruction, the processor clock Form a receipt signal that is synchronized with the signal,
The at least one peripheral device is clocked by a peripheral device clock signal that is asynchronous to the processor clock signal, and transmits the suspension instruction to the processor in synchronization with the peripheral device clock signal;
The first logic circuit forms a reception signal synchronized with a peripheral device clock signal from a reception signal synchronized with a processor clock signal,
The peripheral reception device is notified by the synchronized reception signal that the interruption instruction has been processed.

The method of the invention has the following method steps:
A step in which an interrupt instruction synchronized with the peripheral clock signal is formed by the peripheral clocked by the peripheral clock signal;
The processor is woken up based on the suspend instruction, which causes the processor to transition from its quiescent state to an operational state, where the suspend instruction is processed by the processor, and the processor is clocked by a processor clock signal that is asynchronous to the peripheral clock signal Step,
A step in which a receipt signal synchronized with the processor clock signal is formed after the processor has processed the suspend instruction or formed when the processor processes the suspend instruction, and synchronized with the peripheral clock signal A receipt signal is formed by the first logic circuit from the receipt signal synchronized with the processor clock signal, thereby notifying the peripheral device that the interrupt command has been processed;

  The apparatus of the present invention includes a processor and at least one peripheral device. Peripherals and processors are different and clocked by clock signals that are asynchronous with each other. The processor is typically in a stationary state that conserves energy and is woken up by a suspend instruction issued from a peripheral device to process the suspend instruction in the operating state. During processing of the suspend instruction or after the suspend instruction is processed, the processor forms a receipt signal that is synchronized to the processor clock signal. The reception signal synchronized with the processor is formed to notify the peripheral device that the interruption command has been processed. As a result, the peripheral device does not transmit the interruption command again. The peripheral device is reset based on the received signal, and the interruption command is not transmitted again. A receipt signal that is synchronized to the processor clock signal can also be used to transition the processor back to a quiescent state.

  The processor and peripheral devices operate asynchronously with each other. In particular, the processor can operate with a faster clock than the peripheral device. That is, the clock frequency of the peripheral device clock signal can be made lower than the clock frequency of the processor clock signal. This leads to energy savings of the device of the present invention. This is because the peripheral is slowly clocked, potentially consuming less energy than if it was clocked at a relatively high frequency. In contrast, the processor is typically in a quiescent state and is only operational when processing a suspend instruction. Therefore, clocking with a relatively high clock frequency adversely affects energy consumption, even if relatively small.

  In particular, if the processor is clocked at a higher frequency than the peripheral device, the receive signal that is synchronized to the processor clock signal does not persist until the next clock cycle of the peripheral device, and the peripheral device does not receive the receive signal. There may not be. In order to avoid this, the device of the present invention has a first logic circuit. The first logic circuit forms a reception signal synchronized with the peripheral device clock signal from the reception signal synchronized with the processor clock signal. Therefore, the peripheral device reliably receives the reception signal, and therefore does not undesirably issue the same interruption command to the processor again.

  In a modified embodiment of the device according to the invention, the first logic circuit comprises a first flip-flop and a second flip-flop. The first flip-flop is clocked by the processor clock signal and its input signal is a reception signal that is synchronized at least indirectly to the processor clock signal. The second flip-flop is for forming a reception signal synchronized with the peripheral device clock signal, is clocked by the peripheral device clock signal, and its input signal is an output signal of the first flip-flop. The first flip-flop of the first logic circuit captures the received signal that is synchronized with the processor clock signal and is subsequently synchronized by the second flip-flop to be synchronized with the peripheral device clock signal. According to this variant embodiment, the first flip-flop of the first logic circuit is directly supplied with a reception signal synchronized with the processor clock signal or a signal derived from the reception signal synchronized with the processor clock signal Is supplied.

  Instead of the second flip-flop, at least two flip-flops cascaded can be used. This increases the stability of the first logic circuit.

  According to another variant of the device according to the invention, this device comprises a second logic circuit, which receives a processor clock from an interrupt instruction transmitted in synchronization with the peripheral clock signal. A continuous interruption instruction is formed in synchronization with the signal, and the continuous interruption instruction is supplied to the processor. The interruption command issued from the peripheral device is synchronized with the peripheral device clock signal and is asynchronous with the processor clock signal. Based on this embodiment, the processor can reliably receive a suspend instruction, especially if the processor being used can only process a suspend instruction that is synchronized to its processor clock signal.

  The second logic circuit can include a shift register, a logic circuit that is connected to the shift register, and a flip-flop. The input signal of the shift register is a suspend command transmitted in synchronization with the peripheral device clock signal or a signal synchronized with the suspend command. The logic circuit is for identifying an edge of an output signal of the shift register. The flip-flop is clocked by a processor clock signal, its input signal is an output signal of a logic circuit for identifying an edge, and its output signal is a continuous interruption instruction synchronized with the processor clock signal. The shift register has at least two flip-flops connected in series, for example, which are clocked by a processor clock signal. In particular, the shift register has at least three flip-flops connected in series, which can increase the stability of the shift register. As a result, the post-connected logic circuit for identifying the edge of the output signal of the shift register reliably identifies the edge, especially the rising edge.

  The second logic circuit may also be configured to form a wake-up signal to the processor from a suspend instruction that is synchronized to the peripheral clock signal. This wake-up signal switches on, for example, a clock generator to form a processor clock signal, thereby switching the processor from its quiescent state to an operational state.

  The device of the invention can be used, for example, in wheel electronics. Wheel electronics are generally provided for detecting at least one tire parameter of the tire. The tire parameter is, for example, tire air pressure. In addition to the device of the present invention, the wheel electronic circuit of the present invention has at least one sensor for detecting tire parameters and a transmitter. Here, the processor detects the tire parameter by means of a sensor based on the interruption command, forms a message relating to the tire parameter, which is transmitted by the transmitter.

  The wheel electronics are for example built into the tire or placed on the rim to which the tire is attached. When the vehicle equipped with the tire is operated, the wheel electronic circuit automatically detects the pressure of the corresponding tire and notifies the control device arranged in the vehicle by radio. Based on the detected air pressure, the control device detects, for example, whether one of the tires has an excessively low air pressure, and notifies the person driving the vehicle that the air pressure is excessively low.

  In an embodiment of the wheel electronic circuit of the present invention, the peripheral device is a timer and / or receiver. The timer is provided, for example, for periodically forming an interruption instruction. This causes the wheel electronics to periodically send a message regarding tire parameters to the control device via its transmitter. A receiver is provided for forming an interrupt command based on the received signal. The received signal is derived, for example, from a control device arranged in the vehicle.

Embodiments of the invention are schematically illustrated in the accompanying drawings by way of example.
FIG. 1 is a schematic diagram showing a vehicle in which wheel electronic circuits are arranged on tires.
FIG. 2 is a schematic diagram showing a wheel electronic circuit.
FIG. 3 is a partial circuit diagram of the wheel electronic circuit.
FIG. 4 is a diagram showing signal progress.

  FIG. 1 shows an automobile 1 having four tires 2, to which one wheel electronic circuit 3 shown in detail in FIG. 2 is assigned. The wheel electronics 3 can be incorporated in the corresponding tire 2. Or it can arrange | position to the rim | limb with which the tire 2 was attached. The wheel electronic circuit 3 is provided to measure the air pressure of each tire 2 and to wirelessly transmit information about the measured air pressure to the control device 4 disposed in the automobile 1. The control device 4 processes this information and notifies the person driving the car if one of the air pressures is too low. The wheel electronic circuit 3 is an example of a device comprising a processor and at least one peripheral device.

  In the present embodiment, each wheel electronic circuit 3 includes a processor 21, a transmitter 22, a timer 23, a pressure sensor 24, a receiver 25, and a battery 26. The processor 21 is, for example, a microcontroller or a microprocessor, and the battery 21 supplies electric energy to the processor 21, the transmitter 22, the receiver 25 and the timer 23.

  In the case of the present embodiment, the wheel electronic circuit 3 periodically transmits information on the current air pressure of the tire to the control device 4 by the transmitter 22. In addition, the control device 4 can send an inquiry to the wheel electronic circuit 3, and based on this inquiry, the wheel electronic circuit 3 detects the air pressure of the tire 3 and notifies the control device 4 by the transmitter 22. The wheel electronic circuit 3 receives this inquiry by means of its receiver 25.

  In this embodiment, the processor 21 detects the air pressure by the pressure sensor 24 and forms a message relating to the air pressure. This message is notified to the control device 4 by the transmitter 22. In order to save energy, the processor 21 is normally in a sleep mode or quiescent state that saves energy. Only when the processor 21 should form a message regarding air pressure is the processor woken up by an interrupt instruction. That is, the timer 23 wakes up periodically or in some cases by the receiver 25. Therefore, the timer 23 and the receiver 25 are peripheral devices that issue an interrupt command to the processor 21.

  Based on the suspend instruction, the processor 21 is woken up. That is, the processor 21 shifts from the stationary state to the operating state and processes the interruption command. When the suspend instruction is processed, the processor forms a receipt signal. In response to this reception signal, the processor 21 notifies the corresponding peripheral device that the interruption command has been processed. As an alternative, the receipt signal can already be formed before the processing of the interrupt instruction. The receipt signal can also be used to put the processor 21 back into the quiescent state. Otherwise, another interrupt command is generated. FIG. 3 shows a circuit for executing this scenario in this embodiment. FIG. 4 shows a signal course of the reception signal QS formed by the processor 21.

  When the processor 21 is in the operating state, the processor 21 is clocked by the processor clock signal CLK1. This processor clock signal is formed by the first clock generator 27 in this embodiment. Similarly, the first clock generator 27 is also normally stationary and is woken up by the wake-up signal WS to form the processor clock signal CLK1 and is supplied with energy by the battery 26. The processor clock signal CLK1 has a clock frequency of 4 MHz, for example.

  Unlike the processor 21, the peripheral device, that is, the receiver 25 and the timer 23 are always in an operating state, and are always clocked by the peripheral device clock signal CLK2. Here, the timer 23 and the receiver 25 can be clocked by different peripheral device clock signals. However, in this embodiment, clocking is performed by the same peripheral device clock signal CLK2. The peripheral device clock signal is formed by, for example, the second clock generator 28, and the clock frequency of the peripheral device clock signal CLK2 is much lower than the clock frequency of the processor clock signal CLK1. The peripheral device clock signal CLK2 is, for example, 90 kHz.

  If one of the peripherals requests the processor 21 to form a message regarding the current air pressure, this peripheral, for example the timer 23, forms a signal 31, which is fed to the first flip-flop FF1 . The first flip-flop FF1 is clocked by a corresponding peripheral device, here a peripheral device clock signal of the timer 23. The output signal of the first flip-flop FF1 is supplied to the second flip-flop FF2 as a clock signal. The input terminal of the second flip-flop FF2 is set to logic “1”, so the output signal FF2S of the second flip-flop FF2 is set to “1” by the rising edge of the output signal FF1S of the first flip-flop FF1. Set. The output signal FF2S of the second flip-flop FF2 is supplied to the OR gate 32. A wakeup signal WS for the first clock generator 27 of the processor 21 is generated at the output terminal of the OR gate. An input signal not shown in detail in FIG. 3 is generated from the receiver 25 for the OR gate 32. That is, when the timer 23 or the receiver 25 has an interrupt instruction for the processor 21, the wakeup signal WS for wakeup of the first clock generator 27 is logic “1”. When the wakeup signal WS for the first clock generator 27 is switched from logic “0” to logic “1”, the second clock generator 27 starts to form the processor clock signal CLK1 after a predetermined time. As a result, the processor 21 switches from the stationary state to the operating state. In this embodiment, the wakeup signal WS is formed at time t0, and the processor clock signal CLK1 is formed at time t1.

  The output signal FF2S of the second flip-flop FF2 is further supplied to the shift register train. In this embodiment, the shift register train has third, fourth, and fifth flip-flops FF3, FF4, and FF5, which are clocked by a processor clock signal, respectively. Here, the third flip-flop FF3 forms the output signal FF3S, the fourth flip-flop FF4 forms the output signal FF4S, and the fifth flip-flop FF5 forms the output signal FF5S.

  Output signals FF4S and FF5S of the fourth and fifth flip-flops FF4 and FF5 are supplied to the logic circuit 33. In this embodiment, this logic circuit identifies the rising edge of the output signal FF5S of the fifth flip-flop FF5, and applies a logic “1” to the input terminal of the sixth flip-flop FF6 based on this. The sixth flip-flop FF6 is similarly clocked by the processor clock signal CLK1. The output signal of the sixth flip-flop FF6 is an interrupt signal INTER, which is generated at time t2, and based on this, the processor 21 starts processing the interrupt instruction of the timer 23.

  In this embodiment, the shift register having the third, fourth and fifth flip-flops FF3 to FF5 and the sixth flip-flop FF6 ensure that the interrupt signal INTER elapses in synchronization with the processor 21. .

  When the processor 21 processes the interruption instruction, the processor forms a reception signal QS and an address signal QSad. The peripheral device that issued the interruption command is addressed by this address signal. In this embodiment, the address signal QSad is defined for the timer 23. In order for the address signal QSad to be generated for the first time after the receipt signal QS is formed, this receipt signal is shifted by the half processor clock CLK1 by the delay element 36. As a result, a reception signal QSd is formed, and this signal is synchronized with the processor clock CLK1 in the same manner as the reception signal QS.

  In this embodiment, the processor 21 forms the reception signal QS at time t3. The address signal QSad is formed at the same time t3.

  The delayed reception signal QSd and address signal QSad are supplied to the logic circuit 33 and another logic circuit 34. The logic circuit 34 resets the second flip-flop FF2, whereby the output signal FF2S of the second flip-flop FF2 is reset to logic “0” again, and the wakeup signal WS is cut off again. Otherwise, another interrupt command is generated by the receiver 25, for example. Therefore, the processor 21 is restored to the stationary state again. As a result, the portion of the wheel electronic circuit 3 synchronized with the processor clock CLK1 identifies that the interruption instruction has been processed after the interruption instruction has been processed.

  The wheel electronic circuit 3 has seventh, eighth and ninth flip-flops FF7 to FF9 so that the peripheral device issuing the interrupt command receives information regarding that the interrupt command has been processed. Of these, the seventh flip-flop FF7 is clocked by the processor clock signal CLK1, and the eighth and ninth flip-flops FF8 and FF9 are clocked by the peripheral device clock signal CLK2.

  In this embodiment, the reception signal QS and the address signal QSad are first supplied to the logic circuit 35. The logic circuit evaluates the address signal QSad as to whether or not the reception signal QS is defined for the timer 23.

  If the reception signal QS is specified for the timer 23, the input signal of the seventh flip-flop FF7 is set to logic “1”, and the reception signal QS is captured in synchronization with the processor clock signal CLK1. . The output signal FF7S of the seventh flip-flop FF7 clocked by the processor clock signal CLK1 is supplied to the eighth flip-flop FF8 clocked by the peripheral device clock signal CLK2. Similarly, the output signal FF8S of the eighth flip-flop FF8 is supplied to the ninth flip-flop FF9 that is clocked by the peripheral device clock signal CLK2. The output signal FF9S of the ninth flip-flop FF9 is synchronized with the peripheral device clock signal CLK2, and is supplied to the timer 23 as a reception signal.

  Accordingly, the seventh flip-flop FF7 captures the continuous reception signal QS formed by the processor 21 and synchronized with the processor clock signal CLK1. The eighth and ninth flip-flops FF8 and FF9 synchronize the reception signal QS with the timer 23. That is, an output signal FF9S synchronized with the peripheral device clock signal CLK2 is formed, and this output signal FF9S passes as a reception signal for the timer 23. In this way, the wheel electronic circuit 3 can receive a new interruption command again.

FIG. 1 is a schematic diagram showing a vehicle in which wheel electronic circuits are arranged on tires. FIG. 2 is a schematic diagram showing a wheel electronic circuit. FIG. 3 is a partial circuit diagram of the wheel electronic circuit. FIG. 4 is a diagram showing signal progress.

Explanation of symbols

1 car
2 tires
3 wheel electronic circuit
4 Control device
21 processor
22 Transmitter
23 Timer
24 Pressure sensor
25 Receiver
26 battery
27 First clock generator
28 Second clock generator
31 signals
32 OR gate
33-35 logic circuit
36 Delay element
CLK1 Processor clock signal
CLK2 peripheral clock signal
FF1 to FF9 flip-flop
FF1S to FF9S output signal
INTERS interrupt signal
QS receipt signal
QSd delayed receipt signal
QSad address signal

Claims (14)

A receiving signal forming device comprising a processor (21), at least one peripheral device (23, 25), and a first logic circuit (FF7 to FF9),
The processor (21) is clocked by a processor clock signal (CLK1), is woken up from a quiescent state based on an interrupt command (31), processes the interrupt command in an operating state, and after processing the interrupt command or the During the processing of the suspend instruction, the reception signal (QS) that is synchronized with the processor clock signal (CLK1) is formed,
The at least one peripheral device (23, 25) is clocked by a peripheral device clock signal (CLK2) that is asynchronous with the processor clock signal (CLK1), and the interrupt command (31) is transmitted to the peripheral device clock signal (CLK). (Synchronized with CLK2) to the processor (21),
The first logic circuit (FF7 to FF9) forms a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2) from a reception signal (QS) synchronized with the processor clock signal (CLK1),
An apparatus for forming a reception signal, characterized in that the peripheral device (23, 25) is notified by the synchronized reception signal that the interruption instruction has been processed. The apparatus of claim 1,
The first logic circuit (FF7 to FF9) has a first flip-flop (FF7),
The first flip-flop is clocked by a processor clock signal (CLK1),
The input signal of the first flip-flop is a reception signal (QS) that is at least indirectly synchronized with the processor clock signal (CLK1),
The first logic circuit (FF7 to FF9) has a second flip-flop (FF8) to form a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2),
The second flip-flop (FF8) is clocked by the peripheral clock signal (CLK2),
The input signal of the second flip-flop is an output signal (FF7S) of the first flip-flop (FF7). The apparatus of claim 2,
The first logic circuit (FF7 to FF9) has a second flip-flop (FF8, FF9) composed of a plurality of cascade-connected flip-flops, and each of the plurality of flip-flops has a peripheral device clock signal (CLK2). )
The device characterized in that the output signal of the flip-flop (FF9) connected at the end of the second flip-flop is a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2). In the device according to any one of claims 1 to 3,
The second logic circuit (FF1 to FF6, 33) receives an interruption instruction (INTERS) that passes in synchronization with the processor clock signal (CLK1) from the interruption instruction (31) sent in synchronization with the peripheral device clock signal (CLK2). ) And the interrupt instruction is supplied to the processor (21). The apparatus of claim 4,
The second logic circuit has shift registers (FF3 to FF5),
The input signal of the shift register is a suspend command (31) transmitted in synchronization with the peripheral device clock signal (CLK2) or a suspend command (31 transmitted in synchronization with the peripheral device clock signal (CLK2)). ) (FF2S) synchronized with
The second logic circuit has a logic circuit (33) connected downstream from the shift register (FF3 to FF5),
The post-connected logic circuit identifies the edge of the output signal (FF5S) of the shift register (FF3 to FF5),
The second logic circuit has a flip-flop (FF6),
The flip-flop is clocked by the processor clock signal (CLK1),
The input signal is an output signal of the logic circuit (33) for identifying the edge,
The output signal is an interrupt command (INTERS) that elapses in synchronization with the processor clock signal (CLK1). Using the device according to any one of claims 1 to 5 in a wheel electronics for detecting at least one tire parameter of a tire (2),
The wheel electronic circuit (3) is assigned to the tire,
The wheel electronics has at least one sensor (24) for detecting tire parameters and a transmitter (22);
The processor (21) detects a tire parameter based on an interruption command of the sensor (24), forms a message regarding the tire parameter, and the transmitter (24) transmits the message. how to use. A method for forming a receipt signal comprising the following method steps:
A step formed by a peripheral device (23, 25) in which an interrupt instruction (31) synchronized with the peripheral device clock signal (CLK2) is clocked by the peripheral device clock signal (CLK2);
The processor (21) is woken up based on the suspension instruction, which causes the processor to transition from its quiescent state to an operating state, where the suspension instruction is processed by the processor, and the processor (21) is the peripheral device clock signal (CLK2). A step clocked by an asynchronous processor clock signal (CLK1);
A receipt signal (QS) synchronized with the processor clock signal (CLK1) is formed after the processor (21) processes the interrupt instruction, or is formed when the processor (21) processes the interrupt instruction. And a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2) from the reception signal (QS) synchronized with the processor clock signal (CLK1) by the first logic circuit (FF7 to FF9). A step of notifying the peripheral device (23, 25) that the interruption instruction has been processed,
The formation method characterized by the above-mentioned. The method of claim 7, wherein
The first logic circuit (FF7 to FF9) has a first flip-flop (FF7),
The first flip-flop is clocked by a processor clock signal (CLK1),
The input signal of the first flip-flop is a reception signal (QS) that is at least indirectly synchronized with the processor clock signal (CLK1),
The first logic circuit (FF7 to FF9) has a second flip-flop (FF8) to form a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2),
The second flip-flop (FF8) is clocked by the peripheral clock signal (CLK2),
The input signal of the second flip-flop is the output signal (FF7S) of the first flip-flop (FF7). The method of claim 8, wherein
The first logic circuit (FF7 to FF9) has a second flip-flop (FF8, FF9) composed of a plurality of cascade-connected flip-flops, and each of the plurality of flip-flops has a peripheral device clock signal (CLK2). )
The output signal of the flip-flop (FF9) connected at the end of the second flip-flop is a reception signal (FF9S) synchronized with the peripheral device clock signal (CLK2). A method according to any one of claims 7 to 9,
The second logic circuit (FF1 to FF6, 33) receives an interruption instruction (INTERS) that passes in synchronization with the processor clock signal (CLK1) from the interruption instruction (31) sent in synchronization with the peripheral device clock signal (CLK2). ) And the interrupt instruction is provided to the processor (21). The method of claim 11, wherein
The second logic circuit has shift registers (FF3 to FF5),
The input signal of the shift register is a suspend command (31) transmitted in synchronization with the peripheral device clock signal (CLK2) or a suspend command (31 transmitted in synchronization with the peripheral device clock signal (CLK2)). ) (FF2S) synchronized with
The second logic circuit has a logic circuit (33) connected downstream from the shift register (FF3 to FF5),
The post-connected logic circuit identifies the edge of the output signal (FF5S) of the shift register (FF3 to FF5),
The second logic circuit has a flip-flop (FF6),
The flip-flop is clocked by the processor clock signal (CLK1),
The input signal is an output signal of the logic circuit (33) for identifying the edge,
The output signal is an interrupt instruction (INTERS) that passes in synchronization with the processor clock signal (CLK1). The method according to claim 10 or 11,
The second logic circuit (FF1 to FF6, 33) forms a wake-up signal (WS) to the processor (21) from the interrupt instruction (31) sent in synchronization with the peripheral device clock signal (CLK2). Feature method. A method according to any one of claims 7 to 12,
The method, wherein the processor clock signal (CLK1) has a higher clock frequency than the peripheral clock signal (CLK2). A method according to any one of claims 7 to 13,
The processor (21), peripheral devices (23, 25), and the first logic circuit (FF7 to FF9) detect at least one tire parameter of the tire (2) to which the wheel electronic circuit (3) is assigned. Part of the wheel electronics (3)
The tire parameters of the tire (2) are measured by the sensor (24) of the wheel electronic circuit (3),
A message about the tire parameters of the tire (2) is formed by the processor (21) based on the interruption instruction,
Transmitting said message by means of a transmitter (22) of the wheel electronics (3).

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