JP2009278307A - Delay detection circuit and adjustment method for delay detection circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a detection operation band of a delay detection circuit and an SN ratio. <P>SOLUTION: An input FM modulation pulse signal 21 is non-inverted and inverted to output a non-inverse signal 23 and an inverse signal 24. After a delay by a delay time Td, it is non-inverted and inverted to output a non-inverse delay signal 26 and an inverse delay signal 27. The signals 23 to 27 are band-limited so that ringing of signal waveform is suppressed in respective band limiting circuits 51 to 54. The band-limited signals 63 and 66 are logically ORed to output a non-inverse logical OR signal 68, and the band-limited signals 64 and 67 are logically ORed to output a non-inverse logical OR signal 69, and the signals 28 and 29 are synthesized to obtain a demodulation signal 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a delay detection circuit that obtains a predetermined modulation signal by delay detection of an input FM modulation pulse signal, and a method for adjusting the delay detection circuit.

  As a conventional delay detection circuit, for example, there is a delay detection circuit 10 described in Patent Document 1 shown in FIG. The delay detection circuit 10 includes a signal delay circuit 11 that outputs an input signal after being delayed by a preset delay time Td, and first and second signals having a non-inverted output terminal and an inverted output terminal (indicated by ◯ in the figure). Differential output buffer circuits 12 and 13, and first and second OR circuits 14 and 15.

  Further, the delay detection circuit 10 receives an FM (frequency modulation) modulation pulse signal 21 via an input side connection unit 16 that connects the input ends of both the signal delay circuit 11 and the first differential output buffer circuit 12. In addition, the demodulated signal 22 is output via the output side connection unit 17 that connects the output terminals of both the first and second OR circuits 14 and 15, and the output side connection unit 17 is connected to the power source Vcc via a resistor 18.

  The FM modulation pulse signal 21 input to the delay detection circuit 10 is input to the first differential output buffer circuit 12 and the signal delay circuit 11 via the input side connection unit 16. With this input, the non-inverted signal 23 is output from the non-inverted output terminal of the first differential output buffer circuit 12 to the first OR circuit 14, and the inverted signal 24 is output from the inverted output terminal to the second OR circuit 15. Is output.

  On the other hand, in the signal delay circuit 11, the FM modulation pulse signal 21 is delayed by the delay time Td, and this delay signal 25 is input to the second differential output buffer circuit 13, thereby the second differential output buffer circuit 13. The non-inverted delay signal 26 is output to the first OR circuit 14 from the non-inverted output terminal, and the inverted delay signal 27 is output to the second OR circuit 15 from the inverted output terminal.

  The first logical sum circuit 14 performs a logical sum operation of the non-inverted signal 23 and the non-inverted delay signal 26, and outputs a non-inverted logical sum signal 28 obtained as a result of this operation. The second OR circuit 15 performs an OR operation on the inverted signal 24 and the inverted delay signal 27 and outputs an inverted OR signal 29 obtained as a result of the operation. The non-inverted logical sum signal 28 and the inverted logical sum signal 29 are combined at the output side connection unit 17 to obtain the demodulated signal 22.

Further, the operation of the delay detection circuit 10 will be described in detail with reference to FIG.
The signal input to the first OR circuit 14 has a voltage level of “H” (hereinafter abbreviated as “H”) as shown between times t1 and t3, and between times t3 and t5. A non-inverted signal 23 having a voltage level of “L” (hereinafter abbreviated as “L”) and a non-inverted signal delayed by a delay time Td as shown between time t3 and time t4 with respect to the non-inverted signal 23. This is a delay signal 26. Here, when the logical sum is taken, a non-inverted logical sum signal 28 having “H” between times t1 and t4 and “L” between times t4 and t5 is obtained.

  That is, in the non-inverted OR signal 28, a pulse having a width of the delay time Td shown between the time t3 and the time t4 is added to the carrier signal having the period 2T shown between the time t1 and the time t3 and between the time t3 and the time t5. Signal. On the other hand, when the frequency of the input FM modulation pulse signal 21 is high, the period T becomes shorter as shown by the waveform 28a and between the times t2-1 to t3 and between the times t3 and t4-1. The pulse interval of the inverted OR signal 28 becomes dense. On the contrary, when the frequency is low, although not shown, the period T becomes long and the pulse interval of the non-inverted OR signal 28 becomes sparse.

  In this way, a frequency-voltage conversion operation (hereinafter abbreviated as FV conversion operation) is performed by the density of pulses having a period T width. At this time, if the time required for the rise and fall of the signal is the same, and Tr is shown between the times t6 and t8 or between t9 and t10, the FV conversion operation is “L” shown between the times t4 and t5. The process is performed linearly until the time width Tc becomes 0, that is, until Tc = Tr.

In the case of an ideal rectangular wave, the maximum operating frequency fc for linear operation is expressed by the following equation (1).
fc = 1 / {2 · (Td + Tr)} (1)

  The same operation is performed for the inverted signal 24 and the inverted delay signal 27 by the second OR circuit 15. As apparent from the non-inverted OR signal 28 that is the demodulated output shown in FIG. 2, a carrier wave signal is superimposed on the demodulated output. The carrier signal is also superimposed on the inverted OR signal 29, which is the demodulated output in the second OR circuit 15 that operates in the same manner with respect to the inverted signals 24 and 26, and this phase is opposite, so the first The carrier component is canceled by taking the sum with the non-inverted OR signal 28 output from the OR circuit 14. That is, the non-inverted logical sum signal 28 and the inverted logical sum signal 29 are combined at the output side connection unit 17 so that the carrier wave component is canceled and the desired demodulated signal 22 is obtained.

  As described above, in order to increase the maximum operating frequency fc, it is necessary to use a logic element in which the rise and fall of a signal to be subjected to logic operation processing becomes fast, but the signal waveform in that case is subject to overshoot or undershoot. The accompanying ringing occurs, and this causes a non-linearity error of the FV conversion characteristic during the FV conversion operation.

  This will be described with reference to FIGS. FIG. 3 is a waveform diagram of the non-inverted signal 23R with ringing and the non-inverted delay signal 26R input to the first OR circuit 14 and the non-inverted OR signal 28R with the same ringing. FIG. 4 is an internal circuit diagram of the first or second OR circuit 14 or 15.

  The OR circuit 14 or 15 includes input-side transistors 31 and 32, an output-side transistor 33, a resistor 34, a current source 35, a voltage source 36 that determines the dark value of the input logic, and a base end of the transistor 31. The input base terminal 37 connected, the input base terminal 38 connected to the base end of the transistor 32, and the OR output terminal 39 connected to the collector end of the transistor 33 are comprised.

  In these components 31 to 39, the collector ends of the input side transistors 31 and 32 are both connected to the power source Vcc, the emitter end is grounded via the current source 35, and the collector end of the output side transistor 33 is connected via the resistor 34. The emitter terminal is connected to the ground 40 via the current source 35, and the base terminal is grounded via the voltage source 36.

  When this circuit is the first OR circuit 14, the non-inverted signal 23 is input to the input base terminal 37, and the non-inverted delay signal 26 is input to the input base terminal 38. A non-inverted OR signal 28 is output. In the case of the second OR circuit 15, the inverted signal 24 is input to the input base terminal 37, the inverted delay signal 27 is input to the input base terminal 38, and the inverted OR signal 29 is output from the OR output terminal 39. The

  The output-side transistor 33 transitions through the linear operation region at the timing of rising and falling of the signal at times t4 and t5 shown in FIG. 3, and most of the other time is in the saturation region of on or off. In the time zone in this saturation region, no matter how the input signal changes, the influence on the output signal is small. For example, even when a signal whose logic is inverted from the input base terminal 37 or 38 is input to the base end of one of the transistors 31 or 32 at the time t2 or t3 shown in FIG. The influence on the signal output from 39 is small. However, the change in the input signal at the time when the output-side transistor 33 passes through the linear operation region as at time t4 or t5 affects the output signal. For example, it is a time zone of the rise or fall time Tr width in the vicinity of the times t4 and t5.

  The first OR circuit 14 will be further described as a representative. First, at time t4, the input side is changed in accordance with the falling change of the non-inverted delay signal 26 delayed from the input base terminal 38 by the delay time Td. The transistor 32 and the output side transistor 33 are in a linear operation state. At this time, if the ringing due to the undershoot of the non-inverted signal 23R changed at time t3 does not converge, this affects the capacitance between the base and the emitter of the other input side transistor 31, and the output side transistor 33 in the linear operation state. And the non-inverted logical sum signal 28 from the logical sum output terminal 39 is considerably affected.

  However, since this influence does not change the time width after the time Td from the time t3 even if the input frequency changes, the time width Td is always constant and does not affect the linearity of the FV conversion characteristics.

  Next, at time t5, the input-side transistor 31 and the output-side transistor 33 pass through the linear operation state with the rising change of the non-inverted signal 23R. At this time, the non-inverted delayed signal 26 delayed by the delay time Td. If the ringing generated at the time t4 is not converged, the non-inverted OR signal 28 output from the OR output terminal 39 is affected. Although the time t5 occurs after the time Tc from the time t4, the time width Tc becomes shorter as the input frequency becomes higher, and the FV conversion operation fails when Tc = 0.

As is clear from FIG. 3, when the input signal has ringing due to undershoot, the influence of ringing becomes significant on the high frequency side, and the FV conversion characteristic has a ripple in the high band as shown by the curve 42 in FIG. It becomes.
In order to suppress the ripple error of the FV conversion characteristic due to this ringing, a feedback technique has been conventionally used for differential output buffer circuits and logic circuits, or a band is reduced by inserting a resistor or capacitor in the signal line. A method for suppressing ringing is used.

JP 2006-109018 A

  However, since the conventional method for suppressing ringing is applied uniformly to the delay detection circuit, there is a problem that the detection operation band is considerably reduced at the same time.

  Furthermore, as described above, in the method of using two sets of signals that are phase-inverted in order to widen the detection operation band, detecting using two logic circuits, and finally synthesizing, the variation in circuit element performance and signal If there is a difference in the characteristics of the buffers and logic circuits of the two paths due to variations in the conductivity of the line, the carrier component remains without being completely cancelled, and this influence causes the signal-to-noise ratio of the demodulated signal (signal-to-noise). Ratio) also varies, and there is a problem that the SN ratio is lowered.

  In order to solve the above-described problems, an object of the present invention is to improve the detection operation band and the SN ratio of a delay detection circuit.

  In order to achieve the above object, the inventors non-invert and invert the FM modulation pulse signal input from the outside with a differential output buffer circuit to output a non-inverted signal and an inverted signal, and for a certain time Td. After the delay, the differential output buffer circuit performs non-inversion and inversion to output a non-inverted delay signal and an inverted delay signal, and band limiting is performed on these output signals individually so that ringing of the signal waveform is suppressed by the band limiting circuit. Each of the obtained signals is subjected to a logical sum operation with a logical sum circuit for each of the band-limited non-inverted signal and the band-limited non-inverted delayed signal pair and the band-limited inverted signal and the band-limited inverted signal. The demodulated signal is obtained by synthesizing the non-inverted logical sum signal and the inverted logical sum signal as the result.

  Specifically, a first differential output buffer circuit that receives an FM modulated pulse signal that is a frequency-modulated pulse signal and outputs an inverted signal obtained by inverting the FM modulated pulse signal and a non-inverted signal that is not inverted; A signal delay circuit that receives the FM modulation pulse signal and outputs a delay signal obtained by delaying the FM modulation pulse signal for a predetermined time; an inverted delay signal obtained by inverting the delay signal output from the signal delay circuit; A second differential output buffer circuit that outputs a non-inverted delay signal, and a non-inverted signal that is output from the first differential output buffer circuit is band-limited so that ringing of the signal waveform is suppressed, Ringing of the signal waveform into the first band limiting circuit that outputs the band limited non-inverted signal and the inverted signal output from the first differential output buffer circuit Ringing of the signal waveform is applied to the second band-limiting circuit that outputs the band-limited inverted signal and the non-inverted delay signal that is output from the second differential output buffer circuit. Ringing of the signal waveform is applied to the third band limiting circuit that outputs the band limited non-inverted delay signal and the inverted signal output from the second differential output buffer circuit. A band-limiting circuit that limits the band so as to be suppressed and outputs the band-limited inverted delay signal; a band-limited non-inverted signal output from the first band-limiting circuit; and the third band-limited A first OR circuit that performs a logical OR operation with the band-limited non-inverted delay signal output from the circuit and outputs a non-inverted OR signal obtained as a result, and is output from the first band-limited circuit. band A second OR circuit that performs an OR operation between the limited inverted signal and the band limited inverted delay signal output from the third band limiting circuit, and outputs the inverted OR signal obtained as a result; A logical sum output terminal for synthesizing the non-inverted logical sum signal output from the logical sum circuit and the inverted logical sum signal output from the second logical sum circuit and outputting a demodulated signal. Is a delay detection circuit.

  According to this configuration, ringing that causes ripples in the linearity of the FV conversion characteristics is suppressed, so that the linearity of the FV conversion characteristics during delay detection can be improved.

  In the delay detection circuit according to the present invention, it is desirable that the band limiting widths of the first and second band limiting circuits on the band limiting side of the non-delayed signal be a wide band width in which the ringing is not suppressed.

  According to this configuration, the rise time of the waveform of the signal that has not been delayed among the signals after band limitation can be increased, so that the signal generated by the logical sum operation of each subsequent logical sum circuit can be increased. Rise time can be increased. As a result, when the delay time of the FM modulation pulse signal is the same, the detection operation band can be expanded and improved while maintaining the linearity of the FV conversion characteristics.

  The delay detection circuit of the present invention is included in each of the non-inverted OR signal and the inverted OR signal output from the first and second OR circuits in the first and second OR circuits. Amplitude adjusting means capable of adjusting the amplitude of the carrier component to be adjusted, and the amplitude adjusting means adjusts the amplitude of the carrier component included in each of the non-inverted logical sum signal and the inverted logical sum signal to match. Is desirable.

  According to this configuration, since no amplitude difference occurs between the non-inverted OR signal and the inverted OR signal obtained by each OR operation, each carrier component can be completely canceled, so that the carrier component is removed, As a result, the SN ratio of the demodulated signal can be increased and improved.

  In the delay detection circuit of the present invention, it is desirable that the carrier component is a single unmodulated signal used in place of the FM modulated pulse signal.

  According to this configuration, it is possible to input an unmodulated signal to the delay detection circuit and improve the S / N ratio of the demodulated signal, which is suitable for shipping inspection and the like.

  In the delay detection circuit of the present invention, it is desirable that the carrier component is an FM modulation signal used in place of the FM modulation pulse signal.

  According to this configuration, it is possible to input an unmodulated signal to the delay detection circuit and improve the S / N ratio of the demodulated signal, which is suitable for shipping inspection and the like.

  More specifically, the delay detection circuit adjustment method described above includes a non-inverted OR signal output from the first OR circuit in the first and second OR circuits, and the first and second OR circuits. And adjusting the amplitude of the carrier signal included in each of the inverted OR signals output from the two OR circuits to match the amplitude of the carrier signal.

  According to this method, since there is no amplitude difference between the non-inverted OR signal and the inverted OR signal obtained by each OR operation, each carrier component can be completely canceled, so the carrier component is removed, As a result, the SN ratio of the demodulated signal can be increased and improved. Further, since a person can adjust the amplitude difference of each carrier wave component to improve the S / N ratio of the demodulated signal, it is suitable for various performance inspections such as a shipping inspection.

  The adjustment method of the delay detection circuit according to the present invention uses a single unmodulated signal instead of the FM modulated pulse signal. At this time, the first and second OR circuits use the first OR circuit. It is desirable to adjust so that the amplitude of the carrier wave signal included in each of the non-inverted OR signal output from the circuit and the inverted OR signal output from the second OR circuit is the same.

  According to this method, a person can input an unmodulated signal to the delay detection circuit to improve the S / N ratio of the demodulated signal, which is suitable for various performance inspections such as a shipping inspection.

  The method for adjusting a delay detection circuit according to the present invention uses an FM modulation signal instead of the FM modulation pulse signal. At this time, the first and second OR circuits output from the first OR circuit. It is desirable to adjust so that the amplitude of the carrier wave signal included in each of the non-inverted logical sum signal and the inverted logical sum signal output from the second logical sum circuit matches.

  According to this method, a person can input an unmodulated signal to the delay detection circuit to improve the S / N ratio of the demodulated signal, which is suitable for various performance inspections such as a shipping inspection.

  ADVANTAGE OF THE INVENTION According to this invention, the adjustment method of the delay detection circuit and delay detection circuit which can improve the detection operation band and SN ratio of a delay detection circuit can be provided.

  Embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments described below are examples of the present invention, and the present invention is not limited to the following embodiments. In the present specification and drawings, the same reference numerals denote the same components. In addition, a signal with various names having a symbol after the signal may be simply abbreviated as a signal with the corresponding symbol after.

(Embodiment)
FIG. 6 is a circuit configuration diagram of the delay detection circuit according to the embodiment of the present invention. The delay detection circuit 50 of the present embodiment is different from the conventional delay detection circuit 10 shown in FIG. 1 in that one of the non-inverting output terminal of the first differential output buffer circuit 12 and the first OR circuit 14. The first band limiting circuit 51 is connected between the first input terminal of the first differential output buffer circuit 12 and the other input terminal of the first OR circuit 14. The third band limiting circuit 53 is connected between the non-inverting output terminal of the second differential output buffer circuit 13 and one input terminal of the second OR circuit 15. A fourth band limiting circuit 54 is connected between the inverting output terminal of the second differential output buffer circuit 13 and the other input terminal of the second OR circuit 15, and further, the first OR circuit 14 includes a first amplitude adjusting unit 58 as an amplitude adjusting unit and a second OR circuit 15. In that a second amplitude adjustment unit 59 of the width adjusting means. Each of the band limiting circuits 51 to 54 is a filter such as a band limiting filter.

  The first band limiting circuit 51 applies a band limitation to the non-inverted signal 23 output from the first buffer circuit 12 so that ringing of the signal waveform is suppressed, and the band limiting non-inversion obtained by the band limitation is performed. The signal 63 is output to the first OR circuit 14.

  The second band limiting circuit 52 limits the band of the inverted signal 24 output from the first buffer circuit 12 so that ringing of the signal waveform is suppressed, and the band limited inverted signal 64 obtained by the band limitation. Is output to the second OR circuit 15.

  The third band limiting circuit 53 applies a band limitation to the non-inverted delay signal 26 output from the second buffer circuit 13 so that ringing of the signal waveform is suppressed, and the band limitation non-obtained by the band limitation is performed. The inverted delay signal 66 is output to the first OR circuit 14.

  The fourth band limiting circuit 54 applies a band limitation to the inverted delay signal 27 output from the second buffer circuit 13 so as to suppress ringing of the signal waveform, and a band limited inversion delay obtained by the band limitation. The signal 67 is output to the second OR circuit 15.

  Therefore, in the present embodiment, the first OR circuit 14 performs an OR operation on the band limited non-inverted signal 63 and the band limited non-inverted delay signal 66, and outputs the resulting non-inverted OR signal 68. Output to the side connection unit 17. The second OR circuit 15 performs an OR operation on the band limited non-inverted signal 66 and the band limited non-inverted delayed signal 67 and outputs the inverted OR signal 69 obtained as a result to the output side connection unit 17.

The first amplitude adjusting unit 58 adjusts the amplitude of the carrier wave component included in the non-inverted OR signal 68 output from the OR circuit 14 in the first OR circuit 14.
The second amplitude adjustment unit 59 adjusts the amplitude of the carrier wave component included in the inverted OR signal 69 output from the second OR circuit 15 in the second OR circuit 15.

  The first amplitude adjusting unit 58 and the second amplitude adjusting unit 59 can be adjusted so that the amplitudes of the carrier wave components included in each of the non-inverted OR signal 68 and the inverted OR signal 69 match. In this carrier wave component amplitude adjustment, for example, the amplitudes of the carrier components of the non-inverted logical sum signal 68 and the inverted logical sum signal 69 are automatically detected by a detection device (not shown), and a signal obtained as a result of this detection is sent to each of the amplitude adjusters 58 The process is fed back to 59 so that the amplitudes of both carrier components match.

Next, the operations of the improvement of the linearity of the FV conversion characteristics and the improvement of the detection operation band in the delay detection circuit 50 having such a configuration will be described together.
As shown in the waveform diagram of FIG. 7, first, the operation of the delay detection circuit 50 is such that the FM modulation pulse signal 21 from the outside is connected to the first differential output buffer circuit 12 and the signal delay circuit via the input side connection unit 16. 11 is input. In the signal delay circuit 11, the FM modulation pulse signal 21 is delayed by the delay time Td, and this delay signal 25 is input to the second differential output buffer circuit 13.

  In the first differential output buffer circuit 12, the non-inverted signal 23 is output from the non-inverting output terminal to the first band limiting circuit 51, and the inverted signal 24 is output from the inverting output terminal to the second band limiting circuit 52. The In the second differential output buffer circuit 13, the non-inverting delay signal 26 is output from the non-inverting output terminal to the third band limiting circuit 53, and the inverting delay signal 27 is output from the inverting output terminal to the fourth band limiting circuit 54. Is output.

  In the first band limiting circuit 51, the input non-inverted signal 23 is band-limited so that ringing of the signal waveform is suppressed, and this band-limited non-inverted signal 63 is sent to the first OR circuit 14. Is output. In the second band limiting circuit 52, the input inverted signal 24 is band-limited so that ringing of the signal waveform is suppressed, and this band limited inverted signal 64 is output to the second OR circuit 15. The In the third band limiting circuit 53, the input non-inverted delay signal 26 is band-limited so that ringing of the signal waveform is suppressed, and this band limited non-inverted delay signal 66 is used as the first OR circuit. 14 is output. In the fourth band limiting circuit 54, the input inverted delay signal 27 is band-limited so that ringing of the signal waveform is suppressed, and this band limited inverted delay signal 67 is sent to the second OR circuit 15. Is output.

The first OR circuit 14 performs an OR operation on the input band-limited non-inverted signal 63 and the band-limited non-inverted delay signal 66, and the resulting non-inverted OR signal 68 is output to the output side connection unit. 17 is output. In the second OR circuit 15, an OR operation is performed on the input band-limited non-inverted signal 66 and the band-limited non-inverted delay signal 67, and the resulting inverted OR signal 69 is output to the output side connection unit 17. Is output.
Then, in the output side connection unit 17, the demodulated signal 22 is obtained by combining the non-inverted OR signal 68 and the inverted OR signal 69.

  By the way, the cause of the ripple in the linearity of the FV conversion characteristic is that the output from the first differential output buffer circuit 12 and the second differential output buffer circuit 13 as described above with reference to FIG. This is because ringing occurs in the non-inverted signal 23 and the inverted signal 24 and the non-inverted delayed signal 26 and the inverted delayed signal 27.

  Therefore, in the delay detection circuit 50 of this embodiment, in order to suppress the ringing, each of the band limiting circuits 51 to 54 includes the non-inverted signal 23, the inverted signal 24, the non-inverted delayed signal 26, and the inverted delayed signal 27. The band was limited so that ringing was suppressed and the waveform was smoothed, so that overshoot and undershoot did not occur. This band limiting process will be further described with reference to FIG.

  FIG. 8 shows a band limit non-inverted signal 63 and a band limit non-inverted delay signal 66 output from the first band limit circuit 51 and a non-inverted OR signal 68 output from the first OR circuit 14. It is a waveform diagram. As can be seen from FIG. 8, when ringing as shown in FIG. 3 is eliminated from the respective waveforms of the band limited non-inverted signal 63, the band limited non-inverted delay signal 66, and the non-inverted OR signal 68 by the band limitation, The linearity of the conversion characteristic is improved.

  On the other hand, as shown by a section Tc between times t4 and t5 in FIG. 8, the falling time Tf and the rising time Tr of the waveform forming the “L” section of the non-inverted OR signal 68 also become longer (slower). As can be seen from the above equation (1), the detection operation band decreases. However, Tr = Tf.

  Further, as shown in FIG. 3, in the case of the non-inverted delay signal 26R, the ringing generated at the time t4 affects the rising Tr at the time t5 after the section Tc and must be completely removed. On the other hand, in the case of the non-inverted signal 23R, even if the ringing generated at time t3 remains until time t4, it does not affect the linearity of the FV conversion characteristics, and it only needs to converge by time t5. A wider band than that for the delay signal 26R can be set. The same applies to the inverted signal 24 output from the first OR circuit 14 and can be set to a wider band than the band limit width for the inverted delay signal 27 output from the second OR circuit 15. it can.

  Therefore, only the first and second band limiting circuits 51 and 52 to which the non-inverted signal 23 and the inverted signal 24 which are non-delayed signals are input are set as a wide band, and the wide band limiting circuits 51 and 52 are not inverted. If the signal 23 and the inverted signal 24 are band-limited, the rise time of the band-limited non-inverted signal 63 and the band-limited inverted signal 64 can be shortened. A waveform diagram at this time is shown in FIG. However, in FIG. 9, the band-limited non-inverted signal 63, the band-limited non-inverted delay signal 66, which are input / output signals to / from the first OR circuit 14 out of the first and second OR circuits 14 and 15, The waveform of the non-inverted OR signal 68 is shown as a representative. Further, the falling edge of the band limited non-inverted signal 63 is denoted by a symbol Tf1, the rising edge is denoted by Tr1, the falling edge of the band limited non-inverted delayed signal 66 is denoted by Tf2, and the rising edge is denoted by Tr2.

  As shown in FIG. 9, since the band limited non-inverted signal 63 is band-limited in a wide band, there is a possibility that ringing occurs as shown by a broken line. This is because the non-inverted OR signal 68 is generated as described above. It does not affect the formation of the “L” section indicated by Tc. Furthermore, since the band is limited in a wide band, as shown by the rising edges Tr1 and Tr2, the rising time can be made faster than that of the band limited non-inverted delay signal 66 that is band limited in a narrower band. Therefore, the time of the rising Tr at time t5 of the waveform forming the “L” section indicated by Tc of the non-inverted OR signal 68 can be shortened. The same applies to the band-limited inverted signal 64 and the inverted OR signal 69 not shown in the waveform diagram. As a result, when the delay time Td is the same, the detection operation band is improved while maintaining the linearity of the FV conversion characteristics.

Next, the operation of improving the S / N ratio of the demodulated signal in the delay detection circuit 50 will be described.
As shown in the waveform diagram of FIG. 7, in the same manner as described above, the first OR circuit 14 performs an OR operation on the band-limited non-inverted signal 63 and the band-limited non-inverted delay signal 66, and the non-result of this result is calculated. An inverted OR signal 68 is output. The second logical sum circuit 15 (not shown in the waveform diagram) performs a logical sum operation on the band limited non-inverted signal 66 and the band limited non-inverted delayed signal 67, and outputs the inverted logical sum signal 69 as a result.

  The non-inverted logical sum signal 68 and the inverted logical sum signal 69 are each composed of a hatched portion contributing to demodulation and carrier components inverted from each other. By synthesizing (adding) the carrier components inverted to each other at the output side connection unit 17, each carrier component is canceled because it has an opposite phase, and has a certain width at a position corresponding to the rise and fall times of the input FM modulation pulse signal 21. A pulse train of Td remains.

  However, if there is an amplitude difference between the non-inverted OR signal 68 and the inverted OR signal 69, the carrier component remains without being completely canceled. The carrier wave is used at a frequency considerably higher than that of the normal modulation signal. However, in the case of a broadband FM signal, the modulation signal may spread the spectrum of the carrier over a wide range and cover the carrier wave up to the modulation signal band. For this reason, if the carrier wave is not sufficiently removed, the SN ratio of the demodulated signal 22 remaining in the demodulated signal band as a residual FM signal is lowered and deteriorated.

  In the present embodiment, since the amplitude adjustment units 58 and 59 that can individually adjust the output amplitude are provided in each of the OR circuits 14 and 15, the non-inverted OR signal 68 and the inversion are performed by the amplitude adjustment units 58 and 59. Adjustment is made so that the amplitudes of the carrier wave components included in each of the OR signals 69 coincide. In other words, the residual FM signal is removed by adjusting the amplitude of each carrier spectrum to be the minimum, thereby increasing the S / N ratio of the demodulated signal 22.

  According to the delay detection circuit 50 of this embodiment as described above, the FM modulation pulse signal 21 input from the outside is non-inverted and inverted by the first differential output buffer circuit 12 to be non-inverted signal 23 and inverted signal. 24, and the delay signal 25 delayed by the delay time Td by the signal delay circuit 11 is non-inverted and inverted by the second differential output buffer circuit 13 to output a non-inverted delay signal 26 and an inverted delay signal 27. . These output signals 23, 24, 26, and 27 are band-limited so that ringing of the signal waveform is suppressed by the band-limiting circuits 51 to 54 that are associated in advance. The band-limited non-inverted signal 63 and the band-limited non-inverted delay signal 66 thus obtained are logically ORed by the first OR circuit 14 to output a non-inverted OR signal 68. The limited inverted delay signal 67 is ORed by the second OR circuit 15 to output an inverted OR signal 69. Then, the output side connection unit 17 combines the non-inverted OR signal 28 and the inverted OR signal 29 to obtain the demodulated signal 22.

  Accordingly, ringing, which is a cause of occurrence of ripples in the linearity of the FV conversion characteristics, is suppressed, so that the linearity of the FV conversion characteristics during delay detection can be improved.

  Further, the band limiting widths of the first and second band limiting circuits 51 and 52 that limit the band of the non-delay side signals 23 and 24 are wide bands in which ringing is not suppressed. As a result, the rise time of the waveform of the signal 63, 64 which is not delayed among the band-limited signals can be shortened, so that it is generated by the logical sum operation of the subsequent logical sum circuits 14, 15. The rise time for forming the “L” section of the signals 68 and 69 can be made faster. As a result, when the delay time Td is the same, the detection operation band can be expanded and improved while maintaining the linearity of the FV conversion characteristics.

  The first and second OR circuits 14 and 15 adjust the amplitude of the carrier wave component included in each of the non-inverted OR signal 68 and the inverted OR signal 69 output from the OR circuits 14 and 15. Possible first and second amplitude adjustment units 58 and 59 are provided, and each amplitude adjustment unit 58 and 59 matches the amplitude of the carrier component included in each of the non-inverted OR signal 68 and the inverted OR signal 69. Adjustment was made.

  As a result, there is no difference in amplitude between the non-inverted logical sum signal 68 and the inverted logical sum signal 69, so that each carrier component can be completely canceled. Therefore, even when the carrier wave spectrum is spread over a wide range by the modulation signal as in the case of the broadband FM signal and the carrier wave covers up to the modulation signal band, the carrier wave can be canceled and sufficiently removed. No longer remains. That is, the residual FM signal is removed by adjusting the amplitude of each carrier spectrum to be the minimum, whereby the SN ratio of the demodulated signal 22 can be increased and improved.

  In addition, as a mechanism in which each amplitude adjustment unit 58, 59 can be manually adjusted by an amplitude, a signal waveform display device (not shown) is connected to the output side connection unit 17, and a non-inverted OR signal 68 is connected to this signal waveform display device. And the amplitude of both carrier components of the inverted OR signal 69 are displayed, and the person adjusts the amplitudes to match with each of the amplitude adjusters 58 and 59 while checking the displayed amplitudes. It may be. Also in this case, each carrier wave component can be completely canceled to improve the S / N ratio of the demodulated signal 22.

  In addition to this, a single unmodulated signal is input to the delay detection circuit 50 instead of the FM modulated pulse signal 21, and the signal waveform at the output side connection unit 17 is displayed on the signal waveform display device in the same manner as described above. By adjusting the amplitudes of the signals having the same frequency as that of the input unmodulated signal by the amplitude adjusting units 58 and 59, the residual FM signal can be removed and the S / N ratio of the demodulated signal 22 can be improved. . Further, even if the FM modulation signal is input to the delay detection circuit 50 instead of the FM modulation pulse signal 21, the residual FM signal can be removed by the same adjustment as described above, and the SN ratio of the demodulated signal 22 can be improved. The adjustment using the single unmodulated signal or the FM modulated signal as an input signal can be applied even when the amplitude adjusting units 58 and 59 are automatically performed as described above. This adjustment method can input an unmodulated signal or an FM modulated signal to the delay detection circuit 50 to improve the S / N ratio of the demodulated signal 22 and is therefore suitable for shipping inspection, inspection at the time of failure, and the like.

(Example)
Next, it is a circuit block diagram of the delay detection circuit 70 according to the embodiment of the present invention. The delay detection circuit 70 specifically includes the first to fourth band limiting circuits 51 to 54 and the first and second OR circuits 14 and 15 in the delay detection circuit 50 of the above-described embodiment as electronic circuits. It is a replaced circuit.

The first differential output buffer circuit 12 shown in FIG. 10 includes an input differential output buffer circuit 12k, transistors 71a and 72a, a current source 73a, and resistors 74a and 75a.
The first and second band limiting circuits 51 and 52 include resistors 76a and 77a and capacitors 78a and 79a. However, the resistors 74 a, 75 a, 76 a, 77 a connected to the power supply Vcc are shared with the first differential output buffer circuit 12.

  In the first differential output buffer circuit 12, the base end of the transistor 71a is connected to the inverting output terminal of the input differential output buffer circuit 12k, and the base end of the transistor 72a is non-inverted of the input differential output buffer circuit 12k. Connected to the output terminal. The transistor 71a has a collector end connected to the power supply Vcc via a resistor 74a, an emitter end connected to the ground via a current source 73a, and the transistor 72a also has a collector end connected to the power supply Vcc via a resistor 75a. The emitter end is grounded via the current source 73a.

  In the second differential output buffer circuit 13, the base end of the transistor 71b is connected to the inverting output terminal of the input differential output buffer circuit 13k, and the base end of the transistor 72b is non-inverted of the input differential output buffer circuit 13k. Connected to the output terminal. The transistor 71b has a collector end connected to the power source Vcc via a resistor 74b, an emitter end connected to the ground via a current source 73b, and the transistor 72b also has a collector end connected to the power source Vcc via a resistor 75b. The emitter end is grounded via the current source 73b.

  In the first band limiting circuit 51, one end of the resistor 76a is connected to a connection portion between the collector end of the transistor 71a of the first differential output buffer circuit 12 and the resistor 74a, and the other end of the resistor 76a is a capacitor. It is grounded through 78a. That is, the resistor 76a and the capacitor 78a constitute a low-pass filter using an RC circuit.

  In the second band limiting circuit 52, one end of the resistor 77a is connected to a connection portion between the collector end of the transistor 72a of the first differential output buffer circuit 12 and the resistor 75a, and the other end of the resistor 77a is a capacitor. It is grounded through 79a. That is, the resistor 77a and the capacitor 79a constitute a low-pass filter.

  In the third band limiting circuit 53, one end of the resistor 76b is connected to a connection portion between the collector end of the transistor 71b of the second differential output buffer circuit 13 and the resistor 74b, and the other end of the resistor 76b is a capacitor. It is grounded through 78b. That is, the resistor 76b and the capacitor 78b constitute a low-pass filter.

  In the fourth band limiting circuit 54, one end of the resistor 77b is connected to a connection portion between the collector end of the transistor 72b of the second differential output buffer circuit 13 and the resistor 75b, and the other end of the resistor 77b is a capacitor. It is grounded through 79b. That is, the resistor 77b and the capacitor 79b constitute a low-pass filter.

  The collector terminals of the input side transistors 81a to 84a of the first OR circuit 14 are connected to the power source Vcc, the emitter terminal of the input side transistor 81a is grounded via the current source 86a, and the emitter of the input side transistor 82a. The end is grounded via a current source 87a. The emitter end of the input side transistor 83a is grounded via the variable current source 88a, and the base end is connected to the emitter end of the input side transistor 81a. The emitter end of the input side transistor 84a is grounded via the variable current source 88a, and the base end is connected to the emitter end of the input side transistor 82a.

  Further, the emitter end of the output side transistor 85a is grounded via the variable current source 88a, the base end is grounded via the voltage source 89a, and the collector end is connected to the power source Vcc via the output side connecting portion 17 and the resistor 18. It is connected. Further, the first amplitude adjusting unit 58 is configured by connecting an amplitude adjusting terminal to the current control terminal of the variable current source 88a.

  The collector terminals of the input side transistors 81b to 84b of the second OR circuit 15 are connected to the power source Vcc, the emitter terminal of the input side transistor 81b is grounded via the current source 86b, and the emitter of the input side transistor 82b. The end is grounded via a current source 87b. The emitter end of the input side transistor 83b is grounded via the variable current source 88b, and the base end is connected to the emitter end of the input side transistor 81b. The emitter end of the input side transistor 84b is grounded via the variable current source 88b, and the base end is connected to the emitter end of the input side transistor 82b.

  Further, the emitter end of the output side transistor 85b is grounded via the variable current source 88b, the base end is grounded via the voltage source 89b, and the collector end is connected to the power source Vcc via the output side connecting portion 17 and the resistor 18. It is connected. In addition, the second amplitude adjustment unit 59 is configured by connecting an amplitude adjustment terminal to the current control terminal of the variable current source 88b.

The operation of the delay detection circuit 70 having such a configuration will be described.
First, in the first differential output buffer circuit 12, the input inverted signal 23k is input from the input differential output buffer circuit 12k to the base end of the transistor 71a, and the input non-inverted signal 24k is input to the base end of the transistor 72a. When input, a constant current determined by the current source 73a flows between the collectors and emitters of the transistors 71a and 72a, whereby the input inverted signal 23k is inverted to become the non-inverted signal 23, and the input non-inverted signal 24k becomes the inverted signal 24 inverted.

  In the non-inverted signal 23, the high-frequency line segment is removed by the low pass filter of the resistor 76a and the capacitor 78a of the first band limiting circuit 51, and the low frequency component is output as the band limited non-inverted signal 63 to the base end of the transistor 81a. Is done. From the inverted signal 24, the high frequency line segment is removed by the low pass filter of the resistor 77a and the capacitor 79a of the second band limiting circuit 52, and the low frequency component is output as the band limited non-inverted signal 64 to the base end of the transistor 81b. .

  Next, in the second differential output buffer circuit 13, the input non-inverted signal 26k is input from the input differential output buffer circuit 13k to the base end of the transistor 71b, and the input inverted signal 27k is input to the base end of the transistor 72b. , A constant current determined by the current source 73b flows between the collectors and emitters of the transistors 71b and 72b. As a result, the input non-inverted signal 26k is inverted to become the non-inverted signal 26. The signal 27k is an inverted signal 27 that is inverted.

  In the non-inverted signal 26, the high frequency line segment is removed by the low pass filter of the resistor 76b and the capacitor 78b of the third band limiting circuit 53, and the low frequency component is output to the base terminal of the transistor 82a as the band limited non-inverted signal 66. Is done. From the inverted signal 27, the high frequency line segment is removed by the low pass filter of the resistor 77b and the capacitor 79b of the fourth band limiting circuit 54, and the low frequency component is output as the band limited non-inverted signal 67 to the base end of the transistor 82b. .

  In the first OR circuit 14, when the band-limited non-inverted signal 63 is input to the base terminal of the input-side transistor 81a and the band-limited non-inverted delay signal 66 is input to the base terminal of the input-side transistor 82a, A constant current determined by the current sources 86a and 87a flows between the collectors and emitters of the side transistors 81a and 82a, whereby a predetermined current is input to the base ends of the other input side transistors 83a and 84a.

  A constant current determined by the current adjustment value of the variable current source 88a flows between the collectors and emitters of the input side transistors 83a and 84a which are turned on by this input. At this time, a predetermined power supply is supplied from the voltage source 89a to the base end. Between the collector and emitter of the output-side transistor 85a being performed, a current having a phase opposite to that of the collector-emitter current of the input-side transistors 83a and 84a having a differential circuit flows, and thereby non-inverted to the output-side connection portion 17. A logical sum signal 68 is output.

  In the second OR circuit 15, when the band limited inverted signal 64 is input to the base end of the input side transistor 81b and the band limited inverted delay signal 67 is input to the base end of the input side transistor 82b, each input side transistor A constant current determined by the current sources 86b and 87b flows between the collectors and emitters of 81b and 82b, whereby a predetermined current is input to the base ends of the other input side transistors 83b and 84b.

  A constant current determined by the current adjustment value of the variable current source 88b flows between the collectors and emitters of the input side transistors 83b and 84b which are turned on by this input. At this time, a predetermined power supply is supplied from the voltage source 89b to the base end. A current having a phase opposite to that of the collector-emitter current of the input-side transistors 83b and 84b in the differential circuit flows between the collector-emitter of the output-side transistor 85b that is being performed. A sum signal 69 is output.

In the output side connection unit 17, the non-inverted logical sum signal 68 and the inverted logical sum signal 69 are combined and the demodulated signal 22 is output.
At this time, if there is a difference between the amplitudes of the carrier components of the non-inverted logical sum signal 68 and the inverted logical sum signal 69, the adjustment values of the variable current sources 88a and 88b are changed by the amplitude adjusters 58 and 59, respectively. The amplitude is adjusted to match. As a result, a demodulated signal 22 having a high S / N ratio is obtained.

  In the delay detection circuit 70 of this embodiment, the logical sum operation circuit of each of the logical sum circuits 14 and 15 has a general circuit configuration. However, the non-inverted logical sum signal 68 and the result of the logical sum operation are the same. The inverted OR signal 69 is easily added as a current output. The current sources that determine the output amplitudes of the OR circuits 14 and 15 are variable current sources 88a and 88b that can be finely adjusted. An amplitude adjustment terminal is connected to these current control terminals to connect the amplitude adjustment units 58 and 58 to each other. 59 is configured.

  Further, as each of the band limiting circuits 51 to 54, a low-pass filter using an RC circuit is used as will be described on behalf of the first and second band limiting circuits 51 and 52. Further, the resistors 76a and 77a can be omitted by using the time constants of the collector resistors 74a and 75a and the capacitors 78a and 79a of the differential circuit having the pair of transistors 71a and 71b.

  The capacitors 78a and 79a can also use distributed constant circuits based on wiring patterns. In particular, regarding the first and second band limiting circuits 51 and 52 on the non-delay side, the values of the resistance R and the capacitance C may be extremely small, and the parasitic resistance and parasitic capacitance of the layout may be substituted. .

  The delay detection circuit and the adjustment method of the delay detection circuit of the present invention are widely applied to various communication devices such as telephone devices and various electronic and electrical devices such as video devices.

It is a circuit block diagram of the conventional delay detection circuit. It is a waveform diagram of a non-inverted signal, a non-inverted delayed signal, and a non-inverted OR signal in a conventional delay detection circuit. It is a waveform diagram of a non-inverted signal, a non-inverted delay signal, and a non-inverted OR signal in a ringing occurrence state in a conventional delay detection circuit. It is a specific circuit diagram of an OR circuit in a conventional delay detection circuit. It is a figure which shows the FV conversion characteristic curve in the conventional delay detection circuit. 1 is a circuit configuration diagram of a delay detection circuit according to an embodiment of the present invention. FIG. It is a wave form diagram for explanation of operation of a delay detection circuit of an embodiment. 4 is a waveform diagram of a band limited non-inverted signal, a band limited non-inverted delayed signal, and a non-inverted OR signal in the delay detection circuit of the embodiment. FIG. Waveforms of a band-limited non-inverted signal and a band-limited non-inverted delay signal when the band limit width of the non-delay side signal in the delay detection circuit of the embodiment is wide, and a non-inverted OR signal output from the OR circuit FIG. It is a circuit block diagram of the delay detection circuit based on the Example of this invention.

Explanation of symbols

10, 50, 70: delay detection circuit 11: signal delay circuit 12: first differential output buffer circuit 13: second differential output buffer circuit 14: first OR circuit 15: second OR circuit 16: Input side connection unit 17: Output side connection unit 21: FM modulation pulse signal 23: Non-inversion signal 24: Inversion signal 25: Delay signal 26: Non-inversion delay signal 27: Inversion delay signal 28: Non-inversion OR signal 29 : Inverted OR signals 31, 32, 81a to 84a, 81b to 84b: Input side transistors 33, 85a, 85b: Output side transistors 18, 34, 74a to 77a, 74b to 77b: Resistors 35, 73a, 73b, 86a ˜88a, 86b˜88b: current sources 36, 89a, 89b: voltage sources 37, 38: input base terminals 71a, 72a, 71b, 72b: transistor 39: logical sum output Child 42: FV conversion characteristic curve 51: first band limiting circuit 52: second band limiting circuit 53: third band limiting circuit 54: fourth band limiting circuit 58: first amplitude adjusting unit 59: first 2 Amplitude adjustment unit 63: Band-limited non-inverted signal 64: Band-limited inverted signal 66: Band-limited non-inverted delay signal 67: Band-limited inverted signal 68: Non-inverted OR signal 69: Inverted OR signal

Claims (8)

A first differential output buffer circuit that receives an FM modulated pulse signal that is a frequency-modulated pulse signal and outputs an inverted signal obtained by inverting the FM modulated pulse signal and a non-inverted signal that is not inverted;
A signal delay circuit that receives the FM modulated pulse signal and outputs a delayed signal obtained by delaying the FM modulated pulse signal for a predetermined time;
A second differential output buffer circuit that outputs an inverted delay signal obtained by inverting the delayed signal output from the signal delay circuit and a non-inverted delayed signal that is not inverted;
A first band-limiting circuit that applies a band limitation to the non-inverted signal output from the first differential output buffer circuit so that ringing of the signal waveform is suppressed, and outputs the band-limited non-inverted signal;
A second band limiting circuit that limits the band of the inverted signal output from the first differential output buffer circuit so that ringing of the signal waveform is suppressed, and outputs the band limited inverted signal;
A third band limiting circuit that limits the band of the non-inverted delay signal output from the second differential output buffer circuit so as to suppress ringing of the signal waveform and outputs the band limited non-inverted delay signal. When,
A fourth band limiting circuit that limits the band of the inverted signal output from the second differential output buffer circuit so that ringing of the signal waveform is suppressed, and outputs the band limited inverted delay signal;
A logical sum operation is performed on the band-limited non-inverted signal output from the first band-limited circuit and the band-limited non-inverted delayed signal output from the third band-limited circuit, and the resulting non-inverted logical sum A first OR circuit for outputting a signal;
Performs a logical OR operation on the band limited inverted signal output from the first band limiting circuit and the band limited inverted delay signal output from the third band limiting circuit, and outputs the resulting inverted OR signal A second logical sum circuit,
A logical sum output terminal for combining the non-inverted logical sum signal output from the first logical sum circuit and the inverted logical sum signal output from the second logical sum circuit and outputting a demodulated signal;
A delay detection circuit comprising:   2. The delay detection according to claim 1, wherein a bandwidth limitation width of the first and second bandwidth limitation circuits on the bandwidth-limiting side of the non-delayed signal is a bandwidth that does not suppress the ringing. circuit. The amplitude of the carrier component included in each of the non-inverted OR signal and the inverted OR signal output from the first and second OR circuits can be adjusted in the first and second OR circuits. Equipped with a simple amplitude adjusting means,
3. The delay detection circuit according to claim 1, wherein the amplitude adjustment unit adjusts the amplitude of a carrier wave component included in each of the non-inverted logical sum signal and the inverted logical sum signal to match. .   4. The delay detection circuit according to claim 3, wherein the carrier wave component is a single unmodulated signal used in place of the FM modulated pulse signal.   The delay detection circuit according to claim 3, wherein the carrier wave component is an FM modulation signal used instead of the FM modulation pulse signal. A method for adjusting a delay detection circuit according to claim 1 or 2,
Included in each of the non-inverted OR signal output from the first OR circuit and the inverted OR signal output from the second OR circuit in the first and second OR circuits. A method for adjusting a delay detection circuit, wherein the adjustment is performed so that the amplitudes of carrier wave signals coincide with each other.   A single unmodulated signal is used in place of the FM modulated pulse signal. At this time, in the first and second OR circuits, a non-inverted OR signal output from the first OR circuit and The method of adjusting a delay detection circuit according to claim 6, wherein the carrier wave signal included in each of the inverted OR signal output from the second OR circuit is adjusted to have the same amplitude. .   An FM modulation signal is used instead of the FM modulation pulse signal. At this time, in the first and second OR circuits, a non-inverted OR signal output from the first OR circuit, 7. The method of adjusting a delay detection circuit according to claim 6, wherein the adjustment is performed so that the amplitude of the carrier signal included in each of the inverted OR signals output from the two OR circuits matches.

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