JP2009277776A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size of a semiconductor device with a high breakdown voltage without lowering the breakdown voltage. <P>SOLUTION: The semiconductor device has a drain drift region including a RESURF region formed on a semiconductor substrate, the drain drift region having a lower surface in a wave shape in a gate length direction. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a semiconductor device including a drain drift region including a RESURF region that relaxes electric field concentration on a surface and has a high breakdown voltage, and a method for manufacturing the same.

For example, a high breakdown voltage semiconductor device is used for power applications. Examples of such semiconductor devices are reported in US Pat. Nos. 4,300,150 and 4,811,075 (Patent Documents 1 and 2). FIG. 5 shows a schematic cross-sectional view of the high breakdown voltage semiconductor device described in these specifications. FIG. 5 is a schematic cross-sectional view of a high breakdown voltage lateral MOS transistor having a drain drift region including a general resurf region.
In FIG. 5, the drain drift region 2 is provided on the surface layer of the semiconductor substrate 1, and the drain region 9 and the drain electrode 10 in contact with the drain region 9 are formed in the drain drift region 2. A body region 4 serving as a channel region is formed in a direction opposite to the drain region 9, and a source region 8 and a source electrode 11 in contact with the source region 8 and the body diffusion layer 4 are formed in the body region 4. . 3 is an insulating film, 6 is a gate insulating film, 7 is a gate electrode, and 12 is an interlayer insulating film.

Furthermore, a resurf region 5 having a conductivity type opposite to that of the drain drift region 2 is formed under the insulating film 3 on the drain drift region 2.
In the high breakdown voltage semiconductor device, by providing the RESURF region 5 on the surface of the drain drift region 2, the electric field concentration near the surface can be relaxed. Therefore, the depletion layer from the end of the source region generated with the voltage applied to the drain electrode 10 can be sufficiently expanded in the drain drift region 2. As a result, a high breakdown voltage of the semiconductor device can be realized.

U.S. Pat. No. 4,300,150 U.S. Pat. No. 4,811,075

The breakdown voltage of a semiconductor device having a drain drift region including such a resurf region is determined by the impurity concentration of the semiconductor substrate, the diffusion depth and concentration of the drain drift region and the resurf region, and the length of the drain drift region.
For example, the dotted line in FIG. 4 shows the relationship between the width of the insulating film on the drain drift region and the breakdown voltage in the conventional semiconductor device. FIG. 4 shows that the withstand voltage rapidly decreases as the insulating film width becomes shorter. A shorter insulating film width means a shorter drain drift region.
Therefore, if a certain level of breakdown voltage is to be ensured, the required insulating film width is determined, and therefore the length (pitch) between the drain region and the source region cannot be reduced. As a result, there is a problem that the size of the semiconductor device cannot be reduced. Further, this problem becomes significant when the channel width is increased in order to reduce the on-resistance of the semiconductor device.

Thus, according to the present invention, the source region and the drain region of the second conductivity type formed in the surface layer of the semiconductor substrate of the first conductivity type,
An insulating film formed on the drain region side semiconductor substrate so that the source region side semiconductor substrate is exposed between the source region and the drain region; and
A gate insulating film formed on the exposed semiconductor substrate and a gate electrode thereon;
A first conductivity type resurf region formed in a surface layer of a semiconductor substrate under the insulating film;
A second conductivity type drain drift formed in the surface layer of the semiconductor substrate so as to cover the lower surface of the RESURF region and having two or more corrugated lower surface-shaped diffusion regions in the gate length direction. A semiconductor device including a high breakdown voltage semiconductor device including a region is provided.

According to the present invention, there is provided a method for manufacturing the semiconductor device,
A second conductivity type drain drift region having two or more corrugated lower surface shaped diffusion regions in the surface layer of the first conductivity type semiconductor substrate and in the gate length direction is formed by ion implantation. Process,
Forming an insulating film on the drain drift region and so that the semiconductor substrate is exposed on the source region side;
Forming a first conductivity type RESURF region in the surface layer of the semiconductor substrate under the insulating film and in the drain drift region by ion implantation through the insulating film;
Forming a gate insulating film and a gate electrode in this order on the exposed semiconductor substrate;
Forming a source region and a drain region in a surface layer of the semiconductor substrate by ion implantation using the gate electrode and the insulating film as a mask, and the drain drift region is formed on the semiconductor substrate. There is provided a method for manufacturing a semiconductor device, characterized by being formed by ion implantation through a resist pattern having the same number of openings as the diffusion region having a bottom surface shape.

  By forming the drain drift region in a wave shape from the drain region to the source region, the length of the effective drain drift region can be increased. In other words, it is possible to realize the length of the drain drift region necessary for ensuring the breakdown voltage with a short insulating film width. Therefore, the same withstand voltage as in the prior art can be obtained with a short insulating film width. As a result, the length (pitch) between the drain region and the source region can be shortened, and a semiconductor device with a high breakdown voltage and a reduced size can be provided.

One feature of the semiconductor device of the present invention is that the drain drift region has two or more corrugated lower surface-shaped diffusion regions in the gate length direction. By having such a lower surface-shaped diffusion region, the length of the effective drain drift region in the gate length direction can be increased. As a result, the breakdown voltage can be improved if the drain drift region has the same length as the conventional semiconductor device, and the size of the device can be reduced if the breakdown voltage is the same.
FIGS. 3A and 3B are schematic explanatory diagrams showing why the length of the effective drain drift region can be increased. FIG. 3A shows a case where the drain drift region has two corrugated bottom surface-shaped diffusion regions. FIG. 3B shows a case where the drain drift region has a conventional linear bottom-surface shaped diffusion region.

  From FIG. 3A, by forming the drain drift region from two locations by diffusion, the isoconcentration line α of the drain drift region can be wave-shaped. As a result, the isoconcentration line α in FIG. 3A becomes longer than the linear isoconcentration line α in FIG. 3B, and the effective drain drift region can be lengthened. Note that FIG. 3C shows a case where a RESURF region having two corrugated lower surface-shaped diffusion regions is provided, but the effective drain drift region length is set as in FIG. It has been shown that it can be long. In the figure, 2x and 5x mean the lower surfaces of the drain drift region and the RESURF region, respectively.

  Hereinafter, the semiconductor device of the present invention will be described in more detail. The semiconductor device of the present invention may include other elements as long as it includes a high voltage semiconductor device. Examples of other elements include low breakdown voltage semiconductor devices (eg, logic transistors, memories, etc.), resistors, capacitors, and the like. Here, the high breakdown voltage means 100 V or more, and the low breakdown voltage means less than 100 V.

  Examples of semiconductor substrates that can be used in the present invention include bulk substrates made of elemental semiconductors such as silicon and germanium, and compound semiconductors such as silicon germanium, GaAs, InGaAs, ZnSe, and GaN. In addition, as the semiconductor layer on the surface, various substrates such as an SOI (Silicon on Insulator) substrate, an SOS substrate, or a multilayer SOI substrate, or a semiconductor layer on a glass or plastic substrate may be used. Among these, a silicon substrate or an SOI substrate having a silicon layer formed on the surface is preferable. The semiconductor substrate or semiconductor layer has some amount of current flowing through it, but may be single crystal (for example, by epitaxial growth), polycrystalline, or amorphous.

The semiconductor substrate has the first conductivity type. The first conductivity type is n-type or p-type. The impurity concentration of the semiconductor substrate is not particularly limited. For example, when the impurity is boron, it is about 6E + 13 to 3E + 14 / cm ³ . Further, the semiconductor substrate may include a second conductivity type well region. The second conductivity type is p-type when the first conductivity type is n-type, and n-type when it is p-type. The impurity concentration in the well region is not particularly limited. For example, when the impurity is phosphorus, it is about 8E + 15 to 2E + 16 / cm ³ .

Next, a source region and a drain region of the second conductivity type are formed in the surface layer of the first conductivity type semiconductor substrate (in the case of having a well region, the surface layer of the well region). The impurity concentration of the source region and the drain region is not particularly limited. For example, when the impurity is As, it is about 2E + 20 to 1E + 21 / cm ³ .
A body region of the first conductivity type may be provided so as to cover the lower surface of the source region. By providing the body region, characteristics such as a threshold voltage of the semiconductor device can be set more freely. The impurity concentration in the body region is not particularly limited. For example, when the impurity is boron, it is about 5E + 16 to 2E + 17 / cm ³ .

  Next, an insulating film is formed on the semiconductor substrate on the drain region side so that the semiconductor substrate on the source region side is exposed between the source region and the drain region. A LOCOS film may be used for this insulating film. If the LOCOS film is used, the insulating film in the high voltage semiconductor device can be formed simultaneously with the formation of the LOCOS film for isolating other elements, and the manufacturing process can be shortened.

  Further, a gate insulating film is formed on the exposed semiconductor substrate. The gate insulating film is not particularly limited as long as it is usually used in a semiconductor device. For example, an insulating film such as a silicon oxide film or a silicon nitride film; an aluminum oxide film, a titanium oxide film, or a tantalum oxide. A single-layer film or a laminated film of a high dielectric film such as a film or a hafnium oxide film can be used. Of these, a silicon oxide film is preferable. For example, the gate insulating film is suitably about 10 to 100 nm, preferably about 20 to 60 nm (in terms of gate oxide film).

A gate electrode is formed on the gate insulating film. The gate electrode is not particularly limited as long as it is usually used in a semiconductor device, and conductive film, for example, polysilicon: metal such as copper and aluminum: refractory metal such as tungsten, titanium, and tantalum: Examples thereof include a single layer film or a laminated film such as silicide of a refractory metal. The film thickness of the gate electrode is suitably about 200 to 500 nm, for example.
Furthermore, the gate electrode may extend on the insulating film as long as it exists on the gate insulating film. If it extends over the insulating film, it is not necessary to form a separate contact region in order to form a contact to the gate electrode, and the area of the semiconductor device can be reduced.

  Next, a first conductivity type RESURF region is formed in the surface layer of the semiconductor substrate below the insulating film. Similar to the drain drift region, the RESURF region may have two or more corrugated lower surface-shaped diffusion regions in the gate length direction, and the lower surface shape may be linear as in the conventional case. When the RESURF region also has a corrugated lower surface shape, the effective length of the RESURF region can be increased, so that a semiconductor device with a high breakdown voltage and a reduced size can be provided. When it has a corrugated lower surface shape, the diffusion regions constituting the corrugation may or may not overlap.

When the RESURF region has a corrugated lower surface shape, the number of diffusion regions constituting the corrugation is two or more, and it is preferable to increase as much as possible in order to increase the effective drain drift length. However, since there is a problem that the on-resistance increases when the number is increased, about 5 to 10 is more preferable.
For example, when the impurity is boron, the impurity concentration in the RESURF region is preferably about 2E + 16 to 5E + 16 / cm ³ .

  Next, a drain drift region of the second conductivity type is formed in the surface layer of the semiconductor substrate so as to cover the lower surface of the RESURF region. This drain drift region has two or more corrugated bottom surface shaped diffusion regions in the gate length direction. Here, the diffusion regions constituting the corrugation may or may not overlap with each other, but they are preferably overlapped from the viewpoint of increasing the effective length of the drain drift region.

In the drain drift region, the number of diffusion regions constituting the waveform is two or more. In order to increase the effective drain drift length, it is preferable to increase it as much as possible. Since there also exists a problem that resistance becomes high, about 5-10 are preferable.
Furthermore, when the RESURF region has a corrugated lower surface shape, the number of diffusion regions constituting the drain drift region may be the same as or different from the RESURF region.
For example, when the impurity is phosphorus, the impurity concentration in the drain drift region is preferably about 8E + 15 to 2E + 16 / cm ³ .
In the above description, boron and phosphorus are used as impurities. However, other impurities can be used by appropriately adjusting the impurity concentration in order to achieve desired performance.

In the semiconductor device of the present invention, for example, a step of forming a second conductivity type drain drift region in a surface layer of a first conductivity type semiconductor substrate by ion implantation;
Forming an insulating film on the drain drift region and exposing the semiconductor substrate on the source region side;
Forming a resurf region of the first conductivity type under the insulating film and in the surface layer of the semiconductor substrate in the drain drift region by ion implantation through the insulating film;
A gate insulating film and a gate electrode can be formed on the exposed semiconductor substrate in this order.

In the manufacturing method of the semiconductor device of the present invention, except for the drain drift region and the RESURF region having a corrugated lower surface shape, it can be formed by a known method.
The drain drift region and the RESURF region can be formed by forming a resist pattern having openings corresponding to the number of diffusion regions by a known photolithography method and ion-implanting using the resist pattern as a mask.
The present invention will be further described below with reference to embodiments.

Embodiment An embodiment of the present invention will be described with reference to FIGS. 1 and 2A to 2E. FIG. 1 is a schematic cross-sectional view of the semiconductor device of the present invention, and FIGS. 2A to 2E are schematic process cross-sectional views of the semiconductor device of FIG.
First, on the well region 1 formed in the surface layer of the semiconductor substrate (p-type silicon substrate having a specific resistance of 50 Ω · cm), four openings are formed in a stripe shape along the gate width direction by a known photolithography method. The provided resist pattern a is formed. The number of openings in the resist pattern a corresponds to the number of corrugated shapes in the drain drift region formed in the direction from the drain region 9 to the source region 8 (gate length direction) formed in the subsequent steps. Yes. Ion implantation is performed using the resist pattern a as a mask (FIG. 2A). In the figure, b indicates a thermal oxide film (thickness 20 nm), and an arrow indicates ion implantation. The ion implantation species is phosphorus, the dose is in the range of 3-8E + 12 ions / cm ² , and the ion implantation energy is 150 KeV. The width and interval of the openings are 12 μm (x1), 4 μm (x2), 7 μm (x3), 4 μm (x4), 7 μm (x5), and 4 μm (x6) from the left side of FIG. .

  Next, after removing the resist pattern a, diffusion is performed at 1150 to 1200 ° C. (for example, about 1200 ° C. for about 10 hours) so that the ends of adjacent ion implantation regions overlap, thereby forming a wave-shaped well. A drain drift region 2 (2a, 2b, 2c, 2d) having a junction surface with the diffusion layer is formed (FIG. 2B). The diffusion depth of the drain drift region is 10 μm.

Next, a LOCOS film (silicon oxide film) 3 is formed in the drain drift region 2 by a known method.
Next, a resist pattern c having four openings in a stripe shape along the gate width direction is formed on the LOCOS film 3 by a known photolithography method. The openings of the resist pattern c correspond to the number of corrugated shapes of the RESURF region formed in the direction from the drain region 9 to the source region 8 (gate length direction) formed in the subsequent steps. Ion implantation is performed using the resist pattern c as a mask (FIG. 2C). In the figure, the arrow means ion implantation. The ion implantation species is boron, the dose is in the range of 2-4E + 12 ions / cm ² , and the ion implantation energy is 600 KeV. Note that the width (y1, y3, y5, y7) and the interval (y2, y4, y6) of the openings are 9 μm and 2 μm.

Further, ion implantation for forming a body region is performed on the source region 8 side formed in the subsequent steps. The ion implantation species is boron, the dose is 1E + 13-3E + 13 ions / cm ² , and the ion implantation energy is 80-100 KeV.
Next, the body region 4 and the RESURF region 5 (5a, 5b, 5c, 5d) are formed by diffusing so that the ends of adjacent ion implantation regions are in contact with each other (FIG. 2 (d)). The diffusion depth of the RESURF region is 2 to 3 μm, and the impurity concentration is 2E + 16 to 5E + 16 / cm ³ . The thickness of the body region 4 is 4 to 5 μm, and the impurity concentration is 5E + 16 to 2E + 17 / cm ³ .

Next, after removing the thermal oxide film b by a known method, a gate insulating film 6 having a thickness of 40 to 60 nm made of a silicon oxide film is formed by a thermal oxidation method.
Further, a gate electrode 7 is formed on the gate insulating film 6 so as to overlap the LOCOS film 3. The gate electrode 7 is made of polysilicon and has a thickness of 400 nm.
Further, ion implantation is performed using the LOCOS film 3 and the gate electrode 7 as a mask. The ion implantation species is As, the dose is 2E + 15-5E + 15 ions / cm ² , and the ion implantation energy is 80 KeV. After the implantation, a source region 8 and a drain region 9 are obtained through a diffusion process. The diffusion depth of both regions 8 and 9 is about 0.3 to 0.5 μm, and the impurity concentration is 2E + 20 to 1E + 21 / cm ³ .
Thereafter, the entire surface is covered with an interlayer insulating film 12 by a known method, the source region 8 and the drain region 9 are opened, and the source electrode 11 and the drain electrode 10 are formed, whereby the semiconductor device shown in FIG. obtain.

In FIG. 4, the solid line shows the simulation result of the breakdown voltage of the semiconductor device obtained by the above process. However, in FIG. 4, the length of the LOCOS film 3 in the gate length direction is varied from 45 μm to 75 μm.
In FIG. 4, the simulation result of the breakdown voltage of the conventional semiconductor device is also shown by a dotted line. As shown in FIG. 5, the conventional semiconductor device has the same configuration as the semiconductor device shown in FIG. 1 except that the bottom surfaces of the drain drift region 2 and the RESURF region 5 are flat.

  As shown in FIG. 4, the breakdown voltage sharply decreases as the LOCOS film width becomes shorter. However, by adopting a wave-shaped drain drift region, the point at which the breakdown voltage decreases can be shifted toward a shorter LOCOS width than in the prior art. Become. This is because the length of the drain drift region equivalent to the conventional one is ensured even with a short LOCOS width, and it can be seen that a breakdown voltage equivalent to the conventional one can be realized with a short LOCOS width.

  Specifically, in this simulation, the LOCOS film width can be shortened by 5 μm as compared with the conventional case when a breakdown voltage equivalent to the conventional one is obtained. By the way, the area of the semiconductor device is determined by “distance (pitch) between source region and drain region × channel width (W) + α (electrode, outer area)”. Therefore, for example, when the present invention is applied to a semiconductor device in which the distance (pitch) between the source region and the drain region is 80 μm and the channel length is 20 mm, the device area can be reduced by 5%.

It is a schematic sectional drawing of the semiconductor device of this invention. It is a schematic process sectional drawing of the semiconductor device of this invention. It is a schematic explanatory drawing of the length of a drain drift region. It is a figure which shows the relationship between the LOCOS film | membrane width of a semiconductor device, and a proof pressure. It is a schematic sectional drawing of the conventional semiconductor device.

Explanation of symbols

1 Well region (semiconductor substrate)
2 Drain drift region 2x Drain drift region lower surface 3 LOCOS film (insulating film)
4 Body region 5 RESURF region 5x RESURF lower surface 6 Gate insulating film 7 Gate electrode 8 Source region 9 Drain region 10 Drain electrode 11 Source electrode 12 Interlayer insulating film a, c Resist pattern b Thermal oxide film α Concentration line

Claims (9)

A second conductivity type source region and drain region formed in a surface layer of the first conductivity type semiconductor substrate;
An insulating film formed on the drain region side semiconductor substrate so that the source region side semiconductor substrate is exposed between the source region and the drain region; and
A gate insulating film formed on the exposed semiconductor substrate and a gate electrode thereon;
A first conductivity type resurf region formed in a surface layer of a semiconductor substrate under the insulating film;
A second conductivity type drain drift formed in the surface layer of the semiconductor substrate so as to cover the lower surface of the RESURF region and having two or more corrugated lower surface-shaped diffusion regions in the gate length direction. And a high breakdown voltage semiconductor device including a region. 2. The semiconductor device according to claim 1, wherein the RESURF region has two or more corrugated lower surface-shaped diffusion regions in a gate length direction. The semiconductor device further includes a first conductivity type body region and a second conductivity type well region, and the body region is formed on a surface layer of the semiconductor substrate so as to cover a lower surface of the source region, The semiconductor device according to claim 1, wherein a high voltage semiconductor device is located in the well region formed in a surface layer of the semiconductor substrate. 4. The semiconductor device according to claim 1, wherein the semiconductor device includes the high-voltage semiconductor device and a plurality of low-voltage semiconductor devices, and the insulating film corresponds to an element isolation insulating film that separates the plurality of low-voltage semiconductor devices. The semiconductor device as described in any one. The semiconductor device according to claim 1, wherein the gate insulating film is connected to the insulating film, and the gate electrode extends on the insulating film. The semiconductor device according to claim 1, wherein the insulating film is a LOCOS film. It is a manufacturing method of the semiconductor device according to any one of claims 1 to 6,
A second conductivity type drain drift region having two or more corrugated lower surface shaped diffusion regions in the surface layer of the first conductivity type semiconductor substrate and in the gate length direction is formed by ion implantation. Process,
Forming an insulating film on the drain drift region and so that the semiconductor substrate is exposed on the source region side;
Forming a first conductivity type RESURF region in the surface layer of the semiconductor substrate under the insulating film and in the drain drift region by ion implantation through the insulating film;
Forming a gate insulating film and a gate electrode in this order on the exposed semiconductor substrate;
Forming a source region and a drain region in a surface layer of the semiconductor substrate by ion implantation using the gate electrode and the insulating film as a mask, and the drain drift region is formed on the semiconductor substrate. A method of manufacturing a semiconductor device, characterized by being formed by ion implantation through a resist pattern having the same number of openings as a mold-shaped bottom-shaped diffusion region. The method of manufacturing a semiconductor device according to claim 7, wherein a step of forming a well region on the semiconductor substrate and a subsequent step are performed in the well region before forming the drain drift region. The RESURF region has two or more corrugated lower surface-shaped diffusion regions in the gate length direction, and has a resist pattern having the same number of corrugated openings formed on the insulating film. The method of manufacturing a semiconductor device according to claim 7, wherein the semiconductor device is formed by ion implantation through a substrate.

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