JP2009277245A - Design method and design device for semiconductor integrated circuit, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design method and a device for creating a high-quality layout in a short time by the use of a design system for a standard cell. <P>SOLUTION: Circuit diagram information (11) is inputted, a relative arrangement order of cells is automatically determined to the circuit diagram information (12), and the cells are automatically arranged in a relative positional relationship according to the arrangement order added to the circuit diagram information (13). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design technique, and more particularly, to a method, apparatus, and program suitable for application to a standard cell design.

  Conventionally, there are three methods for designing the layout of a semiconductor integrated circuit: a gate array, a full custom, and a standard cell.

  In the gate array, transistors arranged regularly in advance are designed only by changing the wiring connection. For this reason, it cannot be applied to a semiconductor pursuing integration such as a memory product.

  Full custom design allows high performance semiconductors to be designed, but the designer places the cells manually on physical coordinates while looking at the layout pattern. It cannot be applied to semiconductors that do.

  The design method using standard cells is a system in which cells are automatically arranged, so that it is suitable for semiconductors designed in a short period of time and has been widely used in recent years. However, the conventional standard cell automatic placement method is basically to simply place cells according to a certain rule. For this reason, it is not suitable for the design which draws out performance by optimizing the arrangement position of each cell. Therefore, it is difficult to design with an emphasis on circuit quality by the standard cell design method. In addition, it is possible to define multiple cells as one group by the technique of grouping and automatically place cells belonging to the group close to each other. It is not possible to specify a general positional relationship. For this reason, the arrangement order of cells desired by the designer is not achieved, and an optimized circuit design cannot be performed.

  In addition, as a document related to automatic design such as timing constraint and optimization of arrangement, for example, Patent Document 1 discloses that a logic cell related to a critical path is arranged in an outer divided area, which is close to a group input terminal and output terminal. Since logic cells with a large number of stages from the input terminal and the output terminal are arranged in the inner divided region, automatic arrangement reflecting the circuit configuration is possible, and arrangement that shortens the design period while satisfying the timing constraint condition A method has been proposed. Further, Patent Document 2 generates a net list representing the connection relationship between flip-flops related to timing constraints, determines the layout position of the flip-flops according to the net list, performs layout design, and has a short processing time. A design method is disclosed in which LSI timing constraints are surely satisfied. Patent Document 3 discloses a method for obtaining a layout design with a small distribution of wiring distribution density in a standard cell layout design. Patent Document 4 discloses a method including a step of dividing a module into cell arrangement regions in which internal cells are arranged in a row, optimizing allocation of the internal cells to the cell columns, and optimizing the arrangement of the internal cells in the cell columns. Is described. In Patent Document 5, design changes for cell insertion, replacement, and deletion are taken in the middle of automatic placement design, and timing determination, design change, and loop of placement lines are formed, so that automatic correction processing is realized in a short time. A method is disclosed. Further, Patent Document 6 discloses a method that can realize a high-quality module arrangement without human intervention even in an LSI including a large number of hard macros.

JP 2001-68551 A Japanese Patent Laid-Open No. 10-74842 Japanese Patent Laid-Open No. 10-189750 Japanese Patent No. 2800781 Japanese Patent No. 3256597 Japanese Patent No. 3433025

When designing with an emphasis on circuit quality in the conventional automatic design method using standard cells, etc.
-Cell layout of circuits that require the same timing,
・ Critical path and unimportant path,
-Designing multiple batches of circuits that need to have the same characteristics, such as memory input / output circuits,
・ Designing circuits that need to have symmetrical characteristics, such as amplifier circuits,
I can't. The reason for this is that in the standard cell automatic design method, cells are automatically arranged according to certain rules, so cells are placed in a different positional relationship from the intention of the designer who knows the circuit characteristics. caused by.

For example, in the circuit shown in FIG.
-The part 141 needs to have a cell arrangement that gives the same characteristics in the three systems of circuits.
The element Q of 142 needs to arrange cells at positions close to all of the elements D1, D2, and D3 of 141,
Since the part 143 is a circuit with a sufficient characteristic, it may be arranged at a position with a lower priority than other cells.

  FIG. 17 shows an example in which cells of this circuit are arranged using an algorithm that shortens the total wiring length of the current mainstream standard cell system. 17, 171, 172, 173, 174, and 175 respectively correspond to 141, 142, 143, 144, and 145 in FIG. 14. In this algorithm, since the portion 141 and the portion 143 in FIG. 14 cannot be separated, the portion 143 having a low priority enters between the portions 141 having a high priority. 171 and 173. For this reason, the cell arrangement is such that the characteristics of the three circuits 141 are different.

  Further, the elements D1, D2, D3, and 142 of the element 141 in FIG. 14 are arranged as in the elements 171 and 172 in FIG. 17, and the wiring b in FIG. As shown by 175, the path becomes redundant, resulting in deterioration of circuit quality and an obstacle in arranging other wiring.

  The wiring a of 144 of FIG. 14 is also arranged as shown by 174 of FIG. 17, so that the same input is not generated by the three systems of circuits and the same problem occurs.

  Accordingly, an object of the present invention is to provide a design method, an apparatus, and a program capable of creating a high-quality layout in a short time. In addition, the present invention achieves the above-mentioned object by using automatic design by standard cells, realizes a high-speed critical path, and enables supply of signals at the same speed to a plurality of input wirings. In addition, the purpose is to provide a program.

  The invention disclosed in the present application is generally configured as follows in order to achieve the above object.

  The design method of the present invention includes means for automatically determining the relative arrangement order of cells in accordance with the priority frame added to the circuit diagram information, and the cell in accordance with the relative arrangement order of cells possessed by the circuit diagram information. Arrange them in the desired relative positional relationship.

  A method according to one aspect of the present invention is a method for designing a semiconductor device using a computer. First, circuit diagram information is input, and a relative arrangement order of cells is given to the circuit diagram information. And a second step of automatically arranging cells in a relative positional relationship according to the arrangement order given to the circuit diagram information.

A method according to another aspect of the present invention is a method for designing a semiconductor device using a computer, in which circuit diagram information is input and a group number is added to the circuit diagram information in addition to relative arrangement information of cells. A first step of assigning, and a second step of automatically placing the cells having the same group number in a relative positional relationship according to the placement order added to the circuit diagram information,
including.

  An apparatus according to one aspect of the present invention is a setting device for a semiconductor device, which inputs circuit diagram information and gives a relative arrangement order of cells to the circuit diagram information, and the circuit diagram. Means for automatically arranging the cells in a relative positional relationship according to the arrangement order given to the information. In the present invention, the means for assigning the relative arrangement order of the cells determines each of the areas divided into a plurality of areas in the direction specified in the circuit diagram information when determining the relative arrangement order of the cells. The device may be searched every time, and when the device is searched, the arrangement number of the cell may be given. In the present invention, the means for assigning the relative arrangement order of the cells uses the priority frame set in the circuit diagram information to determine the relative arrangement order of the cells, and prioritizes the priority frame. It is good also as a structure which determines the relative arrangement | positioning order of a cell in order of a degree.

  An apparatus according to another aspect of the present invention has the same group number as arrangement order determining means for inputting circuit diagram information and assigning a group number to the circuit diagram information in addition to relative arrangement information of cells. Placement means for automatically placing the cells in a relative positional relationship in accordance with the placement order added to the circuit diagram information with respect to the cell.

  A program according to an aspect of the present invention is a first process for inputting circuit diagram information to a computer constituting a semiconductor device design apparatus and assigning a relative arrangement order of cells to the circuit diagram information. And a second process for automatically arranging cells in a relative positional relationship according to the arrangement order given to the circuit diagram information.

  A program according to another aspect of the present invention inputs circuit diagram information to a computer constituting a semiconductor device design apparatus, and assigns a group number to the circuit diagram information in addition to relative arrangement information of cells. The program includes a program for executing a process and a process of automatically arranging the cells in the relative positional relationship according to the arrangement order added to the circuit diagram information with respect to cells having the same group number.

  According to the present invention, in an automatic design method using standard cells, the relative arrangement order for automatic cell placement is determined at the time of circuit design by simply specifying the element placement as a priority frame during circuit design. Therefore, it is possible to create a high-quality layout in a short time, which can speed up critical paths and supply signals at the same speed to a plurality of input wirings.

It is a figure for demonstrating the structure of the 1st Embodiment of this invention. It is the flowchart which showed the process of the means to determine the relative arrangement | positioning order of a cell in the 1st Embodiment of this invention. It is circuit diagram information for demonstrating the 1st Embodiment of this invention. It is circuit diagram information in the stage which the process by the means which determines the relative arrangement | positioning order of a cell in the 1st Embodiment of this invention was complete | finished. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 3 in the 1st Embodiment of this invention. It is the flowchart which showed the process of the means to determine the relative arrangement | positioning order of the cell in the 2nd Embodiment of this invention. It is circuit diagram information for demonstrating the 2nd Embodiment of this invention. It is circuit diagram information in the stage which the process by the means which determines the relative arrangement | positioning order of a cell in the 2nd Embodiment of this invention was complete | finished. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 7 in the 2nd Embodiment of this invention. It is circuit diagram information for demonstrating the 3rd Embodiment of this invention. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 10 in the 3rd Embodiment of this invention. It is circuit diagram information for demonstrating the 4th Embodiment of this invention. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 12 in the 4th Embodiment of this invention. It is circuit diagram information for demonstrating the 5th Embodiment of this invention. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 14 in the 5th Embodiment of this invention. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 14 in the 5th Embodiment of this invention. It is a figure which shows the example which carried out the cell arrangement | positioning with the algorithm which shortens the total wiring length of a standard cell system. It is a figure for demonstrating the structure of the 6th Embodiment of this invention. It is circuit diagram information for demonstrating the 6th Embodiment of this invention. It is the figure which designated the arrangement | positioning order and group number by the 6th Embodiment of this invention. It is a figure which shows the result of having arrange | positioned the cell automatically based on the circuit diagram information of FIG. 19 in the 6th Embodiment of this invention.

  Next, an embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a diagram for explaining a design method according to an embodiment of the present invention. Referring to FIG. 1, in the present embodiment, circuit diagram information 11 (including circuit connection information and element information), for example, with a priority frame to be described later is added to circuit diagram information, and automatically generated from the circuit diagram information 11. Means 12 for determining the relative arrangement order of the cells, and means for automatically automatically arranging the cells while maintaining the relative positional relationship according to the information on the arrangement order of the cells determined by the means 12 And.

  For example, a circuit as shown in FIG. 3 is designed as the circuit diagram information 11. The circuit of FIG. 3 includes a path 32 (including element A, element B, and element C) from input J to output M, and a path 33 (including element A, element D, and element E) from input J to output N. Therefore, the circuit designer usually considers the arrangement order of the cells as shown in FIG.

  FIG. 5 shows an arrangement order of cells optimized for circuit quality, which is a design goal of the circuit designer. Cell A (connected to input J) is arranged in the center of one row (cell row) of standard cells, cells B and C are arranged on the left side, and cells D and E are arranged on the right side. . FIG. 5 is a diagram showing a result of automatically arranging cells according to this embodiment based on the circuit diagram information of FIG.

  FIG. 2 is a flowchart showing details of the processing procedure of the means 12 for determining the relative arrangement order of the cells. The design method of the present embodiment will be described using the flowcharts of FIGS. 2 is realized by a program executed by a computer constituting the semiconductor device design apparatus.

  The arrangement number is set to an initial value (step 21). The initial value is 1.

  The element is searched in the direction specified for the circuit diagram information (step 22). The search is performed by confirming the presence of the element in the vertical direction or the horizontal direction. In the present embodiment, the circuit diagram information of FIG. 3 is automatically divided into regions in a vertical direction (for example, set by a circuit designer) in the vertical direction, as indicated by 46 to 48 in FIG. A search is performed from the left end region 46 toward the right end region 48 to determine whether an element is present. As a method of automatically dividing the region, a method of dividing by the horizontal direction, the diagonal direction, and other rules besides the vertical direction can be applied. The width preset in the vertical direction may be set automatically.

  In FIG. 4, reference numerals 46 to 48 denote areas where the means 12 for automatically determining the relative arrangement order of the cells in FIG. Reference numerals 41 to 45 denote arrangement orders automatically determined by the means 12.

  When an element is searched in the search target region by the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1 (YES branch in step 24), the cell arrangement number is assigned and the arrangement is performed at the same time. The means 12 for automatically determining the relative arrangement order of the cells is incremented (step 25). Since the element C is searched in the area 41 of FIG. 1 is incremented to 2 and element B is searched in area 42. Therefore, cell arrangement number 2 is assigned, and the arrangement number is incremented by 1 to 3 and element A is searched in area 43. Therefore, the cell arrangement number 3 is assigned, the arrangement number is incremented by 1 to 4, and the element D is searched in the region 44. Therefore, the cell arrangement number 4 is assigned and the arrangement number is incremented by 1. do it And then, in the region 45, since the element E is retrieved, grant arrangement number 5 cells, the arrangement number and 6.

  When all the elements of the circuit diagram information have been searched (NO branch at step 24), the processing of the means 12 for automatically determining the cell arrangement order is completed. At this time, the circuit diagram information is in a state in which the relative arrangement order of the cells is given as indicated by 41 to 45 in FIG. FIG. 4 is circuit diagram information at the stage when the processing by the means 12 for determining the relative arrangement order of the cells in FIG. 1 is completed. Numbers 1 to 5 are assigned to a plurality (five) of cells C, B, A, D, and E, respectively. From this state, cells are automatically arranged according to the relative arrangement order given to the circuit diagram information. As a result, the arrangement order of the cells is the arrangement as shown in FIG. 5 which the circuit designer thinks is optimal, and the design with optimized timing becomes possible. The paths 31, 32, and 33 in FIG. 3 correspond to the paths 51, 52, and 53 in FIG.

  Next, a second embodiment of the present invention will be described. The difference between this embodiment and the said embodiment is a point which uses the priority frame which characterizes arrangement | positioning order in this embodiment. The design method in the present embodiment follows FIG. 1 as in the first embodiment.

  FIG. 6 is a flowchart showing in detail the means of the means 12 for determining the relative arrangement order of cells in this embodiment. Unlike the first embodiment, this embodiment has a processing procedure for designing using a priority frame. The processing in FIG. 6 is realized by a program executed by a computer constituting the semiconductor device design apparatus.

  FIG. 7 is circuit diagram information for explaining the present embodiment. 71 is the first priority frame, 72 is the second priority frame, 73 is a critical path that requires the highest speed, 74 is a delay path that does not cause any problem even if the wiring length is slightly increased, and 75 is an input to the delay A path 76 indicates an output path of the delay. As the circuit diagram information of FIG. 1, circuit diagram information as shown in FIG. 7 is designed, and priority frames 71 and 72 are set. As a feature of this circuit, it is necessary to make the total wiring length of the critical path 73 as short as possible.

  Therefore, the circuit is divided into two areas (priority frames) 71 and 72, and the critical path 73 and the delay path 74 are extended by extending the wiring length of the input / output unit to the delay paths 75 and 76 connecting these areas. The most optimal design is to arrange the cells together. Therefore, a first priority frame 71 and a second priority frame 72 are set in the circuit diagram information.

  Referring to FIG. 6, the arrangement number is set to an initial value (step 61). The initial value is 1 in this embodiment.

  Next, the element search area is set to the priority frame having the highest priority set in the circuit diagram information (step 62).

  First, an element search is performed for the area of the first priority frame (step 63). In the present embodiment, as in the above-described embodiment, the region is divided in the vertical direction, and it is searched that the element exists from the left region to the right region.

  When an element is searched in the search target area (YES branch of step 64), the cell arrangement number is assigned and the arrangement number is incremented (step 65).

  If all the elements in the search target area have been searched (NO branch of step 64), the process proceeds to step 66.

  If all the priority frame areas have not been searched (NO branch of step 66), the search area number is incremented in accordance with the priority of the area set in advance in step 67, and step 63 is performed for the next search area. Resume search from.

  When all the areas have been searched (YES branch of step 66), the process of the means 12 for automatically determining the cell arrangement order is finished. At this point, the circuit diagram information is given a relative arrangement order of cells as indicated by 81 to 87 in FIG. 8, and the cell arrangement position can be easily determined only by looking at the circuit diagram information. Predictable. FIG. 8 shows circuit diagram information obtained through the means 12 of FIG. Reference numerals 81 to 87 indicate arrangement orders automatically determined by the above-described means 12. The elements A, F, and G in the region (priority frame) 71 are assigned arrangement orders 1, 2, and 3, and the elements B, C, D, and E in the region (priority frame) 72 are arranged in arrangement orders 4, 5, and 6, respectively. , 7 is given.

  Thereafter, cells are arranged according to the relative arrangement order automatically given to the circuit diagram information (arranged from the left to the right in the order of the arrangement orders 1 to 7), the critical path 73 of FIG. Thus, the wiring length can be minimized. FIG. 9 shows the arrangement order of cells optimized by the circuit quality, which is a design goal of the circuit designer, and also shows the result of automatically arranging cells according to the present invention based on the circuit diagram information of FIG.

  Further, the inputs and outputs 75 and 76 to the delay path in FIG. 7 are arranged so as not to affect the critical path as in 95 and 96 in FIG. Since the layout is considered optimal by the designer, it is possible to design with optimized timing.

  Next, a third embodiment of the present invention will be described. The design method of this embodiment is the same as that of the second embodiment described with reference to FIGS. FIG. 10 is circuit diagram information showing the present embodiment. 101 is the first priority frame, 102 is the second priority frame, 103 is the third priority frame, and 104 is the fourth priority frame. FIG. 11 shows the arrangement order of the cells whose circuit quality is optimized, which is a design goal of the circuit designer. Also, the result of automatically arranging the cells according to this embodiment based on the circuit diagram information of FIG. is there.

  Next, the design method of the present embodiment will be described with reference to FIGS. 1 and 6.

  As the circuit diagram information 11 of FIG. 1, circuit diagram information as shown in FIG. 10 is designed, and priority frames 101 to 104 are set. As a feature of this circuit, circuits 101, 103, and 104 have the same characteristics, and it is necessary to arrange all the wiring layouts between the cells.

  The means 12 in FIG. 1 automatically determines and assigns the relative arrangement order of the cells to the circuit diagram information 11, which is realized by the procedure shown in the flowchart of FIG. Since this procedure is the same as that of the second embodiment, detailed description thereof is omitted.

  At the time when the processing of the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1 is completed, the circuit diagram information includes the cell relative to all the elements as indicated by 105 in FIG. Thus, the cell arrangement position can be easily predicted only by looking at the circuit diagram information.

  After that, when cells are arranged in accordance with the relative arrangement order automatically given to the circuit diagram information, 101 in FIG. 10 is at 111 in FIG. 11, 102 is at 112, 103 is at 113. , 104 are arranged at positions 114, the circuit characteristics of 101, 103, 104 are uniform, and an optimized design can be realized.

  Next, a fourth embodiment of the present invention will be described with reference to FIG. 1, FIG. 6, FIG. 12, and FIG. The design procedure of the fourth embodiment is the same as that of the second embodiment described with reference to FIGS.

  FIG. 12 is circuit diagram information for explaining the present embodiment. In FIG. 12, 121 to 123 are the first to third priority frames, respectively. FIG. 13 shows an arrangement order of cells optimized for circuit quality, which is a design goal of the circuit designer, and results of automatically arranging cells according to the present embodiment based on the circuit diagram information of FIG. It is also a figure which shows.

  Next, the design method of this embodiment will be described with reference to the flowcharts of FIGS.

  As the circuit diagram information 11 of FIG. 1, circuit diagram information as shown in FIG. 12 is designed, and priority frames 121 to 123 are set. As a feature of this circuit, the priority frames 121 and 123 need to arrange cells in a symmetrical shape so as to have a symmetrical characteristic with respect to the priority frame 122.

  In the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1, the assignment of the arrangement order to the circuit diagram information 11 is realized by the procedure shown in the flowchart of FIG. Since this procedure is the same as that of the second embodiment, detailed description thereof is omitted.

  When the processing of the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1 is completed, the circuit diagram information includes relative cell positions for all elements as indicated by 124 in FIG. It is in a state where a proper arrangement order is given. Only by looking at the circuit diagram information, the cell arrangement position can be easily predicted.

  Thereafter, when cells are arranged according to the relative arrangement order automatically given to the circuit diagram information, 121 to 123 in FIG. 12 are arranged at the locations 131 to 133 in FIG. The cells corresponding to 123 can be arranged in a symmetrical shape, and the characteristics can be optimized.

  Next, a fifth embodiment of the present invention will be described with reference to FIG. 1, FIG. 6, and FIGS. The design method of this embodiment is the same as that of the second embodiment shown in FIGS.

  FIG. 14 is circuit diagram information for explaining the present embodiment. In FIG. 14, reference numerals 141 to 143 denote circuit portions having different characteristics. Reference numerals 144 and 145 denote specific wirings, and reference numerals 146 to 148 denote first to third priority frames.

  FIG. 15 is circuit diagram information that has undergone processing by the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1, and is automatically determined by the means 12 for all elements as indicated by 151. FIG. This shows that the arranged order is determined. FIG. 16 shows a cell layout order optimized for circuit quality, which is a design goal of the circuit designer, and is also a result of automatic cell placement according to the present invention based on the circuit diagram information of FIG. .

  Next, the design method of this embodiment will be described with reference to the flowcharts of FIGS.

  As the circuit diagram information 11 of FIG. 1, circuit diagram information as shown in FIG. 14 is designed, and priority frames 146 to 148 are set. As a feature of this circuit, the portion 141 needs to have a cell arrangement so that the three circuits have the same characteristics, and the element Q 142 is a position close to all of the elements D1, D2, D3 of 141. In addition, since the cell 143 is a circuit with a sufficient characteristic, it may be arranged at a position having a lower priority than other cells.

  In the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1, the relative arrangement order of the cells is given to the circuit diagram information 11 according to the procedure shown in the flowchart of FIG. Since this procedure is the same as that of the second embodiment, detailed description thereof is omitted.

  When the processing of the means 12 for automatically determining the relative arrangement order of the cells in FIG. 1 is completed, the circuit diagram information includes the relative arrangement order of the cells for all the elements as indicated by 151 in FIG. It will be in the state where is given. Only by looking at the circuit diagram information, the cell arrangement position can be easily predicted.

  Thereafter, the cells are arranged according to the relative arrangement order automatically given to the circuit diagram information. In the fifth embodiment, the cells are not arranged in a line as in the first to fourth embodiments. Instead, when the priority frame changes, by applying an algorithm that changes the number of cell arrangement stages by one, cells can be automatically arranged in three stages as shown in FIG. As a result, 146 to 148 in FIG. 14 are arranged at positions 166 to 168 in FIG. 16, and the portion 141 in FIG. 14 has the same shape of the three circuits as 161 in FIG. Cells can be placed in Also, as shown in 162 and 161 in FIG. 16, cells can be arranged close to each of the elements Q in 142 in FIG. 14 and the elements D1, D2, and D3 in 141, so that the wiring b in 145 in FIG. 16 can be wired so as to have the shortest path as indicated by 165 in FIG.

  The portion 143 in FIG. 14 can also be moved to the end of the cell area where the cell to be arranged is designed as in 163 in FIG. 16, and as a result, the placement of other high priority cells or between cells The configuration does not cause problems that prevent wiring.

<Effects of Embodiment>
In each of the above embodiments, before the cells are actually arranged, the circuit designer can set and grasp the relative positional relationship, and the cells are arranged at a position not intended by the circuit designer. The problem is avoided. The above-described embodiment of the present invention has the following effects.

  As a function and effect of the first embodiment of the present invention, it is possible to design a circuit with the same timing that requires a plurality of input wires to be supplied with signals at the same speed. In the circuit as shown in FIG. 3, it is necessary to design the path 32 from the input J to the output M and the path 33 from the input J to the output N at exactly the same timing. Are designed so that the path distances are equal. In this embodiment, the cell arrangement can be optimized so that 52 paths and 53 paths are equidistant as shown in FIG.

  As a function and effect of the second embodiment of the present invention, a design in which a critical path and an unimportant path are separated is possible. A critical path is a path that requires the fastest speed. It is necessary to arrange cells adjacent to each other, minimize the wiring connecting each cell, and reduce wiring resistance and wiring capacity as much as possible. . In the circuit shown in FIG. 7, reference numeral 73 denotes a critical path. 74 is a path that is not important compared to 73. In particular, the wirings 75 and 76 have no problem even if they have some resistance and capacitance, and it is necessary to preferentially design 73 paths. In the present embodiment, as shown in FIG. 9, an optimized circuit design can be realized by dividing cells into 91 critical path regions and 92 unimportant regions and arranging them adjacent to each other.

  As a function and effect of the third embodiment of the present invention, a plurality of groups of circuits that need to have the same characteristics, such as a memory input / output circuit, can be designed at a time. In the circuit shown in FIG. 10, 101, 103, and 104 are circuits having the same characteristics. In order to design the same characteristics, it is most effective to arrange all the wiring routing shapes between cells. In the present invention, cells 101, 103, and 104 in FIG. 10 can be arranged in a positional relationship such as 111, 113, and 114 in FIG. 11, so that optimization of characteristics can be realized.

  As a function and effect of the fourth embodiment of the present invention, a circuit that needs to have contrasting characteristics such as an amplifier circuit can be designed. FIG. 12 shows an example of this type of circuit. In order to give symmetrical characteristics 121 and 123, it is necessary to arrange and wire cells in a symmetrical shape. In the present invention, cells can be arranged as shown in FIG. 13, and 121 and 123 in FIG. 12 are arranged as 131 and 133 in FIG. 13 to realize a design with optimized circuit characteristics. .

  As a function and effect of the fifth embodiment of the present invention, a circuit that is a complex circuit that combines the circuits of the first to fourth embodiments, and that cannot be designed by the conventional automatic cell placement method, By applying the present invention, separation of critical paths and unimportant paths, cell arrangement suitable for circuits having the same characteristics of a plurality of systems, and all cell arrangements that can optimize the wiring shape after cell arrangement However, it can be specified at the time of creating circuit diagram information, and automatic cell placement can be completed with a shape optimized at one time.

  Next, an embodiment combined with a standard cell type automatic placement algorithm will be described as a sixth embodiment of the present invention.

  FIG. 18 shows a design method according to the present embodiment. In FIG. 18, reference numeral 181 denotes circuit diagram information. For example, FIG. 19 shows circuit diagram information corresponding to this, but the paths 191 and 192 are critical paths, and cells need to be continuously arranged adjacent to each other. The other elements are less important paths, and there is no need to consider the arrangement position of the cells.

  Reference numeral 182 denotes a means for designating the relative arrangement order of the cells only for elements for which the designer needs to designate the arrangement order of the cells in consideration of circuit quality with respect to the circuit diagram information of 181. The difference from the above embodiment is that the arrangement order is not specified for all elements, but is specified only for necessary elements such as those relating to critical paths. In addition, the same group number is assigned to elements having a connection relationship, not just the arrangement order.

  FIG. 20 is a diagram in which the arrangement order and the group number are designated in the circuit diagram information of FIG. In FIG. 20, 201 is a group number, and 202 is a relative arrangement order of cells.

  Reference numeral 183 denotes a means for automatically arranging cells by the standard cell method algorithm. When a cell having a group number is arranged, all the cells having the group number are compared with the cells designated by 182. Arrange the original arrangement order. For example, when cells corresponding to 203 in FIG. 20 are arranged, cells corresponding to elements 204 and 205 having the same group number are successively arranged according to the arrangement order of the cells specified in 182.

  As a result, the arrangement order of the cells becomes the order as shown in FIG. 21 that the circuit designer considers optimal, the critical path 191 in FIG. 19 is as indicated by 211 in FIG. 21, and the critical path 192 in FIG. As in 212 of FIG. 21, a desired arrangement order is observed.

  Although the semiconductor device design method of the present invention has been described above, the process of the above design method (the process of FIG. 1, FIG. 2, FIG. 6, FIG. 18, etc.) is implemented by a program executed by a computer (not shown). Thus, an automatic design apparatus for semiconductor devices is provided.

  Although the present invention has been described with reference to the above embodiment, the present invention is not limited only to the configuration of the above embodiment, and various modifications that can be made by those skilled in the art within the scope of the present invention. Of course, modifications are included.

11, 181 Circuit diagram information 12 Means for determining relative arrangement order of cells 13 Means for automatically arranging cells 31, 32, 33, 51, 52, 53 Paths 71, 72, 91, 92, 101-104, 111 -114, 121-123, 131-133, 146-148, 166-168 Priority frame 73, 74, 75, 76, 93, 95, 96 passes 81-87, 105, 124, 151 Arrangement order 41-48 Area 141 , 143, 161, 163, 171, 173 Parts 142, 162, 172 Element 182 Means of specifying a group number in addition to the relative arrangement order of cells 183 Maintaining the relative positional relationship of cells with respect to cells having the same group number 191, 192, 211, 212 Critical path 201 Group number 202 The relative arrangement order 203-205 element

Claims (19)

A method of designing a semiconductor device using a computer,
A first step in which the computer inputs circuit diagram information and gives a relative arrangement order of cells to the circuit diagram information;
A second step in which the computer automatically arranges the cells in a relative positional relationship according to the arrangement order given to the circuit diagram information;
Including
In the first step, when the computer determines the relative arrangement order of the cells, the computer searches for each element divided into a plurality of areas in a direction specified in the circuit diagram information. A method for designing a semiconductor device, comprising assigning an arrangement number of the cell when an element is searched. In the first step, the computer
A step of setting the cell arrangement number to an initial value;
In searching for an element along a predetermined first direction with respect to the input circuit diagram information, a plurality of widths set in advance in a second direction predetermined with respect to the first direction are set. Searching for whether or not there is an element from the region at one end to the region opposite to the one end with respect to the divided region;
When an element is searched in the search target area, a step of assigning a cell arrangement number and raising the arrangement number;
The method of designing a semiconductor device according to claim 1, further comprising: A method of designing a semiconductor device using a computer,
A first step in which the computer inputs circuit diagram information and assigns a group number to the circuit diagram information in addition to giving a relative arrangement order of cells;
A second step in which the computer arranges the cells having the same group number in a relative positional relationship in accordance with the arrangement order given to the circuit diagram information;
Including
In the first step, when the computer determines the relative arrangement order of the cells, the computer searches for each element divided into a plurality of areas in the direction specified in the circuit diagram information. A method for designing a semiconductor device, comprising assigning an arrangement number of the cell when an element is searched.   4. The semiconductor according to claim 1, wherein a designer can set and grasp a relative positional relationship of cell arrangement before the second step of arranging cells. 5. Device design method. A semiconductor device design device,
Means for inputting circuit diagram information and giving a relative arrangement order of cells to the circuit diagram information;
Means for automatically arranging cells in a relative positional relationship according to the arrangement order given to the circuit diagram information;
Including
The means for assigning the relative arrangement order of the cells determines the relative arrangement order of the cells by determining the element arrangement for each area divided into a plurality of areas in the direction specified in the circuit diagram information. A design apparatus for performing a search and assigning an arrangement number of the cell when an element is searched. A semiconductor device design device,
Means for inputting circuit diagram information and giving a relative arrangement order of cells to the circuit diagram information;
Means for automatically arranging cells in a relative positional relationship according to the arrangement order given to the circuit diagram information;
Including
The means for assigning the relative arrangement order of the cells sets the arrangement number to an initial value, and searches for the element along a predetermined first direction with respect to the circuit diagram information. Search for whether or not there is an element from one region to the region opposite to the one end with respect to a region divided into a plurality of predetermined widths in a predetermined second direction with respect to one direction;
A design apparatus characterized in that when an element is searched for in a search target area, a cell arrangement number is assigned and the arrangement number is incremented. A semiconductor device design device,
Means for inputting circuit diagram information and assigning a group number to the circuit diagram information in addition to giving a relative arrangement order of cells;
Means for automatically placing cells having the same group number in a relative positional relationship according to the placement order assigned to the circuit diagram information;
Including
The means for assigning the relative arrangement order of the cells determines the relative arrangement order of the cells by determining the element arrangement for each area divided into a plurality of areas in the direction specified in the circuit diagram information. A design apparatus for performing a search and assigning an arrangement number of the cell when an element is searched. In a computer constituting a semiconductor device design apparatus,
A first process of inputting circuit diagram information and assigning a relative arrangement order of cells to the circuit diagram information;
A second process for automatically arranging cells in a relative positional relationship in accordance with an arrangement order assigned to the circuit diagram information;
A program for executing
The first process includes
Processing to set the cell arrangement number to the initial value;
In searching for an element along a predetermined first direction with respect to the input circuit diagram information, a plurality of widths set in advance in a second direction predetermined with respect to the first direction are set. A process for searching whether or not there is an element from a region at one end to a region opposite to the one end with respect to the divided region;
When an element is searched in the search target area, a process of assigning a cell arrangement number and incrementing the arrangement number;
The program characterized by including. The first process includes
Processing to set the allocation number to the initial value;
For priority frames preset in the circuit diagram information, in order of priority,
The element is searched for the priority frame region. At that time, when searching for the element along the predetermined first direction with respect to the circuit diagram information, the predetermined number with respect to the first direction is determined. In the region divided into a plurality of widths set in advance in the direction of 2, search whether there is an element from one region to the region opposite to the one end, and the device searches in the region to be searched. The program according to claim 8, wherein, if it is, the process of assigning a cell arrangement number and incrementing the arrangement number is performed for all priority frames. In a computer constituting a semiconductor device design apparatus,
A process of inputting circuit diagram information and assigning a group number to the circuit diagram information in addition to providing a relative arrangement order of cells;
A process of automatically arranging relative positional relationships according to the arrangement order assigned to the circuit diagram information for cells having the same group number;
A program for executing
The first process includes
Processing to set the cell arrangement number to the initial value;
In searching for an element along a predetermined first direction with respect to the input circuit diagram information, a plurality of widths set in advance in a second direction predetermined with respect to the first direction are set. A process for searching whether or not an element is present from a region at one end to a region opposite to the one end with respect to the divided region;
When an element is searched in the search target area, a process of assigning a cell arrangement number and incrementing the arrangement number;
The program characterized by including. A method of designing a semiconductor device using a computer,
A first step in which the computer receives circuit diagram information comprising a plurality of elements;
A second step in which the computer searches each element of the circuit diagram information to find each of the plurality of elements;
A third step in which the computer assigns a different arrangement number to the found element each time the element is found by the search;
The computer is a step of automatically arranging a plurality of cells respectively corresponding to the plurality of elements, and the relative arrangement relationship of the plurality of cells is in the order of the assigned arrangement numbers. A fourth step of automatically arranging the plurality of cells;
A method for designing a semiconductor device, comprising: The second step includes
A fifth step of dividing the circuit diagram information into a plurality of regions;
A sixth step of scanning the plurality of elements in the first direction to find the plurality of elements;
The method for designing a semiconductor device according to claim 11, further comprising:   In the first step, when the computer determines the relative arrangement order of the cells, the element is a priority frame preset in the circuit diagram information and should be arranged with priority over other elements. 12. The method of designing a semiconductor device according to claim 11, wherein a relative arrangement relationship of cells is determined in order of priority of the priority frame using a priority frame that designates. In the first step, the computer assigns m consecutive arrangement numbers to the first to m-th cells corresponding to m (where m is a positive integer) elements in the priority frame. ,
14. The method of designing a semiconductor device according to claim 13, wherein in the second step, the first to m-th cells in the priority frame are continuously arranged in a cell row.   14. The method of designing a semiconductor device according to claim 13, wherein, in the circuit diagram information, a priority frame of an area including a critical path is set in advance to a higher priority than an area not including a critical path. The circuit diagram information includes a configuration in which a signal is commonly given from one other circuit block to a plurality of circuit blocks,
The upper limit of the arrangement number given to the cell in the priority frame including at least one circuit block of the plurality of circuit blocks, and the arrangement number given to the cell in the priority frame of the other one circuit block 14. The method for designing a semiconductor device according to claim 13, wherein the lower limit is preset to a value adjacent to each other. In the first step, the computer
A step of setting the arrangement number to an initial value;
For priority frames set in the circuit diagram information, in order of priority,
The element is searched for the priority frame region. At that time, when searching for the element along the predetermined first direction with respect to the circuit diagram information, the predetermined number of the first direction is determined. A step of searching whether there is an element from a region at one end to a region opposite to the one end with respect to a region divided into a plurality of widths set in advance in the direction of 2;
When an element is searched in the search target area, a step of assigning a cell arrangement number and raising the arrangement number;
12. The method of designing a semiconductor device according to claim 11, wherein the step is performed for all priority frames.   15. The semiconductor according to claim 14, wherein when the priority frame assigned to the circuit diagram information is changed, the second step includes the step of changing the number of stages of cell columns in the cell arrangement in the second step. Device design method. A semiconductor device design device,
A first means for receiving circuit diagram information comprising a plurality of elements;
A second means for searching each element of the circuit diagram information to find each of the plurality of elements;
A third means for assigning a different arrangement number to the found element each time the element is found by the search;
Means for automatically arranging a plurality of cells respectively corresponding to the plurality of elements, wherein the plurality of cells are arranged such that a relative arrangement relationship of the plurality of cells is in the order of the assigned arrangement numbers. A fourth means for automatically arranging
An apparatus for designing a semiconductor device, comprising:

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