JP2009276987A - Circuit design verification method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit design verification method for allowing an operator to perform design verification without omission while reducing his burden. <P>SOLUTION: When registering a cell in a library 3, the circuit element of a standard cell is changed according to the specifications of a product, and registered as a specific cell 4, and when the size of the element is extracted about a GDS file of the specific cell 4, a cell single GDS file 5 is created for a bipolar transistor and a diode, and when a separation script for executing LVS in the cell units is created on the basis of the data and cell name of the cell, an include file for the LVS is created on the basis of this separation script. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a circuit design verification method for comparing and verifying a circuit diagram and layout data designed based on the circuit diagram.

  When verifying the layout design of the integrated circuit based on the circuit diagram, the size of each device is verified together with the connection state. The size of the latter depends on the attribute of each device if it is a MOS transistor, resistor element, or capacitor. Verification can be performed.

However, bipolar transistors and diodes can be verified using the emitter area and the anode area as attributes, but cannot be detected even if a mismatch occurs in other parts. This is because the current verification algorithm is premised on classification based on the device structure (PNP, NPN for bipolar transistors, Zener, withstand voltage, etc. for diodes).
As a conventional technique for performing design verification in this way, for example, there is one disclosed in Patent Document 1.
Japanese Patent Laid-Open No. 7-93392

If verification is performed according to Patent Document 1, in the end, bipolar transistors and diodes are all designed with different device details (for example, about 100 to several hundred types) created as individual cells in advance. There is a problem that the work burden is very large and time is required.
The present invention has been made in view of the above circumstances, and an object thereof is to provide a circuit design verification method capable of performing design verification without leakage while reducing the burden on the operator.

  According to the circuit design verification method of claim 1, when a cell is registered in a library, a standard cell circuit element changed according to a product specification is registered as a special cell, and the element for a special cell GDS file is registered. When extracting the size of a bipolar transistor and diode, create a GDS file for each individual cell and create a separation script to execute LVS on a cell-by-cell basis based on the cell data and cell name Then, an include file for LVS is generated based on the separation script.

  Also, from the layout data, for bipolar transistors and diodes, change their device names to the same cell names as the individual cell names, and from the cell names called by including the include file and the layout data A cell name comparison LVS process for comparing the generated cell name is performed. If no error occurs in the cell name comparison LVS process, the XOR process is performed for all registered cells and the cell locations of the layout data.

  If verification is performed as described above, even when there are a large number of elements having different detailed configurations of bipolar transistors and diodes, different cell names are automatically assigned to the respective elements, and comparison is made by cell names. . Further, since XOR processing is also performed for each cell, verification is performed at a more detailed level. Therefore, the user does not need to create individual cells for each element having different specifications as in Patent Document 1, and can easily perform design verification without leakage.

  According to the circuit design verification method of the second aspect, the normal LVS process (separated by device unit) is executed first, and if no error occurs as a result, the cell name comparison LVS process is performed. . In other words, after the LVS process at the coarser device level passes, the detailed cell level LVS process is performed on the bipolar transistor and the diode, thereby optimizing the procedure and improving the verification efficiency.

  An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a flowchart conceptually showing a processing procedure of the circuit design verification method. The layout 2 of the semiconductor integrated circuit is designed based on the circuit diagram 1. In the design, the data of the circuit element to be used is converted into a device unit cell (GDS or GDS2 format) cell library (master file) 3 Register with. The layout 2 data can also be viewed as a GDS file of cells used in the design.

  In addition, the elements used in the above design generally use a large number of standard cells prepared in advance as standard elements, which are changed according to the design specifications. Library 4 is configured (becomes part of cell library 3). Then, when extracting the size of each cell in the device unit for the special cell library 4 (step S1), the cell unit GDS file 5 divided for each individual element is created for the bipolar transistor and the diode (step S2). ). When these processes are completed, the cell unit GDS file 5 is registered in the cell library 3 together with the size information for each device (step S3).

Further, when performing cell division in step S2, a separation script is created from the cell data and the cell name (step S4). The separation script is used to select the outer shape of the cell by the cell name, and the include file generated by the separation script is arranged in the cell library 3 (verification master file).
A conventional LVS process (step S5) is performed based on a net list, which is generated based on the circuit diagram 1 and described by a device name, a GDS file of layout 2, and a GDS file of cell library 3. For each device name, verify whether the described sizes match. If an error occurs (step S6 → Yes), the LVS process is performed again after correcting the design data.

  Here, FIG. 2 shows the details of the LVS process in a modeled form. First, the input layout data 2 is separated into a MOS device, a resistance element / capacitance element, a bipolar device, and a diode device according to the device structure. Then separate each device in more detail. MOS devices are separated into four types according to the combination of N channel and P channel, and low breakdown voltage and high breakdown voltage, and resistance elements and capacitive elements are separated according to diffusion resistance and capacitor structure. Then, the gate length L and the gate width W are verified for the MOS device, the resistance value and the element width are verified for the resistance element, and the capacitance value is verified for the capacitance element. The above is the content corresponding to the conventional LVS process.

  Bipolar devices are separated by a combination of lateral PNP, vertical PNP, NPN and withstand voltage, and diode devices are separated by a combination of an ESD diode, Zener diode and withstand voltage. The number of specific points in the conventional LVS processing is insufficient, and verification is insufficient. Therefore, if the LVS process in step S5 passes (step S6 → None), the cell name comparison LVS process that is unique to the present invention is executed (step S7).

  For this reason, the net list (described by the device name) generated based on the circuit diagram 1 is converted into the net list 6 described by the cell name only for the bipolar transistor and the diode by the conversion program (step S11). Here, FIG. 4 is an example of a net list converted by the conversion program, where (a) shows a list before conversion and (b) shows a list after conversion.

In FIG. 4A, when “HS” in the row indicated by the arrow is a device name (for example, an NPN transistor) and “T4N4” sandwiched between symbols “$” is generated from the circuit diagram 1 in FIG. This comment is given a name corresponding to each cell name in the single cell GDS file 5 divided in step S2. This process is realized by setting options of a program that generates the netlist of FIG.
In the converted list shown in FIG. 4B, the device name “HS” in the row indicated by the arrow is replaced with the cell name “T4N4”. That is, the conversion program performs processing for extracting a comment in the list of FIG. 4A and replacing the device name with the comment.

  Refer to FIG. 1 again. In order to execute the cell name comparison LVS process in step S7, it is necessary to change the LVS rule file. This change is performed by generating an include file from the separation script created in step S4 and incorporating it into the LVS rule file. The LVS rule file 7 shown in FIG. 1 shows a file that has been changed as a result of taking in an include file. Note that the above-described file import (include) is performed by executing a program that includes when a cell name comparison LVS process is started.

  5A shows an example before the LVS rule file is changed, and FIG. 5B shows an example after the change. FIG. 5A shows a file used when performing the conventional LVS in step S5, in which the device name “HD” is described. In the changed file 7 shown in (b), the device name is replaced by the cell name “T4PB1” and the text “LAYOUT TEXT“ T4PB1 ”...” Is added.

  In step S7, the cell name netlist 6 and the cell single GDS file 5 of the cell library (master file) 3 are compared, and the bipolar transistor and the diode are compared by the cell name. If there is no error (step S8 → None), then XOR (COMP) processing is performed (step S9). Since the cell library 3 includes the single cell GDS file 5, XOR processing is performed for each individual cell with respect to the bipolar transistor and the diode.

  In other words, if XOR processing is performed on a cell used in layout 2 and a cell registered in a conventional cell library, the cell is expanded (breaking the hierarchical structure) when designing layout 2, and the cell If there is unnecessary data in the upper hierarchy, it cannot be verified. Therefore, in the present invention, the data of the cell library 3 in which the cell regions are individually separated from the state where there is no hierarchy is compared with the data of the layout 2. FIG. 6 shows an image of a separated area for each of the cell names T4PL1 and T4PB1.

  FIG. 3 schematically shows the XOR process in step S9. When the cell name comparison LVS in step S7 is executed, a list 8 of compared cells is created. Then, the GDS file of the layout 2, the GDS file of the cell library 3, and the cell list 8 are compared. If no error occurs (step S10 → None), a series of verification processing is terminated.

  7 to 9 show examples of lists displayed on the monitor screen of the verification apparatus as a result of executing the flow of FIG. FIG. 7A shows the result of executing the specified input of the first LVS rule file (lvs.cal), the specified input of the process file (AAA) to be verified, and the cell name comparison LVS process in step S7. FIG. 7B shows the execution result of the XOR process in step S9. FIG. 7C shows an output file output when all the verification processes are completed.

FIG. 8 shows various patterns of the execution result of the cell name comparison LVS process. FIG. 8A shows a case where there is no error (CORRECT) as in FIG. 7A. (B) shows a case where there is an error (INCORRECT), (c) shows a case where the LVS process is stopped (NOT_COMPARED), and (d) shows a case where the LVS process is not executed (NOT_EXCUTE). (E), (d) is an example of a report file when there is an error in (b), and is a message when a non-registered cell is used or when a different cell is used.
FIG. 9 shows a case where an error is included in the execution result of the XOR process in step S9. If there is an error, “ERROR” is displayed, and if the cell GDS file does not exist, “FAILED” is displayed. Is displayed.

As described above, according to this embodiment, when a cell is registered in the library 3, the standard cell circuit element changed according to the product specification is registered as the special cell 4, and the GDS file of the special cell 4 is registered. When extracting the element size, for bipolar transistors and diodes, a cell unit GDS file 5 is created, and a separation script is created to execute LVS on a cell basis based on the cell data and cell name. Then, an include file for LVS is generated based on the separation script.
Also, from the data of layout 2, for bipolar transistors and diodes, the device names are changed to the same cell names as the individual cell names, and the cell name called by including the include file and the layout The cell name comparison LVS process for comparing the cell name generated from the data 2 is performed, and if no error occurs, the XOR process is performed for all registered cells and the cell locations of the layout data.

If verification is performed as described above, even when there are many elements having different detailed configurations of bipolar transistors and diodes, different cell names are assigned to the respective elements, and comparison is performed using the cell names. Further, since XOR processing is also performed for each cell, verification is performed at a more detailed level. Therefore, the user does not need to create individual cells for each element having different specifications as in Patent Document 1, and can easily perform design verification without leakage.
The normal LVS process is executed first, and as a result, if no error occurs, the cell name comparison LVS process is performed. Therefore, after the LVS process at the coarser device level passes, the bipolar transistor and the diode are described in detail. By performing the LVS process at the cell level, the procedure can be optimized and the verification efficiency can be improved.

The present invention is not limited to the embodiments described above and shown in the drawings, and the following modifications or expansions are possible.
The cell name comparison LVS process in step S7 may be executed before executing the LVS process in step S5.

1 is a flowchart conceptually showing a processing procedure of a circuit design verification method according to an embodiment of the present invention. Diagram showing details of LVS processing The figure which shows the XOR process of step S9 modelly (A) is a diagram showing a netlist after being converted by the conversion program, and (b) is a diagram showing a netlist after the conversion. (A) is a diagram showing an example before the LVS rule file is changed, and (b) is a diagram showing an example after the change. Diagram showing the image of the area separated for each cell name The figure which shows an example of the list | wrist displayed on a monitor screen as a result of performing the flow of FIG. FIG. 7 equivalent diagram showing various patterns of the execution result of the cell name comparison LVS process FIG. 7 equivalent diagram when an error is included in the execution result of the XOR process

Explanation of symbols

  In the drawing, 1 is a circuit diagram, 2 is a layout, 3 is a cell library, 5 is a single GDS file, and 6 is a cell name netlist.

Claims (2)

LVS (Layout Versus Schematic) processing for comparing and verifying netlist data extracted from a circuit diagram and layout data designed based on the circuit diagram;
In a circuit design verification method for executing the XOR processing for comparing and verifying the layout data and a library in which element data used in the circuit diagram is registered as a cell,
When registering a cell in the library, register a circuit element defined as a standard cell as a special cell, which is changed according to the product specifications,
Regarding the GDS (Graphic Data Stream) file of the special cell, when extracting the element size, for the bipolar transistor and the diode, a GDS file of the individual cell is created and the cell data and the cell name are used. Then, when a separation script for executing LVS on a cell basis is created, an include file for LVS is generated based on the separation script,
From the layout data, for bipolar transistors and diodes, change their device names to be the same cell names as the individual cell names,
For the bipolar transistor and the diode, a cell name comparison LVS process for comparing the cell name called by including the include file with the cell name generated from the layout data is performed.
A circuit design verification method comprising: performing XOR processing for all registered cells and cell locations of layout data when no error occurs as a result of the cell name comparison LVS processing.   2. The circuit design verification method according to claim 1, wherein when a normal LVS process is executed first and no error occurs as a result, the cell name comparison LVS process is performed.

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