JP2009272465A - Silicon wafer and method of manufacturing epitaxial substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid cracking by preventing a silicon wafer from sliding on a susceptor and preventing a circumferential edge of the wafer from coming into contact with a surface of the susceptor. <P>SOLUTION: The silicon wafer is curved such that when the susceptor 20 of a vapor deposition device rotates in a state wherein the silicon wafer is placed on the susceptor 20, a portion of the wafer circumferential edge 11 does not come into contact with the surface of the susceptor 20. In the method of manufacturing an epitaxial substrate in which an epitaxial layer is formed on a principal surface of the silicon wafer 10 while the susceptor 20 of the vapor deposition device rotates in the state wherein the silicon wafer 10 is placed thereupon, the silicon wafer 10 is so curved that when the susceptor 20 rotates in the state wherein the wafer is placed on the susceptor 20, the portion of the circumferential edge 11 of the silicon wafer 10 does not come into contact with the surface of the susceptor 20. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a silicon wafer on which an epitaxial layer is formed on a main surface thereof while rotating on a susceptor of a vapor phase growth apparatus, and a method for manufacturing an epitaxial substrate composed of such a silicon wafer and an epitaxial layer.

Conventionally, in order to form an epitaxial layer on the main surface of a silicon wafer, generally, vapor phase growth apparatuses having various structures are used depending on the heating method and the shape of the susceptor. In recent years, the quality required for the epitaxial layer is becoming stricter year by year, and a single-wafer type vapor phase growth apparatus has attracted attention. Furthermore, a mini batch type vapor phase growth apparatus aiming at high productivity is also used. In general, this vapor phase growth apparatus is composed of a quartz passage-shaped or circular bell-shaped chamber, and a single or a plurality of silicon wafers are placed on a disk-shaped susceptor in which a graphite base material is coated with SiC. Heating is performed by a lamp or a high-frequency coil disposed on the front side and / or the back side, and various source gases are introduced into the chamber from a nozzle provided at the end of the chamber. In this vapor phase growth apparatus, an epitaxial layer is formed on the main surface of a silicon wafer while the silicon wafer is placed on a disk-shaped susceptor and rotated (see, for example, Patent Documents 1 and 2).
Japanese Patent Laying-Open No. 2001-35800 (Description [0034], FIG. 1) JP 2003-197532 A (specifications [0004] to [0006], FIG. 8)

  However, in order to grow an epitaxial layer on the main surface of a silicon wafer placed on the susceptor using such a vapor phase growth apparatus, the wafer 1 is generally placed on the susceptor 2 and the susceptor 2 is rotated in that state. Heating is started and the temperature is raised to a predetermined temperature. At this time, when a wafer 1 with relatively high flatness is placed on the susceptor 2, the entire periphery of the wafer contacts the surface of the susceptor 2, and particularly when the silicon wafer 1 is convex, the back surface and the susceptor 2. A sealed space is formed between the two. Even if the wafer is stationary on the susceptor immediately after being placed on the susceptor, when the susceptor 2 is rotated and heating is started, the carrier gas accumulated in the space between the wafer back surface and the susceptor 2 expands due to the heating. The silicon wafer 1 is lifted from the susceptor 2. If the susceptor 2 rotates while the wafer 1 is floating, the wafer 1 may slide on the susceptor 2. Furthermore, in the high-frequency heating method, the wafer is heated indirectly by heating the susceptor, so if the wafer is heated, it will warp in a concave shape, resulting in uneven temperature in the wafer surface, slip, epitaxial layer resistivity, thickness There was also a symptom of poor quality.

  Here, in order to prevent positioning and movement of the wafer 1 on the susceptor 2 and to make the temperature in the wafer surface uniform, a concave spot facing 3 is formed, and the wafer 1 is placed at the center of the spot facing 3. However, when the wafer 1 moves inside the counterbore 3, a part of its peripheral edge comes into contact with the side wall of the counterbore 3 constituting the surface of the susceptor 2. When epitaxial growth is performed while the peripheral edge of the wafer 1 is in contact with the side wall of the counterbore 3, the temperature distribution in the wafer surface changes greatly at the contact portion, causing slippage and reducing the yield of the epitaxial substrate. There is a bug to do.

  Further, if the peripheral edge of the silicon wafer 1 is in contact with the side wall of the spot facing 3 constituting the surface of the susceptor 2, the temperature distribution becomes uneven on the silicon wafer 1 during epitaxial growth. There is also a problem that the resistance distribution is deteriorated and the uniformity of the layer is deteriorated. Further, when epitaxial growth is performed while a part of the peripheral edge of the wafer 1 is in contact with the side wall of the spot facing 3, an epitaxial layer grows between the surface of the wafer 1 and the side wall of the spot facing 3, and the grown epitaxial layer becomes There is also a problem that the wafer 1 is cracked when the peripheral edge of the wafer and the counterbore side wall are connected and then the wafer 1 is removed from the susceptor 2.

  An object of the present invention is to provide a silicon wafer that can prevent slipping at the bottom face of the counterbore on the susceptor, and thereby an epitaxial substrate that can avoid cracking by preventing the peripheral edge of the wafer from contacting the counterbore side wall of the susceptor It is in providing the manufacturing method of.

  As shown in FIG. 1, when the temperature of the silicon wafer placed on the susceptor 20 of the vapor phase growth apparatus is raised while rotating the susceptor 20, as shown in FIG. The silicon wafer is characterized in that a warp is formed so as to create a space between the portion and the counterbore bottom surface of the susceptor 20.

  The invention according to claim 2 is an improvement of an epitaxial substrate manufacturing method in which an epitaxial layer is formed on the main surface of the silicon wafer 10 while the silicon wafer 10 is placed on the susceptor 20 of the vapor phase growth apparatus and rotated.

  The characteristic point is that the silicon wafer 10 is warped such that a part of the peripheral edge portion 11 of the silicon wafer 10 does not come into contact with the surface of the susceptor 20 when the susceptor 20 rotates while being placed on the susceptor 20. .

  In the method for manufacturing the silicon wafer described in claim 1 and the epitaxial substrate described in claim 2, the silicon wafer 10 having a large warp is intentionally formed, and warpage after epi does not affect warpage before epi. The warp causes the gap between the surface of the susceptor 20 and the silicon wafer 10 to communicate with the outside and prevents a sealed space from being formed between them, and avoids the wafer 10 from floating due to the expansion of the air in the gap therebetween. can do. As a result, the slippage of the wafer 10 on the susceptor 20 due to the floating of the wafer 10 is prevented, thereby suppressing the cracking of the wafer 10 caused by the peripheral edge 11 of the wafer 10 coming into contact with the surface of the susceptor 20. can do.

  In the method for producing a silicon wafer and epitaxial substrate of the present invention, the silicon wafer is warped such that a part of the peripheral edge of the wafer does not come into contact with the surface of the susceptor when the susceptor rotates while being placed on the susceptor of the vapor phase growth apparatus. Therefore, the warp allows the gap between the surface of the susceptor and the silicon wafer to communicate with the outside, and prevents the wafer from floating due to the expansion of the air in the gap therebetween. Therefore, the slippage of the wafer on the susceptor due to the floating of the wafer is prevented, and thereby the wafer is cracked due to the peripheral edge of the wafer contacting the surface of the susceptor, and the epitaxial layer resistivity and thickness are in the plane. Distribution degradation and occurrence of slip can be suppressed.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
As shown in FIG. 1, the silicon wafer 10 of the present invention is placed on a susceptor 20 of a vapor phase growth apparatus, and when the susceptor 20 rotates in this state, a part of the wafer peripheral portion 11 does not contact the surface of the susceptor 20. It is characterized by warping like this. Here, the wafer 10 placed on the susceptor 20 moves during the rotation of the susceptor 20 because the carrier gas accumulated between the back surface of the silicon wafer 10 and the susceptor 20 is expanded by heating, and the silicon wafer 10 is moved. The silicon wafer 10 of the present invention is intentionally made to have a large warped silicon wafer 10, and the warpage of the counterbore 21 of the susceptor 20, the silicon wafer 10, and the like are considered to be caused by floating from the susceptor 20. In this case, the gap is communicated to the outside to prevent the wafer 10 from floating from the susceptor 20 and to prevent slippage caused by the wafer 10 floating. Here, the shape of the warpage is not limited to a symmetrical shape such as a hat shape or a bowl shape. Moreover, the clearance gap should just exist between the counterbore 21 bottom face and the silicon wafer 10 until it reaches a state where the wafer is softened by heat and cannot move.

  Here, although the silicon wafer 10 is made by slicing a silicon ingot, the warp of the silicon wafer 10 is preferably applied at the time of slicing. Specifically, a silicon wafer 10 having a desired warp can be obtained by adopting a method such as slicing that changes the outer peripheral portion so that the so-called internal tooth-shaped ID saw has a non-uniform thickness. . On the other hand, even when the silicon ingot is sliced with a wire saw, the silicon wafer 10 having a desired warp can be obtained by cutting the warp value to be described later.

  In general, a warp value and a bow value are known as indices representing warpage of the wafer 10. This warp value is expressed as a difference between the maximum displacement and the minimum displacement of the center plane of the wafer 10 from the reference plane on the back surface of the wafer 10, and the reference plane at this time is made by three points on the back surface of the wafer 10 or a best fit criterion. Is. On the other hand, the bow value is expressed by the displacement from the center reference plane of the wafer 10 to the center plane at the midpoint of the wafer 10, and the center reference plane at this time is formed by three points on the center plane or the best fit reference. Is. Therefore, in the bow value, the one represented by the plus (+) sign has a convex warp, and the one represented by a minus (-) sign has a concave warp.

  As a warp in which a part of the peripheral portion 11 of the silicon wafer does not contact the surface of the susceptor 20, the silicon wafer 10 having an outer diameter of 6 inches and a thickness of 600 μm has a warp value of 20 μm to 80 μm. It can be mentioned that the value is within a range of −30 μm to +30 μm. Further, in the case of the silicon wafer 10 having an outer diameter of 8 inches and a thickness of 700 μm, the warp value is in the range of 20 μm to 40 μm, and the bow value is in the range of −30 μm to +30 μm. The reason why the warp value of each wafer 10 is 20 μm or more is to prevent a part of the wafer peripheral portion 11 from coming into contact with the surface of the susceptor 20. This is because it is difficult to avoid contact with the surface. Further, the warp value of the 6-inch wafer 10 is set to 80 μm or less, and the warp value of the 8-inch wafer 10 is set to 40 μm or less. When the warp value exceeds 80 μm or 40 μm, the warpage of the wafer 10 becomes larger than necessary. This is because the temperature distribution in the wafer surface becomes unstable. The reason why the bow value is within the range of −30 to +30 μm is to obtain a convex or saddle-shaped wafer 10 and to ensure the flatness of the wafer 10, and the bow value is within a range of −30 to +30 μm (− ) Direction, the outer peripheral portion of the wafer is lifted up too much, and the temperature distribution of the wafer becomes worse, causing slip and deterioration of the specific resistance distribution. Further, when the bow value exceeds the (+) direction, the warpage of the wafer 10 becomes larger than necessary. Here, the more preferable value of the warp value in the 6-inch wafer 10 is 20 μm or more and 70 μm or less, and the more preferable range of the bow value is in the range of −10 μm + 30 μm. Further, the more preferable value of the warp value in the wafer having the thickness of the 8-inch wafer 10 of 600 μm is 20 μm or more and 70 μm or less, and the more preferable range of the bow value is in the range of −10 μm + 30 μm.

  In addition, the epitaxial substrate manufacturing method of the present invention is to form an epitaxial layer on the main surface of the silicon wafer 10 having the above-described warp while the silicon wafer 10 is placed on the susceptor 20 of the vapor phase growth apparatus and rotated. That is, the silicon wafer 10 is warped such that a part of the peripheral edge portion 11 of the silicon wafer 10 does not come into contact with the surface of the susceptor 20 when the susceptor 20 rotates while being placed on the susceptor 20.

  A general susceptor 20 in a vapor phase growth apparatus has a disk shape in which SiC is coated on a graphite base material, and a counterbore 21 for preventing positioning and movement of the wafer 10 is formed on the upper surface of the susceptor 20. Is done. The outer diameter of the counterbore 21 is formed to be larger than the outer diameter of the wafer 10 to be placed, the silicon wafer 10 is placed on the central portion of the counterbore 21, and the gap between the counterbore 21 and the edge portion of the wafer 10 is circumferential. There are gaps around the entire circumference. When the epitaxial layer is formed on the main surface of the silicon wafer 10, the susceptor 20 is rotated, but when the susceptor 20 rotates, a part of the peripheral edge 11 of the silicon wafer 10 placed on the susceptor 20 is the surface of the susceptor 20. The silicon wafer 10 is warped so as not to contact the wafer. Specifically, if the silicon wafer 10 has outer diameters of 6 inches and 8 inches, the warp value is 20 μm or more and 80 μm or less, and the bow value is in the range of −30 μm to +30 μm. Then, the susceptor 20 is heated by a lamp or the like, and various source gases are introduced into the chamber from the nozzle portion to form an epitaxial layer on the main surface of the silicon wafer 10.

  When the silicon wafer 10 is warped such that a part of the peripheral edge portion 11 of the silicon wafer 10 does not contact the surface of the susceptor 20, the carrier gas accumulated between the back surface of the silicon wafer 10 and the susceptor 20 is It becomes easy to escape from the gap between the edge of the silicon wafer 10 and the bottom surface of the outer periphery of the susceptor 20, and the carrier gas accumulated between the back surface of the silicon wafer 10 and the susceptor 20 expands by heating, so that the silicon wafer 10 is removed from the susceptor 20. It wo n’t float. Therefore, the slip of the wafer 10 due to the silicon wafer 10 floating from the susceptor 20 is suppressed, and a situation where the side wall of the susceptor 20 counterbore 21 and the edge of the wafer 10 come into contact can be effectively avoided.

  Here, a preferable situation of the wafer 10 is that when the wafer 10 is set on the spot facing 21, the gap between the outer peripheral portion of the bottom face of the spot facing 21 and the edge of the wafer 10 is 10 to 50 μm is a part of the entire circumference or 1 / 2 rounds are generated, and there is no slip when the wafer 10 is placed on the counterbore 21. During the epi growth after the temperature rise is completed, the counterbore 21 and the wafer 10 are in contact with each other around the center of gravity position 2 / 3r. Thus, the edge portion is not so far away from the surface of the susceptor 20 so that the temperature on the surface of the wafer 10 is uniform. If there is such an interval, when the wafer is rotated and heating is started and the temperature is raised, the wafer does not float due to the expansion of the carrier gas, that is, the wafer does not move on the bottom face of the counterbore. It reaches a state where it becomes softened by heat and stops moving. This configuration was achieved with the warp and bow values of the pre-epi silicon wafer described.

  In the method of manufacturing the silicon wafer 10 and the epitaxial substrate according to the present invention, since one end of the silicon wafer 10 can be prevented from coming into contact with the side wall of the counterbore, slip does not occur even when epitaxial growth is performed. It is possible to avoid a reduction in the yield of the epitaxial substrate 10 to be performed. Further, the temperature distribution of the silicon wafer 10 during the epitaxial growth becomes uniform, and the specific resistance distribution of the epitaxial film can be made uniform. Furthermore, the surface of the wafer 10 and the side wall of the susceptor 20 are not connected in the epitaxial layer, and a situation in which the wafer 10 breaks when the wafer 10 is removed from the susceptor 20 can be avoided. it can.

  The preferable value of the epi thickness in the present invention is 50 μm or more and 180 μm or less. If the thickness of the epi is thin, the stress of the epi layer is small, so the in-plane shape of the warp of the silicon wafer (substrate) before the epi affects the warp after the epi, but the epi is thick, for example, When the thickness is 50 μm or more, the in-plane shape of the substrate warp does not affect the warp after epi, and the factor of the in-plane shape of the warp due to the thickness of the epi increases. Further, when the epi is thick, the influence due to the epi growth thickness is large, and the effect of the present invention cannot be obtained. In other words, the present invention takes into consideration the influence of the warp of the substrate in the thickness epi and forms an optimal warp with the warp value and the bow value. The result was a product with good layer thickness resistance distribution. The temperature at which the wafer softens due to heat and stops moving is 900 ° C. or lower, and if it is higher, it can be visually confirmed, but no movement is observed in any warp of the wafer. In other words, the present invention is a technique for preventing a part of the peripheral portion 11 of the silicon wafer 10 from contacting the surface of the susceptor 20 at 900 ° C. or lower.

<Example 1>
As shown in FIG. 1, a silicon wafer 10 was placed on a counterbore 21 of a susceptor 20 in a high-frequency heating type mini-batch vapor phase growth apparatus. In this state, while the susceptor 20 is rotated at a speed of 10 rpm, the susceptor and the wafer are heated with a lamp to raise the temperature and heated to 1150 to 1100 ° C. which is a reaction temperature, and then SiHC1 ₃ is added to the silicon source. As a result, epitaxial films having a thickness of about 60 μm were grown on the main surfaces of the seven silicon wafers 10 respectively. The silicon wafer 10 used at this time has an outer diameter of 6 inches and a thickness of 600 μm. The warpage of each of the seven silicon wafers 10 is 5, 10, 20, 25, 35, 53, 64 μm in the warp value, and also in the bow value in the order of −3, +7, −4, +25, +40, − 5, +12 μm.

  When each silicon wafer 10 is mounted on the counterbore 21 of the susceptor 20, it is confirmed that the silicon wafer 10 does not move in the counterbore, and then the wafer is not moved even when the temperature is increased by rotating the susceptor. The slip in the spot facing was confirmed visually. Further, after the epitaxial film is grown, the presence or absence of slippage of the wafer 10 placed on the spot facing 21 is visually confirmed, and the wafer 10 on which the epitaxial layer is formed is actually taken out from the susceptor 20 and imaged by a microscope and a CCD sensor. The presence or absence of cracks was confirmed. The results are shown in Table 1 together with the warpage size.

表１から明らかなように、ウェーハの形状が凸型で面内の凹凸が有る物が良かった。ワープ値及びバウ値が（５μｍ、−３μｍ）、（１０μｍ，＋７μｍ）及び（３５μｍ，＋４０μｍ）の反りを有する番号５〜７におけるシリコンウェーハ１０は、座ぐり２１の中で滑っているのが確認された。これは、サセプタ２０に載せたウェーハ１０の周縁部がサセプタ２０の座ぐり２１底部に接触して、座ぐり底面とウェーハ裏面の間に密閉空間を形成し、その空間に溜まったキャリアガスが加熱により膨張してシリコンウェーハ１０が浮かんでサセプタの回転による遠心力ですべってしまい、サセプタ座ぐりの側壁に移動したことによるものと考えられる。そして、これらの比抵抗、厚さは、座ぐり２１の側壁に接触している部分が分布が悪くなっているのが観察された。そして（５μｍ、−３μｍ）のそりを有するシリコンウェーハ１０にあっては、エピタキシャル層を形成した後に割れ、及び小さなクラックが発生した。

As apparent from Table 1, a wafer having a convex shape and in-plane irregularities was good. It is confirmed that the silicon wafers 10 in the numbers 5 to 7 having warps and bow values of (5 μm, −3 μm), (10 μm, +7 μm) and (35 μm, +40 μm) are slipping in the counterbore 21. It was done. This is because the peripheral portion of the wafer 10 placed on the susceptor 20 contacts the bottom of the counterbore 21 of the susceptor 20 to form a sealed space between the bottom surface of the counterbore and the back surface of the wafer, and the carrier gas accumulated in the space is heated. This is considered to be due to the fact that the silicon wafer 10 floats and slips due to the centrifugal force generated by the rotation of the susceptor and moves to the side wall of the susceptor counterbore. And it was observed that the specific resistance and thickness of the part in contact with the side wall of the spot facing 21 are poorly distributed. In the silicon wafer 10 having a warp of (5 μm, −3 μm), cracks and small cracks occurred after the epitaxial layer was formed.

  However, the other wafers 10 were not observed to slip, cracks at the edge of the wafer 10, and cracks. This is considered to be because the gap between the susceptor 20 and the silicon wafer 10 communicates with the outside due to the warpage applied to the silicon wafer 10 and the wafer 10 is prevented from floating from the susceptor 20.

<Example 2>
An epitaxial film having a thickness of about 100 μm was grown on the main surface of two silicon wafers 10 under the same temperature conditions as in Example 1 using a lamp heating type single wafer vapor phase growth apparatus. The silicon wafer 10 used at this time has an outer diameter of 8 inches and a thickness of 600 μm. The warpage of each of the two silicon wafers 10 was 15 μm and 35 μm in the warp value, and +18 μm and +28 μm in turn in the bow value.

  After growing an epitaxial film on each silicon wafer 10, the presence or absence of slippage of the wafer 10 placed on the spot face 21 is visually confirmed, and the wafer 10 on which the epitaxial layer has been formed is actually taken out of the susceptor 20 and microscope. And the presence or absence of a crack was confirmed in the image by a CCD sensor. The results are shown in Table 2 together with the warpage size.

表２より明らかなように、８インチのシリコンウェーハ１０では、ワープ値及びバウ値が（１５μｍ、＋１８μｍ）のものにおいてウェーハ１０の滑りは確認されたが、割れには至っていなかった。スティッキングしたもののぎりぎりのところで割れには至っていないと考える。一方、ワープ値及びバウ値が（３５μｍ、＋２８μｍ）のものにおいては問題がなかった。これは、ワープ値及びバウ値が（１５μｍ、＋１８μｍ）のものは反りが足りずにシリコンウェーハ１０が浮かんでしまったことによるものと考えられ、ワープ値及びバウ値が（３５μｍ、＋２８μｍ）のものにおいては、シリコンウェーハ１０の浮きを防止するに足りる反りが付されていたことによるものと考えられる。

As is apparent from Table 2, in the 8-inch silicon wafer 10, slipping of the wafer 10 was confirmed when the warp value and the bow value were (15 μm, +18 μm), but no crack was reached. I think that there is no crack at the last minute of the sticking. On the other hand, there was no problem when the warp value and the bow value were (35 μm, +28 μm). This is because the warp value and bow value (15 μm, +18 μm) are considered to be due to the fact that the silicon wafer 10 floated due to insufficient warpage, and the warp value and bow value (35 μm, +28 μm). In this case, it is considered that the warp sufficient to prevent the silicon wafer 10 from being lifted was added.

It is sectional drawing which shows the state which mounted the wafer of embodiment of this invention on the susceptor. It is sectional drawing corresponding to FIG. 1 which shows the state which mounted the conventional wafer on the susceptor.

Explanation of symbols

10 silicon wafer 11 peripheral edge 20 susceptor

Claims (2)

  In a silicon wafer placed on a susceptor of a vapor phase growth apparatus, when the temperature is raised while rotating the susceptor, a warp is generated so that a space is generated between a part of the peripheral edge of the back surface of the wafer and the bottom surface of the counterbore of the susceptor. A silicon wafer characterized by In an epitaxial substrate manufacturing method for forming an epitaxial layer on the main surface of the silicon wafer while rotating the silicon wafer on a susceptor of a vapor phase growth apparatus,
A method of manufacturing an epitaxial substrate, wherein a warp is applied to the silicon wafer so that a part of a peripheral edge of the silicon wafer does not contact the surface of the susceptor when the susceptor rotates in a state of being placed on the susceptor. .

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