JP2009272388A5

JP2009272388A5 -

Info

Publication number: JP2009272388A5
Application number: JP2008119996A
Authority: JP
Filing date: 2008-05-01
Publication date: 2011-12-15
Anticipated expiration: 2028-05-01

Claims

Of the plurality of semiconductor elements, a first semiconductor element having a defect region and a second semiconductor element stacked on the first semiconductor element, wherein the second semiconductor element is stacked when stacked on the first semiconductor element. An element selection step of selecting a pair with a second semiconductor element that does not cause malfunction due to the defective area in a normal area;
A method for manufacturing a stacked semiconductor device, comprising: an element stacking step of stacking the first semiconductor element and the second semiconductor element selected in the element selecting step.

In the element selection step, a semiconductor element having a defect region at a position corresponding to the defect region of the first semiconductor element is selected as the second semiconductor element,
The said 1st semiconductor element and the said 2nd semiconductor element are mutually laminated | stacked at the said element lamination | stacking step so that the said defect area | region of the said 1st semiconductor element and the said defect area | region of the 2nd semiconductor element may mutually overlap. 2. A method for producing a laminated semiconductor device according to 1.

The plurality of semiconductor elements each have a plurality of regions that function independently,
3. The stacked semiconductor device according to claim 2, wherein in the element selection step, a set of the first semiconductor element and the second semiconductor element is selected so that the number of the normal regions overlapping each other when stacked is increased. Element manufacturing method.

In the element selection step, as at least one of the first semiconductor element and the second semiconductor element, at least one of the defect area in the same semiconductor element and the defect area of the stacked semiconductor element on the other side is relieved. 4. The method for manufacturing a laminated semiconductor device according to claim 1, wherein a semiconductor device having a redundant circuit is selected.

5. The method for manufacturing a stacked semiconductor device according to claim 4, further comprising a wiring cutting step of cutting a wiring that is connected to the redundant circuit and is not used in a stacked state in order to relieve the defective area by the redundant circuit. .

In the wiring cutting step, when the defect region of the first semiconductor element overlaps the normal region of the second semiconductor element, the redundancy circuit provided in the first semiconductor element and the defect of the first semiconductor element The method for manufacturing a laminated semiconductor device according to claim 5, wherein wiring other than the wiring connecting the region is cut.

In the wiring cutting step, when the defect region of the first semiconductor element overlaps the normal region of the second semiconductor element, the redundancy circuit provided in the second semiconductor element and the defect of the first semiconductor element The method for manufacturing a laminated semiconductor device according to claim 5, wherein wiring other than the wiring connecting the region is cut.

In the element selection step, a sum of the number of the defective regions that can be repaired by the redundant circuit in the first semiconductor element and the number of the defective regions that can be repaired by the redundant circuit in the second semiconductor element is the first semiconductor element. 8. The set of the first semiconductor element and the second semiconductor element is selected so as to be equal to or greater than the sum of the number of the defect regions of the element and the number of the defect regions of the second semiconductor element. The method for manufacturing a laminated semiconductor device according to any one of the above.

A defect detection step of detecting a defect content of the plurality of semiconductor elements;
9. The method for manufacturing a stacked semiconductor element according to claim 1, wherein, in the element selection stage, a set of the semiconductor elements is selected based on the content of the defect detected in the defect detection stage.

The method of manufacturing a stacked semiconductor device according to claim 9, wherein the content of the defect includes at least one of presence / absence of a defect, the number of defects, a position where the defect is generated, and whether repair or repair is possible.

The plurality of semiconductor elements include a first semiconductor element group and a second semiconductor element group,
The defect detecting step detects a defect content of each of the semiconductor elements in the first semiconductor element group, and detects a defect content of each of the semiconductor elements in the second semiconductor element group. A second defect detection stage,
In the element selection step, based on the content of the defect, the semiconductor element to be the first semiconductor element is selected from the first semiconductor element group, and the second semiconductor element is to be selected from the second semiconductor element group. The method for manufacturing a laminated semiconductor element according to claim 9 or 10, wherein a semiconductor element is selected.

12. The semiconductor device according to claim 1, wherein one of the first semiconductor element and the second semiconductor element is an individual chip that is individually separated, and the other is a semiconductor element that is formed on a wafer and is not individually separated. The method for producing a laminated semiconductor device according to Item.

A stacked semiconductor element manufacturing apparatus for manufacturing a stacked semiconductor element by stacking semiconductor elements,
Of the plurality of semiconductor elements, a first semiconductor element having a defect region and a second semiconductor element stacked on the first semiconductor element, the second semiconductor element being stacked on the first semiconductor element An element selection unit that selects a pair with a second semiconductor element that does not cause a malfunction due to the defective region in a normal region of
An apparatus for manufacturing a stacked semiconductor element, comprising: an element stacking section that stacks the first semiconductor element and the second semiconductor element selected by the element selecting section.

The element selection unit selects a semiconductor element having a defect region at a position corresponding to the defect region of the first semiconductor element as the second semiconductor element,
The element stacking unit stacks the first semiconductor element and the second semiconductor element so that the defect region of the first semiconductor element and the defect region of the second semiconductor element overlap each other. 14. The laminated semiconductor device manufacturing apparatus according to 13.

The stacked semiconductor device according to claim 14, wherein the element selection unit selects a set of the first semiconductor element and the second semiconductor element so that the number of the normal regions that overlap each other when stacked is increased. Element manufacturing equipment.

In the element selection section, as at least one of the first semiconductor element and the second semiconductor element, at least one of the defect area in the same semiconductor element and the defect area of the stacked counterpart semiconductor element is relieved. The laminated semiconductor device manufacturing apparatus according to claim 13, wherein a semiconductor device having a redundant circuit is selected.

The stacked semiconductor device manufacturing apparatus according to claim 16, further comprising: a wiring cutting unit that cuts a wiring that is connected to the redundant circuit and is not used in a stacked state in order to relieve the defective region by the redundant circuit. .

The wiring cutting unit may include the redundant circuit provided in the first semiconductor element and the defect of the first semiconductor element when the defective area of the first semiconductor element overlaps the normal area of the second semiconductor element. The laminated semiconductor device manufacturing apparatus according to claim 17, wherein wiring other than the wiring connecting the region is cut.

The wiring cutting unit may include the redundant circuit provided in the second semiconductor element and the defect of the first semiconductor element when the defective area of the first semiconductor element overlaps the normal area of the second semiconductor element. The laminated semiconductor device manufacturing apparatus according to claim 17, wherein wiring other than the wiring connecting the region is cut.

The element selection unit is configured such that a sum of a number of the defective regions that can be repaired by the redundant circuit in the first semiconductor element and a number of the defective regions that can be repaired by the redundant circuit in the second semiconductor element 20. The set of the first semiconductor element and the second semiconductor element is selected so as to be equal to or greater than the sum of the number of the defect regions of the element and the number of the defect regions of the second semiconductor element. The laminated semiconductor device manufacturing apparatus according to any one of the above.

A defect detector for detecting the content of defects in the plurality of semiconductor elements;
21. The stacked semiconductor element manufacturing apparatus according to claim 13, wherein the element selection unit selects the set of semiconductor elements based on the content of the defect detected by the defect detection unit.

The stacked semiconductor device manufacturing apparatus according to claim 21, wherein the content of the defect includes at least one of presence / absence of a defect, the number of defects, a position where the defect is generated, and whether repair or repair is possible.

The defect detection unit includes a defect content of each semiconductor element of the first semiconductor element group among the plurality of semiconductor elements and a defect content of each semiconductor element of the second semiconductor element group among the plurality of semiconductor elements. And detect
The element selection unit selects the semiconductor element to be the first semiconductor element from the first semiconductor element group based on the content of the defect, and the second semiconductor element from the second semiconductor element group. The laminated semiconductor device manufacturing apparatus according to claim 21 or 22, wherein a semiconductor device is selected.

The first semiconductor element, which is an individual chip separated individually, and the second semiconductor element, which is a semiconductor element formed on a wafer and before being individually separated, are stacked. The laminated semiconductor device manufacturing apparatus according to 1.