JP2009272328A - Method and apparatus for manufacturing silicon oxide semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a post ion-implantation heat treatment method and an apparatus for improving characteristics of an SiC element. <P>SOLUTION: The method is provided with: a step for implanting ion seeds into a silicon carbide substrate; a step for holding the silicon carbide substrate on a first portion at a first heat treatment processing temperature, and depositing the silicon carbide evaporated at a second portion different from the first portion to the surface of the silicon carbide substrate; and a step for performing heat treatment for activating the implanted ion seeds by controlling the temperature of the silicon carbide substrate at a second temperature higher than the first heat treatment temperature subsequently to or simultaneously with the step for depositing the silicon carbide. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method and an apparatus for manufacturing a silicon carbide semiconductor element including an activation process of implanted ion species.

In silicon carbide power semiconductor elements, the formation of impurity layers by ion implantation is widely performed. However, due to the heat treatment for activating the implanted ion species, silicon escape from the silicon carbide surface may occur, resulting in surface roughness. Are known. As a result of this silicon loss, a carbon excess layer is formed on the surface of the silicon carbide semiconductor, and the presence of this carbon excess layer causes an increase in leakage current, causing problems in the electrical characteristics of the semiconductor device. In order to solve this problem, the sacrificial oxide film removal step is essential after performing the sacrificial oxidation. The sacrificial oxidation referred to here is thermal oxidation. Speed varies greatly. That is, the thermal oxidation rate at the site where the impurities are ion-implanted is considerably higher than that at the site where the impurities are not implanted, so the thermal oxide film at the site where the ions are implanted is thicker than the region where the impurity is not implanted. .

  For this reason, when the sacrificial oxide layer is removed with hydrofluoric acid or the like, since the oxidation of the ion-implanted part has progressed deeply, it is dug deeper than the part not ion-implanted. Such unevenness on the surface causes unevenness of the film thickness when the gate oxide film is formed, thereby impairing the reliability of the gate insulating film.

  On the other hand, various methods for suppressing surface roughness have been disclosed (for example, see Patent Document 1). Specifically, after forming an organic film pattern such as a photoresist, impurity ions are implanted, and then the organic film is carbonized to form a graphite film, and high-temperature heat treatment is performed using this graphite film as a mask. According to such a method, since the organic film is masked with the carbonized graphite film, surface roughness under the mask can be suppressed.

  As described above, when an organic graphite film is used, impurities contained in the organic solvent do not diffuse into the silicon carbide substrate, and the electrical characteristics of the semiconductor element can be prevented from being affected. .

Further, during the epitaxial growth of silicon carbide, silane (SiH ₄ ) gas and propane (C ₃ H ₈ ) gas are used as growth gases, and after the epitaxial growth is completed, a heat treatment process is performed in a mixed gas atmosphere of hydrogen gas and propane gas. A method for suppressing surface roughness has also been disclosed (see Patent Document 2).

In addition, the silicon carbide substrate after the ion implantation is heated in a heating vessel covered with silicon carbide to activate the ion-implanted impurities and from the silicon carbide gas sublimated from the surface of the heating vessel. Also disclosed is a method of depositing silicon carbide on a substrate to prevent surface roughness (see Patent Document 3).
JP 2005-260267 A JP 2006-332495 A JP 2008-034464 A

  However, in the method described in Patent Document 1, since the graphite film is formed with the organic film pattern used for ion implantation, the graphite film is not formed in the opening for ion implantation. Not protected.

  Therefore, in the opening where the graphite film is not formed, silicon is sublimated by the high temperature heat treatment to form a carbon excess layer, and the surface becomes rough. For this reason, it is presumed that the sacrificial oxidation process cannot be omitted in order to remove the carbon excess layer during the manufacture of the semiconductor device, and the above-described surface unevenness cannot be avoided.

  Further, in the method of Patent Document 2, it is difficult to manage the composition ratio of the growth gas (silane and propane gas), and thickness variations and reproducibility problems are expected. In addition, an increase in the size of the growth gas supply device and the like is expected, and the manufacturing apparatus becomes expensive.

  Moreover, in the method of patent document 3, since the silicon carbide layer coated on the surface of the heating container is used as the silicon carbide source, it is predicted that the flatness of the source surface is poor and the supply rate by sublimation is unstable. For this reason, it is difficult to obtain a silicon carbide film having a uniform thickness in the wafer surface.

  The present invention has been made in view of the above circumstances, and its object is to provide a silicon carbide semiconductor that can maintain a clean surface without causing surface irregularities even after activation heat treatment. An object is to provide an element manufacturing method and a simple manufacturing apparatus.

  In order to solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a step of implanting ionic species into a silicon carbide substrate, and the silicon carbide substrate is held at a first location at a first heat treatment temperature. And a step of depositing silicon carbide sublimated at a second location different from the first location on the surface of the silicon carbide substrate, and a second temperature higher than the first heat treatment temperature. And a step of performing a heat treatment for activating the implanted ion species by controlling the temperature of the silicon carbide substrate.

  The silicon carbide semiconductor element manufacturing apparatus of the present invention includes a supply source holding mechanism for holding a silicon carbide supply source, and a substrate for holding a silicon carbide substrate in the same space when the silicon carbide supply source is installed. The surface of the silicon carbide substrate is coated with a holding mechanism, a sublimation means for raising the temperature of the silicon carbide supply source to 1600 ° C. or higher and sublimating the silicon carbide, and silicon carbide by sublimation from the silicon carbide supply source. A heating means for holding the silicon carbide substrate at a first temperature and heat-treating the silicon carbide substrate at a second temperature higher than the first temperature after the silicon carbide is coated. It is characterized by doing.

  ADVANTAGE OF THE INVENTION According to this invention, even if it performs activation heat processing, the unevenness | corrugation of a surface is not caused and the manufacturing method and simple manufacturing apparatus of a silicon carbide semiconductor element which can maintain a clean surface can be provided.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view of a silicon carbide semiconductor device according to the first embodiment of the present invention, and shows a normally-off type n-channel planar type vertical power MOSFET. On the main surface of the (0001) plane n ⁺ type substrate 11 of 4H-silicon carbide, an n ⁻ type epitaxial layer 12 having a nitrogen concentration lower than that of the substrate 11 is formed.

A p-type base region 13 is formed in the surface layer portion of the n ⁻ -type epitaxial layer 12. This base region 13 is formed by Al multi-stage ion implantation, and has a concentration of 1 × 10 ¹⁷ / cm ³ or more. Further, an n ⁺ -type source region 14 shallower than the p-type base region 13 is formed in the surface layer portion of the p-type base region 13. Further, an n ⁻ type surface channel layer 15 is formed on the surface portion of the p type base region 13 so as to connect the n ⁺ type source region 14 and the n ⁻ type epitaxial layer 12.

A gate oxide film 16 is formed on the upper surface of the surface channel 15 and the n ⁺ -type source region 14 by thermal oxidation, and a gate electrode 17 is formed on the gate oxide film 16. The gate electrode 17 is covered with a SiO ₂ insulating film 18 formed by chemical vapor deposition (CVD), and an n ⁺ -type source region 14 and a p-type base region 13 are formed on the insulating film 18. An electrically connected source electrode 19 is formed to constitute a vertical power MOSFET.

Next, the manufacturing process of the vertical power MOSFET shown in FIG. 1 will be described with reference to the flowchart of FIG. First, an n-type 4H silicon carbide semiconductor substrate 11 on which an n ⁻ -type epitaxial layer 12 is formed is prepared (S1).

A p-type base region 13 is formed in the epitaxial layer 12 (S2). More specifically, a photoresist is applied on the epitaxial layer 12. After performing pre-baking, exposure and development are performed using a glass mask for forming alignment marks. After post-baking, reactive ion etching is performed to form alignment marks. Thereafter, after removing the photoresist, SiO ₂ is deposited by the CVD method, and then the photoresist is applied again. After pre-baking, exposure and development are performed using a glass mask for patterning the SiO ₂ . After post-baking, a region that will later become the p-type base region 13 is exposed by reactive ion etching. In this state, aluminum (Al) which is a p-type impurity is ion-implanted. The conditions at this time are a substrate temperature of 500 ° C. and a dose of 3 × 10 ¹⁴ / cm ² . Thereby, the p-type base region 13 is formed. Thereafter, SiO ₂ used as a mask material is removed.

Next, an n-type source region 14 is formed (S3). Specifically, after depositing SiO ₂ on the entire surface by CVD, a photoresist is applied. After pre-baking, exposure and development are performed using a glass mask for patterning the SiO ₂ . After post-baking, a region that will later become the n ⁺ -type source region 14 is exposed by reactive ion etching. In this state, phosphorus (P) which is an n-type impurity is ion-implanted. The conditions at this time are a substrate temperature of 500 ° C. and a dose of 1 × 10 ¹⁵ / cm ² . As a result, an n ⁺ type source region 14 is formed. Thereafter, SiO ₂ used as a mask material is removed.

Next, the surface channel layer 15 is formed (S4). Specifically, SiO ₂ is again deposited on the entire surface by CVD, and then a photoresist is applied. After pre-baking, exposure and development are performed using a glass mask for patterning this SiO ₂ . After post-baking, a region that will later become the n ⁻ -type surface channel layer 15 is exposed by reactive ion etching. In this state, nitrogen (N) which is an n-type impurity is ion-implanted. The conditions at this time are a substrate temperature of 500 ° C. and a dose of 4 × 10 ¹⁴ / cm ² . As a result, the n ⁻ type surface channel layer 15 is formed. Thereafter, SiO ₂ used as a mask material is removed.

Next, a p-contact is formed in the p-type base region (S5). Specifically, SiO ₂ is again deposited on the entire surface by CVD, and then a photoresist is applied. After pre-baking, exposure and development are performed using the glass mask for patterning SiO ₂ . After the post-baking, only the region that will later be in contact with the source electrode 19 in the p ⁻ type base region 13 is exposed by reactive ion etching. In this state, Al, which is a p-type impurity, is ion-implanted. The conditions at this time are a substrate temperature of 500 ° C. and a dose of 1 × 10 ¹⁵ / cm ² . As a result, a contact region is formed in which the p-type impurity in the base region 13 is partially formed at a high concentration so as not to overlap the n ⁺ -type source region 14. Thereafter, SiO ₂ used as a mask material is removed.

  Next, a heat treatment step for activating the ion species implanted in S2 to S5 is entered. In the present embodiment, the process includes three steps of SiC layer formation (S6), heat treatment (S7), and SiC layer removal (S8). Details of this step will be described with reference to FIGS.

  FIG. 3 is a schematic cross-sectional view of the silicon carbide semiconductor manufacturing apparatus according to the first embodiment. The silicon carbide source heater 21 is a resistance heater, and can control power independently of the silicon carbide semiconductor substrate heater 22. A silicon carbide holding boat 24 is arranged inside the silicon carbide source heater 21 so that a silicon carbide source (silicon carbide supply source) 23 can be held. In the present embodiment, a high-purity semi-insulating silicon carbide single crystal bulk substrate is used as the silicon carbide source, and the aim is to eliminate contamination from the source as much as possible.

  A silicon carbide semiconductor substrate heater 22 is provided in parallel with the silicon carbide source heater 21. A silicon carbide semiconductor substrate holding boat 26 is disposed inside the silicon carbide semiconductor substrate heater 22 so that several silicon carbide semiconductor substrates 25 can be processed at a time. Silicon carbide semiconductor substrate 25 and silicon carbide source 23 are provided in the same space.

  In addition to the above configuration, another silicon carbide source heater 21 ′ may be provided on the silicon carbide semiconductor substrate heater 22 as shown in FIG. In this way, variations in the amount of silicon carbide deposited on several silicon carbide semiconductor substrates 25 can be reduced. Further, the direction of silicon carbide semiconductor substrate 25 is not limited to facing the source 23 as shown in FIG. 3, and as shown in FIG. 5, if the silicon carbide semiconductor substrate 25 is within the same space, They may be arranged in a direction perpendicular to the direction. Further, the heaters 21 and 22 may be configured in an annular shape, and one of the source 23 and the substrate 25 may be rotated.

  FIG. 6 is a diagram for explaining the temperature profile employed in the present embodiment, in which the vertical axis of the graph indicates the in-furnace position, and the left furnace configuration diagram corresponds to the position. The horizontal axis of the graph is temperature. In the step S6, electric power supplied to the silicon carbide source heater 21 and the silicon carbide semiconductor substrate heater 22 so that the temperature of the silicon carbide source 23 is 1650 ° C. and the temperature of the silicon carbide semiconductor substrate 25 is 1500 ° C., respectively. To control.

  Preliminary experiments were conducted before processing a substrate for device fabrication that was actually ion-implanted. At this time, a bulk substrate without an epitaxial growth layer is placed on the silicon carbide semiconductor substrate holding boat 26. The silicon carbide source 23 uses a high purity semi-insulating silicon carbide bulk substrate. After reaching the temperature profile in step S6 shown in FIG. 4, the power input to the silicon carbide source heater 21 and the silicon carbide semiconductor substrate heater 22 is turned off after processing for 1 hour, 2 hours, and 3 hours, respectively.

  When the bulk substrate taken out after cooling was cleaved and the cross section was observed with a scanning electron microscope, the contrast between the bulk substrate and the vapor phase growth layer formed by heat treatment was clearly observed. From the measurement result of the thickness of the vapor-grown layer, the growth rate of the vapor-grown layer in the state of step S6 was estimated and found to be about 2 μm / h. In the actual device creation process, the processing time of the step S6 is adjusted to about 12 minutes so that the vapor phase growth layer becomes 400 nm.

  In the above method, silicon carbide sublimated from silicon carbide source 23 is transported to the position of silicon carbide substrate 25 in a vapor state and deposited on silicon carbide substrate 25. In this embodiment, this method is called a sublimation transport method.

  The supply of silicon carbide by the sublimation transport method in the gas phase becomes significant when the temperature of the silicon carbide source exceeds 1600 ° C., but sublimation was not observed at a practical speed at temperatures lower than that. Moreover, although the sublimation rate tended to increase as the temperature was raised above 1650 ° C., considering that it is later removed by sacrificial oxidation, forming a thick growth layer requires a longer oxidation time. In addition, a short processing time leads to deterioration of the controllability and reproducibility of the film thickness. For this reason, the temperature range of about 1600 to 1650 ° C. was most suitable as the source temperature.

  From the above result, the holding time in the step S6 is determined to be 12 minutes. Therefore, after holding for 12 minutes, the set temperature is lowered so that the temperature of the silicon carbide source 23 becomes 1500 ° C., and at the same time, the temperature of the silicon carbide semiconductor substrate 25 becomes 1600 ° C., that is, shown in the process of S 7 in FIG. The input power is controlled so that the temperature distribution is as follows. Specifically, the input power of the silicon carbide semiconductor substrate heater 22 is increased, and after reaching 1600 ° C. for 5 minutes, the total heating is finished.

  Next, in order to remove the silicon carbide vapor phase growth layer formed in the step S6, dry oxidation is performed at 1150 ° C. in an oxidation furnace. Oxidation rate measurement experiments conducted in advance show that it takes 6 hours to oxidize the 400 nm layer grown in the step S6, so dry oxidation is performed for 6 hours. After the dry oxidized sample is taken out, the oxide film is removed with hydrofluoric acid to remove the silicon carbide vapor phase growth layer covered during the high temperature heat treatment (S8).

  Thereafter, the following steps are subsequently performed on the substrate on which the actual vertical power MOSFET is formed. That is, the gate oxide film 16 is formed on the entire surface by performing an oxidation process in a dry oxidation furnace whose atmospheric temperature is set to 1100 ° C. (S9). When the temperature is lowered, for example, by forming a wet atmosphere by a pyrogenic method using hydrogen and oxygen, the interface state density of the oxide film can be effectively reduced and the channel mobility can be increased.

  Next, on the gate insulating film 16, polysilicon is deposited at a substrate temperature of 600 ° C. by low pressure CVD, and the polysilicon is patterned to form the gate electrode 17 (S10). Subsequently, after unnecessary portions of the gate insulating film 17 are removed, an insulating film 18 made of a low temperature deposited oxide film is grown at about 400 ° C. to cover the gate insulating film 17. Further, annealing at about 1000 ° C. is performed.

  Then, after forming the source electrode 19 and the drain electrode 20 by sputtering at room temperature (S11), the planar vertical power MOSFET as shown in FIG. 1 is completed by sintering at 1000 ° C.

  As described above, in the present embodiment, when performing the treatment for activating the impurities introduced by ion implantation, silicon carbide is formed as a cap material by the sublimation transport method immediately before, so that the implanted impurities are activated. In the heat treatment, it is possible to prevent surface degradation such as silicon loss on the surface of the ion implanted portion.

  In addition, in the case of using a cap material obtained by carbonizing a photoresist, unevenness or the like due to a residue when the graphite cap material is removed occurs, but in this embodiment, there is no such concern.

  In addition, there is a concern about the deterioration of the surface protection function, such as the adhesiveness during heat treatment or the unevenness of the density of the formed graphite cap, that is, the generation of microcracks or the formation of a material containing many bubbles such as pumice. There is no need to do this, and the surface can be protected reliably.

  Further, the sacrificial oxidation performed when removing the silicon carbide of the cap material does not significantly oxidize the ion implantation layer. Accordingly, there is no step formed due to the deep oxidation of the ion implanted portion as compared with the non-implanted portion, which has been a problem in the past.

  Thus, according to this embodiment, instead of using a carbon layer formed by carbonizing a resist, silicon carbide formed by a sublimation transport method is used as a cap material, so that the resist is carbonized. In addition, there is no need to worry about problems such as generation of bubbles in organic matter or damage of resist due to bumping, and the temperature can be increased to a predetermined temperature of 1600 ° C. or higher at a high temperature increase rate, resulting in high time efficiency. The effect is obtained.

  In addition, since the cap material is formed after the ion implantation, there is no risk of occurrence of the unevenness. Furthermore, the problem that impurities in the organic solvent contained in the resist remain on the surface as a residue when the cap material is removed, and the surface cleanliness is lowered. Further, the unevenness of the gate insulating film 16 does not occur, and the deterioration of the reliability of the gate insulating film or the deterioration of device characteristics can be prevented.

(Second Embodiment)
In the first embodiment, the case of using a furnace for simultaneously heat-treating a plurality of wafers has been described as an example. However, a single-sheet processing furnace may be used. Such a case will be described as a second embodiment.

  FIG. 7 shows a high-frequency heating furnace used in the second embodiment. The graphite susceptor 41 is heated by an induction current from the high-frequency heating coil 42 so that the silicon carbide source 43 placed on the graphite susceptor 41 is heated. On the graphite susceptor 41, a susceptor cover 45 is provided for heat insulation and holding the silicon carbide semiconductor substrate 44.

  When performing high-temperature heat treatment using such an apparatus, in order to form a temperature profile as shown in FIG. 6, when the temperature of the silicon carbide source 43 is set to 1650 ° C. in the first step (step S6). Further, the positional relationship in the height direction between the high-frequency heating coil 42 and the graphite susceptor 41 is adjusted so that the temperature of the silicon carbide semiconductor substrate 44 becomes 1500 ° C.

  In the second step (step S7), although the temperature profile as shown in FIG. 6 cannot be realized, the graphite susceptor 41 is moved downward relative to the high-frequency overheating coil 42 or the input power is increased. By one or a combination of these, the temperature of silicon carbide semiconductor substrate 44 can be set to a predetermined heat treatment temperature, for example, 1600 ° C. However, at this time, the temperature of the silicon carbide source 43 becomes higher than 1600 ° C., and the growth of silicon carbide by the sublimation transport method is continued in the second step.

  However, as described in the first embodiment, the thickness of the silicon carbide film grown in the first step (step S6) and the second step (step S7) is measured in advance and controlled to, for example, 400 nm. If this is desired, the purpose can be achieved by reducing the time of the first step (step S6). Therefore, as shown in the description of the step S6 (FIG. 6) of the first embodiment. A temperature profile is not essential.

  Even if it implements as mentioned above, there can exist the same effect as a 1st embodiment.

(Third embodiment)
The third embodiment is a modification of the second embodiment. In the second embodiment, the case where the temperature of the silicon carbide source 43 part is higher than the temperature of the silicon carbide semiconductor substrate 44 in the second step has been described. However, the longitudinal temperature gradient in the figure may be set larger by decreasing the number of turns of the high-frequency heating coil 42 in FIG.

  More specifically, in the first step, as described in the first embodiment, the silicon carbide source 43 part is set to 1650 ° C., the silicon carbide semiconductor substrate 44 part temperature is 1500 ° C., and a predetermined time has elapsed. Then, the graphite susceptor 41 is lowered below the lower end of the high-frequency heating coil 42 while temporarily reducing the input power.

  Thereafter, by raising the input power of high-frequency heating coil 42 again, the temperature of silicon carbide source 43 part can be set lower than the temperature of silicon carbide semiconductor substrate 44. This makes it possible to create a temperature environment as shown in the temperature profile of the second step of FIG.

  Thus, it is only necessary that the temperatures of the silicon carbide source 43 part and the silicon carbide semiconductor substrate 44 part can be controlled independently in each step, and the heat treatment apparatus does not necessarily include a heating means for a plurality of zones.

  As described above in detail, according to the present invention, it is not necessary to form a thick graphite cap material over a long period of time, and it is possible to obtain a clean surface in which no residue remains after the activation heat treatment. In the state before film formation, it becomes possible to maintain the required surface cleanliness. Furthermore, since it is not necessary to remove the ion-implanted surface by sacrificial oxidation, an efficient dose can be secured and unnecessary implantation damage can be avoided. Due to the above effects, it is possible to prevent the reliability of the gate insulating film from being lowered, and hence the deterioration of the semiconductor element characteristics.

  The present invention is not limited to the above-described embodiments. In addition, various modifications can be made without departing from the scope of the present invention.

FIG. 3 is a schematic cross-sectional view of a vertical power MOSFET manufactured by the manufacturing method according to the first embodiment. 2 is a flowchart of a manufacturing method according to the first embodiment. 1 is a schematic cross-sectional view of a silicon carbide semiconductor element manufacturing apparatus according to a first embodiment. It is a schematic cross section of the 1st modification of the manufacturing apparatus which concerns on 1st Embodiment. It is a schematic cross section of the 2nd modification of the manufacturing apparatus which concerns on 1st Embodiment. It is an example of the temperature profile in the manufacturing apparatus of 1st Embodiment. It is a schematic cross section of a manufacturing apparatus for a silicon carbide semiconductor device according to the second embodiment.

Explanation of symbols

11 ... n ⁺ -type 4H- silicon carbide semiconductor substrate 12 ... n ^- -type epitaxial layer 13 ... p ^- -type base region 14 ... n ⁺ -type source region 15 ... surface channel layer 16 ... gate oxide film 17 ... gate electrode 18 ... insulating film DESCRIPTION OF SYMBOLS 19 ... Source electrode 20 ... Drain electrode 21 ... Silicon carbide source heater 22 ... Silicon carbide semiconductor substrate heater 23 ... Silicon carbide source 24 ... Silicon carbide holding boat 25 ... Silicon carbide semiconductor substrate 26 ... Silicon carbide semiconductor substrate holding boat 41 ... Graphite susceptor 42 ... high frequency heating coil 43 ... carbide source 44 ... silicon carbide semiconductor substrate 45 ... susceptor cover

Claims (7)

Implanting ion species into the silicon carbide substrate;
At the first heat treatment temperature, the silicon carbide substrate is held at the first location, and silicon carbide sublimated at a second location different from the first location is silicon carbide on the surface of the silicon carbide substrate. Depositing
Performing a heat treatment for activating the implanted ion species by controlling the temperature of the silicon carbide substrate to a second temperature higher than the first heat treatment temperature;
The manufacturing method of the silicon carbide semiconductor element characterized by the above-mentioned.   2. The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the step of performing the heat treatment for activating the implanted ion species is performed after the step of depositing the silicon carbide.   2. The method for manufacturing a silicon carbide semiconductor element according to claim 1, wherein the first heat treatment temperature is less than 1550 ° C. and the second heat treatment temperature is 1550 ° C. or higher. A source holding mechanism for holding a silicon carbide source;
A substrate holding mechanism for holding a silicon carbide substrate in the same space where the silicon carbide supply source is installed;
Sublimation means for raising the temperature of the silicon carbide supply source to a temperature of 1600 ° C. or higher and sublimating the silicon carbide;
When the surface of the silicon carbide substrate is coated with silicon carbide by sublimation from the silicon carbide supply source, the silicon carbide substrate is held at a first temperature, and after the silicon carbide is coated, the silicon carbide substrate Heating means for heat treatment at a second temperature higher than the first temperature;
An apparatus for manufacturing a silicon carbide semiconductor element, comprising:   The sublimation means is configured such that when the temperature of the silicon carbide supply source is raised to 1600 ° C or higher, the first temperature of the silicon carbide substrate is less than 1550 ° C. Item 5. A silicon carbide semiconductor device manufacturing apparatus according to Item 4.   The said heating means is comprised so that said 1st temperature may be less than 1550 degreeC, The manufacturing apparatus of the silicon carbide semiconductor element of Claim 4 or 5 characterized by the above-mentioned.   The sublimation means for raising the temperature of the silicon carbide supply source to 1600 ° C. or higher and sublimating the heating means for heat treating the silicon carbide substrate comprises the same heater, the supply source holding mechanism and the substrate holding mechanism, The apparatus for manufacturing a silicon carbide semiconductor element according to claim 4, wherein temperatures of the supply source holding mechanism and the substrate holding mechanism can be adjusted according to the relative positions.

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