JP2010272798A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that there is the case that desired transistor characteristics cannot be obtained when hydrogen heat treatment for natural oxide film removal is performed by a conventional method after forming an element isolation insulating film by a shallow trench isolation method. <P>SOLUTION: In the method of manufacturing a semiconductor device, to a silicon substrate, first heat treatment is performed in a reducing atmosphere containing hydrogen on condition that a temperature is within the range of 930°C-1,030°C and the time is longer than 0 second and is equal to or shorter than 30 seconds. After the first heat treatment, while keeping it in the reducing atmosphere containing the hydrogen as it is, the substrate temperature which is lower than the substrate temperature during the first heat treatment and is in the range of 900°C-980°C is maintained for the time longer than 0 second and shorter than 30 seconds and second heat treatment is performed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of removing a natural oxide film by performing a heat treatment in a reducing atmosphere containing hydrogen.

  A conventional method for forming a gate insulating film having two types of thickness will be described. First, an element isolation insulating film is formed on the surface layer portion of the silicon substrate by a shallow trench isolation method. A plurality of active regions are defined by the element isolation insulating film. By thermally oxidizing the surface of the active region, a first gate insulating film that becomes a relatively thick gate insulating film is formed.

  The active region where the relatively thick gate insulating film is to be formed is covered with a resist pattern, and the first gate insulating film on the active region where the relatively thin gate insulating film is to be formed is removed with hydrofluoric acid or the like. The resist pattern is removed using a mixed solution (SPM chemical solution) of sulfuric acid and hydrogen peroxide solution. Thereafter, the substrate surface is cleaned using a mixed solution of ammonia water and hydrogen peroxide solution (SC-1 cleaning solution) and a mixed solution of hydrochloric acid and hydrogen peroxide solution (SC-2 cleaning solution).

  By thermally oxidizing the surface of the active region, a relatively thin second gate insulating film is formed in the active region where the first gate insulating film is not formed.

  During cleaning, a natural oxide film is formed on the surface of the active region where a relatively thin gate insulating film is to be formed. A method of removing this natural oxide film by performing a heat treatment (hydrogen heat treatment) at 900 ° C. to 1050 ° C. in a hydrogen atmosphere before forming the second gate insulating film is known.

  Further, by performing heat treatment on the silicon wafer in a hydrogen atmosphere at a temperature of 1200 ° C. to 1350 ° C., crystal-origin particles (COP) introduced during crystal growth can be reduced. Subsequently, by performing heat treatment at 900 ° C. to 1200 ° C., microroughness and haze can be reduced.

JP 2004-87960 A JP 2004-152965 A JP 11-354529 A

  By performing heat treatment in a reducing atmosphere containing hydrogen, the natural oxide film can be removed and microroughness can be reduced. However, it has been found that when a heat treatment for removing a natural oxide film is performed by a conventional method after forming an element isolation insulating film by a shallow trench isolation method, desired transistor characteristics may not be obtained.

According to one aspect of the invention,
Performing a first heat treatment on a silicon substrate in a reducing atmosphere containing hydrogen at a temperature in a range of 930 ° C. to 1030 ° C., for a time longer than 0 seconds and not longer than 30 seconds;
After being placed in a reducing atmosphere containing hydrogen after the first heat treatment, the temperature is lower than the substrate temperature at the time of the first heat treatment and the substrate temperature is in the range of 900 ° C. to 980 ° C. from 0 second. And a step of performing the second heat treatment while maintaining a longer time than 30 seconds.

According to another aspect of the invention,
Performing a first heat treatment on a silicon substrate in a reducing atmosphere containing hydrogen at a temperature in a range of 950 ° C. to 1050 ° C. for a time longer than 0 seconds and 60 seconds or less;
A step of lowering the temperature of the silicon substrate at a first temperature-decreasing rate slower than −20 ° C./s as a second heat treatment while being placed in a reducing atmosphere containing hydrogen after the first heat treatment;
There is provided a method for manufacturing a semiconductor device, comprising: after the second heat treatment, lowering the temperature of the silicon substrate at a second temperature drop rate that is faster than the first temperature drop rate.

  Desired transistor characteristics can be obtained by performing the heat treatment in a hydrogen atmosphere by dividing the heat treatment into the first heat treatment and the second heat treatment.

It is sectional drawing (the 1) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by an Example. It is sectional drawing (the 2) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by an Example. It is sectional drawing (the 3) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by an Example. It is sectional drawing (the 4) of the apparatus in the middle of manufacture of the manufacturing method of the semiconductor device by an Example. FIG. 7 is a cross-sectional view (No. 5) of the device in the middle of manufacturing and a cross-sectional view of the manufactured semiconductor device of the semiconductor device manufacturing method according to the example. (2A) is a cross-sectional view in the vicinity of the boundary between the active region and the element isolation insulating film in the middle of manufacture manufactured by the method according to the embodiment, and (2B) is the activity in the middle of manufacturing manufactured by the method according to the conventional example. It is sectional drawing of the boundary vicinity of an area | region and an element isolation insulating film. It is the schematic of the rapid heating rapid cooling apparatus used in an Example. It is a graph which shows the time calendar of the substrate temperature at the time of the hydrogen heat treatment employ | adopted with the method by an Example and a modification. It is a graph which shows the relationship between the thickness of the remaining film when the silicon substrate in which the natural oxide film was formed is subjected to hydrogen heat treatment, and the hydrogen heat treatment time for each heat treatment temperature.

  A method for manufacturing a semiconductor device according to an embodiment will be described with reference to FIGS.

  As shown in FIG. 1A, after cleaning the silicon substrate 10, a buffer film 11 made of silicon oxide and having a thickness of about 10 nm is formed on the surface thereof. For example, dry oxidation or pyrogenic oxidation is used to form the buffer film 11. A mask film 12 made of silicon nitride and having a thickness of about 80 nm to 130 nm is formed on the buffer film 11. For example, chemical vapor deposition (CVD) is used to form the mask film 12.

  As shown in FIG. 1B, the mask film 12 and the buffer film 11 in a region to be an element isolation insulating region are removed. The element isolation trench 14 is formed by etching the surface layer portion of the silicon substrate 10 using the mask film 12 as an etching mask. A silicon oxide film (not shown) having a thickness of about 5 nm is formed by thermally oxidizing the inner surface of the element isolation trench 14.

  Processes up to the structure shown in FIG. 1C will be described. A silicon oxide film thicker than the depth of the element isolation trench 14 is deposited on the silicon substrate 10 by chemical vapor deposition (HDP-CVD) using high-density plasma. By performing chemical mechanical polishing (CMP), the silicon oxide film deposited above the upper surface of the mask film 12 is removed. An element isolation insulating film 15 made of silicon oxide remains in the element isolation trench 14. The element isolation insulating film 15 is densified by performing a heat treatment in a nitrogen atmosphere at a temperature of about 900 ° C.

  After densification, the mask film 12 and the buffer film 11 are removed using hydrofluoric acid and hot phosphoric acid.

  As shown in FIG. 1D, active regions 16A to 16C in which the silicon surface of the silicon substrate 10 is exposed are formed. Thereafter, cleaning with hydrofluoric acid, SC-1 cleaning liquid, and SC-2 cleaning liquid is performed.

  FIG. 2A shows an enlarged cross-sectional view of the interface between the element isolation insulating film 15 and the active region 16B. Since strain is generated at the edge of the element isolation insulating film 15, the etching rate by hydrofluoric acid or the like is higher near the edge of the element isolation insulating film 15 than at the center. For this reason, when the hydrofluoric acid treatment is performed, the vicinity of the edge of the element isolation insulating film 15 is etched deeper than the central portion, and the divot 20 is generated. The divot 20 becomes deeper every time the hydrofluoric acid treatment is repeated.

  As shown in FIG. 1E, a protective film 21 made of silicon oxide and having a thickness of about 10 nm is formed. As shown in FIG. 1F, a p-type well 25 is formed by implanting a p-type impurity such as boron (B) into the surface layer portion of the active regions 16A and 16B where NMOSFETs are to be formed. An n-type well 26 is formed by implanting an n-type impurity such as phosphorus (P) or arsenic (As) into the active region 16C where the PMOSFET is to be formed. Furthermore, impurity implantation for channel doping and threshold control is performed. After these impurity implantations, activation annealing is performed in a nitrogen atmosphere at a temperature of 900 ° C. to 1050 ° C. After the activation annealing, the protective film 21 is removed with hydrofluoric acid.

  As shown in FIG. 1G, the silicon surface of the silicon substrate 10 is exposed in the active regions 16A to 16C.

  As shown in FIG. 1H, the surfaces of the active regions 16A to 16C are wet-oxidized at a temperature of 800 ° C., thereby forming a first gate insulating film 30 having a thickness of 7 nm that becomes a relatively thick gate insulating film. To do.

  As shown in FIG. 1I, a resist pattern 31 is formed on the silicon substrate 10. The resist pattern 31 is provided with an opening 31A that encloses an active region 16B in which a relatively thin gate insulating film is to be formed in plan view. The resist pattern 31 covers the active regions 16A and 16C where the relatively thick first gate insulating film 30 is to be formed.

  As shown in FIG. 1J, the first gate insulating film 30 (FIG. 1I) exposed in the opening 31A is removed using hydrofluoric acid.

  As shown in FIG. 1K, the resist pattern 31 is removed using an SPM chemical. Further, cleaning is performed using the SC-1 cleaning liquid and the SC-2 cleaning liquid. After the cleaning, a natural oxide film 33 is formed on the surface of the active region 16B.

  As shown in FIG. 1L, in order to remove the natural oxide film 33, heat treatment (hydrogen heat treatment) is performed in a hydrogen gas atmosphere.

  FIG. 3 shows a schematic diagram of a rapid heating and rapid cooling apparatus used for this heat treatment. A wafer holding table 104 is disposed in the chamber 102. The silicon substrate 10 to be annealed is held by the wafer holder 104. A plurality of heating lamps 103 are arranged above the silicon substrate 10 held by the wafer holder 104. By turning on the heating lamp 103, the silicon substrate 10 can be rapidly heated.

  The chamber 102 is provided with a gas inlet 109 and a gas outlet 110. A gas source 106 is connected to a gas inlet 109 through a valve 108. The gas source includes a hydrogen gas source, a nitrogen gas source, an oxygen gas source, and the like. By adjusting a valve 108 provided for each gas type, hydrogen gas, nitrogen gas, oxygen gas, or a mixed gas thereof can be supplied into the chamber 102. The gas introduced into the chamber 102 is exhausted from the gas exhaust port 110 to the outside of the chamber. An exhaust pump 111 is attached to the gas exhaust port 110, and the inside of the chamber 102 can be depressurized to a pressure lower than the atmospheric pressure.

  FIG. 4A shows an example of a time calendar of the substrate temperature during the hydrogen heat treatment. 4A is a programmed temperature target value, and the actual substrate temperature does not necessarily vary linearly as shown in FIG. 4A, but is shown in FIG. 4A. Trace the time calendar approximated by the drawn line.

First, the silicon substrate 10 is loaded into the chamber 102 and hydrogen gas is supplied to make the chamber 102 an atmosphere of 100% hydrogen gas. The substrate temperature was raised to T _1, to maintain a constant state of temperature T ₁ of the 600 ° C. or less time. Maintaining the state of the temperature T ₁ of a certain time, in order to equalize the temperature of the silicon substrate 10 in the plane. Thereafter, the substrate temperature is increased to T _2. The substrate temperature _{T 2} is, for example, 1000 ° C.. The substrate temperature at time _{t 1} reaches _{T 2,} the state of the substrate temperature _{T 2,} maintained for 5 seconds such as up to the time _{t 2.} The process of maintaining the temperature T ₂ for a certain period of time is referred to as “first heat treatment”.

After the first heat treatment, the substrate temperature is lowered so that the substrate temperature becomes T ₃ at time t ₃ . Substrate temperature _{T 3} is, for example, 950 ° C.. The state of the substrate temperature _{T 3,} maintained for 10 seconds such as up to time _{t 4.} The process for a predetermined time maintained at a substrate temperature T _3, and referred to as "second heat treatment". After the second heat treatment, the substrate temperature is lowered to a normal temperature range. The temperature decrease rate when the substrate temperature is decreased from T ₂ to T ₃ is slower than the temperature decrease rate when the substrate temperature is decreased from T ₃ to the normal temperature range.

  By the first heat treatment and the second heat treatment, as shown in FIG. 1L, the natural oxide film 33 (FIG. 1K) formed on the surface of the active region 16B is removed.

  As shown in FIG. 1M, the surface of the active region is thermally oxidized. A relatively thin second gate insulating film 35 is formed on the surface of the active region 16B where the first gate insulating film 30 is not formed. This thermal oxidation is performed by switching the introduced gas from hydrogen to oxygen using the apparatus shown in FIG. 3 in which the first and second heat treatments have been performed. The thickness of the second gate insulating film 35 is, for example, in the range of 1 to 2 nm. Note that. On the surface of the active regions 16A and 16C where the first gate insulating film 30 is formed, oxidation hardly proceeds.

After the second gate insulating film 35 is formed, the first gate insulating film 30 and the second gate insulating film 35 are nitrided in an N ₂ O or NO atmosphere.

  As shown in FIG. 1N, a gate electrode 36 made of polycrystalline silicon is formed on the active regions 16A to 16C.

  As shown in FIG. 1O, NMOSFETs 50 and 51 are formed in the active regions 16A and 16B, respectively, and a PMOSFET 52 is formed in the active region 16C. Hereinafter, a procedure for forming these MOSFETs will be briefly described.

  The active region 16C where the PMOSFET is disposed is covered with a resist pattern, and ion implantation for forming extension portions of the NMOSFETs 50 and 51 is performed using the gate electrode 36 as a mask. As the impurity, phosphorus or arsenic is used. Note that ion implantation for forming extension portions of two types of NMOSFETs 50 and 51 having different gate insulating film thicknesses may be performed separately.

  The resist pattern covering the active region 16C where the PMOSFET is to be formed is removed by ashing and wet processing. The active regions 16A and 16B where the NMOSFET is to be formed are covered with a new resist pattern, and ion implantation for forming the extension portion of the PMOSFET 52 is performed using the gate electrode 36 as a mask. For example, boron is used as the impurity. When two types of PMOSFETs having different thicknesses of the gate insulating film are formed, ion implantation for forming the extension portion may be performed separately for each thickness of the gate insulating film.

  The resist pattern covering the active regions 16A and 16B where the NMOSFET is to be formed is removed by ashing and wet processing. Next, rapid thermal annealing (RTA) is performed under conditions of a temperature of 900 ° C. to 1050 ° C. and a time of 60 seconds or less, thereby activating the impurities implanted in the extension portion.

  Sidewall spacers 40 are formed on the side surfaces of the gate electrode 36. Thereafter, impurity implantation for forming the source and drain is performed separately for the NMOSFET and the PMONFET. Note that ion implantation for forming a source and a drain may be separately performed for each of two types of NMOSFETs having different gate insulating film thicknesses. Similarly, ion implantation for forming a source and a drain may be separately performed for each of two types of PMOSFETs having different gate insulating film thicknesses. Impurities implanted into the source and drain are activated by performing rapid thermal annealing (RTA) under conditions of a temperature of 900 ° C. to 1050 ° C. and a time of 60 seconds or less.

  A refractory metal silicide film 41 such as CoSi is formed on the surface of the source and drain and the upper surface of the gate electrode. The refractory metal silicide film 41 is formed, for example, by depositing a CoSi film on the entire surface of the substrate by sputtering and performing a heat treatment at 500 ° C. for 30 seconds. The excess CoSi film is removed by cleaning (RCA cleaning) using sulfuric acid, hydrochloric acid, hydrogen peroxide solution, aqueous ammonia, or the like.

  A multilayer wiring layer (not shown) is formed on the NMOSFETs 50 and 51 and the PMOSFET 52 by using a damascene method or a dual damascene method.

Next, the effect of removing the natural oxide film will be described separately for the first heat treatment at the temperature T ₂ shown in FIG. 4A and the _second heat treatment at the temperature T ₃ .

  FIG. 5 shows the measurement results of the thickness of the oxide film remaining after the silicon substrate on which the natural oxide film is formed is heat-treated in a hydrogen atmosphere. The horizontal axis represents the time of heat treatment in a hydrogen atmosphere in the unit “second”, and the vertical axis represents the thickness of the remaining film in the unit “nm”. The thickness of the remaining film was measured using an ellipsometer. The natural oxide film was formed by a chemical treatment, and the thickness of the natural oxide film before the heat treatment was 0.7 nm. The asterisks, triangles, diamonds, squares, and circles in the figure indicate the measurement results when the heat treatment temperatures are 950 ° C., 970 ° C., 990 ° C., 1000 ° C., and 1010 ° C., respectively. It is considered that the natural oxide film is almost completely removed from the sample having a remaining film thickness of 0.1 nm or less.

  When heat treatment is performed at 1000 ° C. for 10 seconds, the natural oxide film is almost completely removed. When the silicon surface is exposed to a high temperature of about 1000 ° C. with the natural oxide film removed, migration of silicon atoms occurs.

  FIG. 2B shows an example of a cross-sectional view of the vicinity of the boundary between the active region 16B and the element isolation insulating film 15 after heat treatment at 1000 ° C. for 10 seconds in a hydrogen atmosphere. When the divot 20 is generated, silicon atoms in the vicinity of the edge of the active region 16B migrate, thereby changing the cross-sectional shape of the surface of the active region 16B and making it round. This phenomenon is similar to a phenomenon in which silicon atoms migrate and COP disappears by heat-treating a silicon wafer in a hydrogen atmosphere. When the cross-sectional shape of the surface of the active region changes, the gate width and the like change, and desired transistor characteristics cannot be obtained.

In the example, the first heat treatment is performed at T ₂ = 1000 ° C. for 5 seconds. From the evaluation results shown in FIG. 5, the hydrogen oxide heat treatment at 1000 ° C. for 5 seconds does not completely remove the natural oxide film, and the natural oxide film with a thickness of about 0.18 nm remains on the surface of the active region. ing. In the state where the natural oxide film remains on the surface of the active region, migration of silicon atoms hardly occurs.

In the above embodiment, after the first heat treatment, the second heat treatment is performed at a temperature T ₃ = 950 ° C. for 10 seconds. From the evaluation results shown in FIG. 5, it is understood that the thickness of the natural oxide film is reduced by about 0.25 nm by the hydrogen heat treatment at 950 ° C. for 10 seconds. That is, the thickness of the natural oxide film is reduced by about 0.25 nm during the second heat treatment. Since the thickness of the natural oxide film remaining after the first heat treatment is about 0.18 nm, the natural oxide film is almost completely removed in the second heat treatment. Note that migration of silicon atoms is less likely to occur as the substrate temperature is lower. For example, when the substrate temperature is about 950 ° C., migration of silicon atoms hardly occurs. For this reason, the natural oxide film can be almost completely removed while maintaining the cross-sectional shape of the surface of the active region. In addition, for example, when the measurement result of the film thickness by the ellipsometer is less than 0.1 nm, it can be said that “almost completely removed”.

  In order to remove the natural oxide film while maintaining the cross-sectional shape of the surface of the active region, the first heat treatment is preferably terminated when the natural oxide film remains on the surface of the active region. Specifically, as shown in FIG. 5, it is preferable to end the first heat treatment in a state where the measurement result of the remaining film thickness by an ellipsometer is thicker than 0.1 nm. For example, when the first heat treatment is performed at 1010 ° C., the heat treatment time is preferably 4 seconds or less, and when it is performed at 990 ° C., the heat treatment time is preferably 8 seconds or less, at 970 ° C. When performing, it is preferable to make heat processing time into 17 seconds or less.

  When the first heat treatment temperature is increased, the treatment time can be shortened. If the temperature of the first heat treatment is higher than 1030 ° C., the natural oxide film is removed in an extremely short time, and therefore it is difficult to control the first heat treatment to be completed with the natural oxide film remaining. If the temperature of the first heat treatment is too low, the natural oxide film is hardly removed or the first heat treatment time must be extremely long. For this reason, it is preferable that the 1st heat processing temperature shall be in the range of 930 degreeC-1030 degreeC.

  The temperature of the second heat treatment is preferably as low as possible. Specifically, it is preferable to set the temperature at which silicon atoms on the silicon surface are difficult to migrate, more specifically, 980 ° C. or lower. If the temperature of the second heat treatment is too low, the natural oxide film is hardly removed. For this reason, it is preferable that the temperature of 2nd heat processing shall be 900 degreeC or more.

  The time of the 1st and 2nd heat processing should just be longer than 0 second. Moreover, it is preferable to set it as 30 seconds or less from a viewpoint of productivity. Note that the temperature and time of the first and second heat treatments are preferably selected appropriately depending on the thickness of the natural oxide film formed on the silicon surface.

  In the above embodiment, the deformation of the cross section of the surface of the active region can be suppressed in the vicinity of the boundary between the active region and the element isolation insulating film. For this reason, it can suppress that the characteristic of MOSFET formed in an active region shifts from a desired characteristic.

FIG. 4B shows a time calendar of the substrate temperature during the hydrogen treatment according to the modification of the above embodiment. The time calendar of the substrate temperature until the first heat treatment is completed is the same as in FIG. 4A. In the example shown in FIG. 4B, after the first heat treatment, a period of t ₅ from the time t _2, the are gently the substrate temperature is lowered. At time t ₅ when the substrate temperature reaches T _4, and a faster cooling rate.

In a period t _{2 to} t ₅ during which the substrate temperature is gradually lowered, a phenomenon equivalent to the second heat treatment at the temperature T ₃ shown in FIG. 4A occurs. That is, the remaining film of the natural oxide film is removed during this period. Thus, the second heat treatment does not necessarily maintain the substrate temperature constant. It is sufficient that the natural oxide film remaining after the first heat treatment is removed during the period in which the substrate temperature is gradually lowered. The temperature lowering rate during the second heat treatment may be set so that the natural oxide film is almost completely removed. As an example, it is preferable to make the temperature drop rate slower than −20 ° C./s. Moreover, if the temperature lowering rate is too slow, there is a concern that the substrate temperature is maintained at 1000 ° C. or higher even after the natural oxide film is completely removed. For this reason, it is preferable to make a temperature-fall rate faster than -5 degrees C / s.

  It should be noted that the temperature lowering rate is preferably set so that the substrate temperature is as low as possible, specifically, 980 ° C. or less when the natural oxide film is completely removed. Thereby, migration of silicon atoms can be prevented.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited thereto. It will be apparent to those skilled in the art that various modifications, improvements, combinations, and the like can be made.

10 silicon substrate 11 buffer film 12 mask film 14 element isolation trench 15 element isolation insulating films 16A, 16B, 16C active region 20 divot 21 protective film 25 p-type well 26 n-type well 30 first gate insulating film 31 resist pattern 31A opening 33 Natural oxide film 35 Second gate insulating film 36 Gate electrode 40 Side wall spacer 41 Refractory metal silicide films 50 and 51 NMOSFET
52 PMOSFET
102 Chamber 103 Heating lamp group 104 Wafer holder 106 Gas source 108 Valve 109 Gas inlet 110 Gas outlet 111 Exhaust pump

Claims (5)

Performing a first heat treatment on a silicon substrate in a reducing atmosphere containing hydrogen at a temperature in a range of 930 ° C. to 1030 ° C., for a time longer than 0 seconds and not longer than 30 seconds;
After being placed in a reducing atmosphere containing hydrogen after the first heat treatment, the temperature is lower than the substrate temperature at the time of the first heat treatment and the substrate temperature is in the range of 900 ° C. to 980 ° C. from 0 second. A step of performing the second heat treatment while maintaining a longer time than 30 seconds. Performing a first heat treatment on a silicon substrate in a reducing atmosphere containing hydrogen at a temperature in a range of 950 ° C. to 1050 ° C. for a time longer than 0 seconds and 60 seconds or less;
A step of lowering the temperature of the silicon substrate at a first temperature-decreasing rate slower than −20 ° C./s as a second heat treatment while being placed in a reducing atmosphere containing hydrogen after the first heat treatment;
And a step of lowering the temperature of the silicon substrate at a second temperature-decreasing rate that is faster than the first temperature-decreasing rate after the second heat treatment. A natural oxide film is formed on the surface of the silicon substrate before performing the first heat treatment,
2. The first heat treatment is performed under conditions of temperature and time at which the natural oxide film is not completely removed, and the natural oxide film remaining after the first heat treatment is removed in the second heat treatment. Or a method of manufacturing the semiconductor device according to 2; Before performing the first heat treatment,
A step of defining an active region by forming an element isolation insulating film by a shallow trench isolation method on a surface layer portion of the silicon substrate;
4. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a first gate insulating film by oxidizing a surface layer portion of the active region after the second heat treatment. 5. In the step of defining the active region, defining a plurality of active regions;
Before performing the first heat treatment,
Forming a second gate insulating film by oxidizing the surfaces of the plurality of active regions;
Removing the second gate insulating film formed on the surface of a part of the active region,
The method for manufacturing a semiconductor device according to claim 4, wherein the first heat treatment is performed after removing the second gate insulating film.

Images