JP2009264959A - Connection abnormality detection device and onboard electronic apparatus using this device - Google Patents

Connection abnormality detection device and onboard electronic apparatus using this device Download PDF

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JP2009264959A
JP2009264959A JP2008115589A JP2008115589A JP2009264959A JP 2009264959 A JP2009264959 A JP 2009264959A JP 2008115589 A JP2008115589 A JP 2008115589A JP 2008115589 A JP2008115589 A JP 2008115589A JP 2009264959 A JP2009264959 A JP 2009264959A
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resistance
connection
abnormality detection
detection device
voltage
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JP4825235B2 (en
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Kei Hayase
佳 早瀬
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide: a connection abnormality detection device that precisely measures minute changes in resistance in a solder joint regardless of variations or changes over time in electronic components and early detects a connection abnormality in the solder joint; and an onboard electronic apparatus using the device. <P>SOLUTION: Voltage measuring means 108 measures the voltage of a connection point V1 between a resistivity measuring solder joint 102b and a constant-voltage supply 105 and the voltages of points V2 and V3 at both ends of a reference resistor 106. Resistance calculating means 109 calculates the resistance Rr of the resistivity measuring solder joint 102b with use of the measured voltages Vout1, Vout2 and Vout3 of the three points V1, V2 and V3. Abnormality determination means 110 determines a connection abnormality in accordance with a change in resistance ΔRr of the resistivity measuring solder joint 102b. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

この発明は、車載用電子機器などに用いる回路基板に実装された半導体パッケージの半田接続部の接続異常を検知する接続異常検知装置およびその装置を用いた車載用電子機器に関するものである。   The present invention relates to a connection abnormality detection device for detecting a connection abnormality in a solder connection portion of a semiconductor package mounted on a circuit board used in a vehicle-mounted electronic device or the like, and a vehicle-mounted electronic device using the device.

近年、電子機器の主要コンポーネントとして、パッケージ基板が広く用いられている。このパッケージ基板は、例えば、BGA(Ball Grid Array:ボール・グリッド・アレイ)パッケージや、CSP(Chip Size Package:チップ・サイズ・パッケージ)などの小型電子部品に代表される半導体パッケージを実装したプリント基板である。前記BGAパッケージはパッケージの裏面に入出力用のパッドが並べられ、多ピンのICを表面実装するために広く用いられており、前記CSPはBGAパッケージと同じ基本構造にて、ICチップとほぼ同じ大きさを実現する超小型の半導体パッケージである。   In recent years, package substrates have been widely used as main components of electronic devices. The package substrate is, for example, a printed circuit board on which a semiconductor package represented by a small electronic component such as a BGA (Ball Grid Array) package or a CSP (Chip Size Package) is mounted. It is. The BGA package has input / output pads arranged on the back side of the package and is widely used for surface mounting of multi-pin ICs. The CSP has the same basic structure as the BGA package and is almost the same as an IC chip. It is an ultra-small semiconductor package that realizes its size.

半導体パッケージは、一般的にプラスチック樹脂あるいはアルミナなどのセラミックを主材料にして形成されており、エポキシ系樹脂材料などによって形成された回路基板に実装されて使用される。その際、半導体パッケージを構成するIC自身で発生した熱や環境温度の変動に起因して温度変動が繰り返し生じて、半導体パッケージと回路基板との間に線膨張率差に起因した機械的応力が加わり、半導体パッケージとこの半導体パッケージを実装する回路基板とを接続する半田に接続異常が発生する。この半田の接続異常を検知するために、機械的応力が一番大きく、理論的に半田接続寿命の短いとされるBGAパッケージのコーナー付近に、電気的接続確認用の半田接続部を設けた技術が開示されている(例えば、特許文献1参照)。   A semiconductor package is generally formed using a plastic resin or a ceramic such as alumina as a main material, and is used by being mounted on a circuit board formed of an epoxy resin material or the like. At that time, temperature fluctuations repeatedly occur due to fluctuations in heat and environmental temperature generated in the IC itself constituting the semiconductor package, and mechanical stress due to the difference in linear expansion coefficient is generated between the semiconductor package and the circuit board. In addition, a connection abnormality occurs in the solder connecting the semiconductor package and the circuit board on which the semiconductor package is mounted. In order to detect this solder connection abnormality, a technology for providing a solder connection portion for confirming electrical connection near the corner of a BGA package, which has the largest mechanical stress and theoretically has a short solder connection life Is disclosed (for example, see Patent Document 1).

また、半田接続部のクラックを検知する技術も開示されている。即ち、電気的接続確認用の半田接続部のLSI側を電気的にGNDに接続する。そして基板側を抵抗によりプルアップしてコンパレータのプラス側に接続し、コンパレータのマイナス側に基準電源を接続する。このように構成して電気的接続確認用の半田接続部にクラックが発生したときに生じるインピーダンスとプルアップ抵抗の分圧値が基準電源電圧に達すると、コンパレータの出力値が変化する。このコンパレータの出力値の変化を検知し、半田接続部の接続異常を検知する技術である(例えば、特許文献2参照)。   Also disclosed is a technique for detecting a crack in a solder connection portion. That is, the LSI side of the solder connection portion for electrical connection confirmation is electrically connected to GND. The substrate side is pulled up with a resistor and connected to the plus side of the comparator, and the reference power supply is connected to the minus side of the comparator. When the impedance generated when the crack is generated in the solder connection portion for confirming electrical connection and the divided value of the pull-up resistor reach the reference power supply voltage, the output value of the comparator changes. This is a technique for detecting a change in the output value of the comparator and detecting a connection abnormality in the solder connection portion (see, for example, Patent Document 2).

更に、電気的接続確認用の半田接続部の接続異常をラッチ回路とOR回路およびセレクタ回路で実現している技術の開示もある。即ち、BGAパッケージにおいて、電気的接続確認用の半田接続部が複数箇所あって、基板にはBGAパッケージの半田接続部から各々導出される配線パターンを有する。そして、半田の接続異常による電位の変化をラッチ回路により取り込み、OR回路で異常状態を検知し、セレクタ回路で複数個所の半田接続部の中から異常が生じた半田接続部を特定する技術である(例えば、特許文献3参照)。   Furthermore, there is also a disclosure of a technique that realizes connection abnormality of a solder connection part for electrical connection confirmation by a latch circuit, an OR circuit, and a selector circuit. That is, in the BGA package, there are a plurality of solder connection portions for electrical connection confirmation, and the substrate has a wiring pattern derived from the solder connection portion of the BGA package. Then, it is a technology that takes in a potential change due to an abnormal connection of solder by a latch circuit, detects an abnormal state with an OR circuit, and identifies a solder connection portion where an abnormality has occurred from a plurality of solder connection portions with a selector circuit. (For example, refer to Patent Document 3).

特開平10−93297号公報(段落0020−段落0029、図1)Japanese Patent Laid-Open No. 10-93297 (paragraph 0020-paragraph 0029, FIG. 1) 特開2001−228191号公報(段落0012−段落0014、図1)JP 2001-228191 A (paragraph 0012-paragraph 0014, FIG. 1) 特開2007−35889号公報(要約の欄、図3)JP 2007-35889 A (summary column, FIG. 3)

特許文献1あるいは特許文献2に開示された技術によれば、電気的接続確認用の半田接続部を半導体パッケージのコーナー付近に設けてクラックを確認することにより、信号用半田接続部に重大な接続不良が発生する前に異常を検知することができる。また、特許文献3に開示された技術によれば、どの半田接続部に異常が発生したか記録することで、故障診断時に有効となる。   According to the technique disclosed in Patent Document 1 or Patent Document 2, a critical connection is made to a signal solder connection portion by providing a solder connection portion for confirming electrical connection in the vicinity of a corner of a semiconductor package and checking a crack. Abnormalities can be detected before defects occur. Further, according to the technique disclosed in Patent Document 3, it is effective at the time of failure diagnosis by recording which solder connection portion has an abnormality.

ところで、近年の半導体パッケージの小型化や信号端子の増加によって、電気的接続確認用の半田接続部は信号用半田接続部に近接して配置せざるを得ない状況にあり、信号用半田接続部と電気的接続確認用の半田接続部を近づけるほど、電気的接続確認用の半田接続部で異常を検知した際には、信号用半田接続部にもクラックなどの異常が発生している可能性が高くなる。特に、車載部品など高い信頼性が求められる場合には、信号用半田接続部の接続異常を早期に且つ正確に検知する必要があり、そのためには電気的接続確認用の半田接続部の微小な抵抗値変化を精度よく測定する必要がある。   By the way, due to the recent miniaturization of semiconductor packages and the increase in signal terminals, the solder connection part for electrical connection confirmation has to be placed close to the signal solder connection part. The closer the solder connection part for electrical connection confirmation is, the more likely an abnormality such as a crack has occurred in the signal solder connection part when an abnormality is detected in the solder connection part for electrical connection confirmation Becomes higher. In particular, when high reliability such as in-vehicle parts is required, it is necessary to detect the connection abnormality of the solder connection part for signals early and accurately. It is necessary to measure the resistance change with high accuracy.

しかし、特許文献1には、具体的な抵抗値変化を検知する手法について開示されていない。また、特許文献2の開示技術では、基準電源電圧で閾値の調節は可能であるが、プルアップ抵抗のばらつきや温度変化、コンパレータのオフセットにより微小な抵抗変化は測定できない。したがって、接続異常初期の微小な抵抗変化は検知することができず、異常の早期発見は困難であるという課題がある。更に、特許文献3の開示技術では、ラッチ回路というデジタル回路を利用しており、閾値はラッチ回路の電源電圧とGNDの中心付近であるため、半田接続部のクラックが進行し、破断に近い状態の場合以外に検知することができない課題がある。   However, Patent Document 1 does not disclose a specific method for detecting a change in resistance value. In the disclosed technique of Patent Document 2, the threshold value can be adjusted with the reference power supply voltage, but a minute resistance change cannot be measured due to variations in pull-up resistance, temperature changes, and comparator offsets. Therefore, there is a problem that a minute resistance change at the beginning of connection abnormality cannot be detected, and early detection of abnormality is difficult. Furthermore, in the disclosed technique of Patent Document 3, a digital circuit called a latch circuit is used, and the threshold value is near the center of the power supply voltage and GND of the latch circuit. There is a problem that cannot be detected except in the case of.

また、特許文献1あるいは特許文献2に開示されているように、半導体パッケージのコーナー付近のみで異常検知すると、本来異常検知すべき箇所が中央に集中している場合など、明らかに無駄に寿命を削ることになり、このような構成では必要な寿命を確保するために過剰な信頼性を確保しなければならない課題もある。   Further, as disclosed in Patent Document 1 or Patent Document 2, if an abnormality is detected only near the corner of the semiconductor package, the life is obviously wasted if the locations where the abnormality should be detected are concentrated in the center. In such a configuration, there is a problem that excessive reliability must be ensured in order to ensure a necessary life.

この発明は、前記の課題を解消するためになされたもので、半田接続部の微小な抵抗値変化を電子部品のばらつきや経年変化および温度変動によらず精度良く測定し、半田接続部の接続異常を早期に検知する接続異常検知装置およびその装置を用いた車載用電子機器を得ることを目的とするものである。   The present invention has been made to solve the above-mentioned problems. A small change in resistance value of a solder connection portion is accurately measured regardless of variations in electronic components, aging, and temperature fluctuations. An object of the present invention is to obtain a connection abnormality detection device that detects an abnormality at an early stage, and an in-vehicle electronic device using the device.

この発明に係る接続異常検知装置は、回路基板に実装される半導体パッケージと前記回路基板との半田接続部の接続異常を検知する接続異常検知装置であって、前記半田接続部は、定電圧源に接続される被抵抗計測半田接続部と、前記半導体パッケージの内部配線により前記被抵抗計測半田接続部に接続される配線取り出し用半田接続部を含むと共に、前記配線取り出し用半田接続部に接続される抵抗値が既知の参照抵抗と、前記被抵抗計測半田接続部と前記定電圧源との接続点をV1、前記参照抵抗の一端をV2、前記参照抵抗の他端をV3としたとき、前記V1の電圧と前記第V2の電圧、及び前記V3の電圧をそれぞれ測定する電圧測定手段と、前記電圧測定手段により測定される前記V1の電圧と前記V2の電圧、及び前記V3の電圧を用いて前記被抵抗計測半田接続部の抵抗値を算出する抵抗値算出手段と、前記抵抗値算出手段により算出される前記被抵抗計測半田接続部の抵抗値の変化をもとに接続異常を判定する異常判定手段と、を具備するものである。   The connection abnormality detection device according to the present invention is a connection abnormality detection device that detects a connection abnormality of a solder connection portion between a semiconductor package mounted on a circuit board and the circuit board, and the solder connection portion includes a constant voltage source. Including a resistance measurement solder connection portion connected to the resistance measurement solder connection portion connected to the resistance measurement solder connection portion by an internal wiring of the semiconductor package, and connected to the wiring extraction solder connection portion. When a reference resistance having a known resistance value, a connection point between the resistance measurement solder connection portion and the constant voltage source is V1, one end of the reference resistance is V2, and the other end of the reference resistance is V3, A voltage measuring means for measuring the voltage of V1, the voltage of V2, and the voltage of V3; the voltage of V1, the voltage of V2, and the voltage of V3 measured by the voltage measuring means; A resistance value calculating means for calculating a resistance value of the resistance measuring solder connecting portion using a resistance, and a connection abnormality based on a change in the resistance value of the resistance measuring solder connecting portion calculated by the resistance value calculating means. Abnormality determining means for determining.

この発明に係る接続異常検知装置によれば、半田接続部の微小な抵抗値変化を電子部品のばらつきや経年変化および温度変動によらず、精度良く測定し、半田接続部の接続異常を早期に検知することができる。   According to the connection abnormality detecting device according to the present invention, a minute change in resistance value of the solder connection portion is accurately measured regardless of variations in electronic components, aging, and temperature fluctuations, and the connection abnormality of the solder connection portion is detected at an early stage. Can be detected.

以下、添付の図面を参照して、この発明に係る接続異常検知装置およびその装置を用いた車載用電子機器について好適な実施の形態を説明する。なお、これらの実施の形態によりこの発明が限定されるものではない。   DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of a connection abnormality detection device according to the invention and an in-vehicle electronic device using the device will be described with reference to the accompanying drawings. Note that the present invention is not limited to these embodiments.

実施の形態1.
まず、この発明に係る接続異常検知装置の原理構成について説明する。図1はこの発明の原理構成図である。図1において、半導体パッケージ101は半田接続部102a、102b、102cを介して回路基板103に実装されている。半田接続部102aは信号用半田接続部であり、半田接続部102bは接続異常を検知するための抵抗計測対象の被抵抗計測半田接続部である。また、半田接続部102cは配線取り出し用半田接続部であって、半導体パッケージ101のIC内部配線104により被抵抗計測半田接続部102bに接続されている。
Embodiment 1 FIG.
First, the principle configuration of the connection abnormality detection device according to the present invention will be described. FIG. 1 is a block diagram showing the principle of the present invention. In FIG. 1, a semiconductor package 101 is mounted on a circuit board 103 via solder connection portions 102a, 102b, and 102c. The solder connection part 102a is a signal solder connection part, and the solder connection part 102b is a resistance measurement solder connection part to be subjected to resistance measurement for detecting a connection abnormality. The solder connection portion 102 c is a wiring connection solder connection portion, and is connected to the resistance measurement solder connection portion 102 b by the IC internal wiring 104 of the semiconductor package 101.

被抵抗計測半田接続部102bの回路基板103と接する側は定電圧源105に接続されている。また、配線取り出し用半田接続部102cの回路基板103と接する側は高精度の参照抵抗106を介してアース電位などの接続異常検知装置に共通する共通電位107に接続されている。   The side in contact with the circuit board 103 of the resistance measurement solder connection portion 102 b is connected to the constant voltage source 105. Further, the side of the wiring connection solder connection portion 102c that is in contact with the circuit board 103 is connected to a common potential 107 common to a connection abnormality detection device such as a ground potential via a high-precision reference resistor 106.

電圧測定手段108は、被抵抗計測半田接続部102bと定電圧源105が接続される点V1、配線取り出し用半田接続部102cと参照抵抗106が接続される点V2、および参照抵抗106と共通電位107が接続される点V3の電圧を測定する。そして、抵抗算出手段109は、電圧測定手段108で測定された前記電圧測定点V1、V2、V3の測定電圧値Vout1、Vout2、Vout3を用いることにより、後述する方法で被抵抗計測半田接続部102bの抵抗値Rrを算出する。そして、被抵抗計測半田接続部102bの抵抗値Rrを元に異常判定手段110により、接続異常を判定する。なお、図1中の符号111は被抵抗計測半田接続部102bの抵抗を示している。   The voltage measuring means 108 includes a point V1 where the resistance measurement solder connection portion 102b and the constant voltage source 105 are connected, a point V2 where the wiring connection solder connection portion 102c and the reference resistor 106 are connected, and the reference resistor 106 and the common potential. The voltage at point V3 to which 107 is connected is measured. Then, the resistance calculating means 109 uses the measured voltage values Vout1, Vout2, and Vout3 of the voltage measuring points V1, V2, and V3 measured by the voltage measuring means 108, so that the resistance measurement solder connection portion 102b is used in a method described later. The resistance value Rr is calculated. Then, a connection abnormality is determined by the abnormality determination means 110 based on the resistance value Rr of the resistance measurement solder connection portion 102b. In addition, the code | symbol 111 in FIG. 1 has shown the resistance of the to-be-resisted measurement solder connection part 102b.

以上、この発明に係る接続異常検知装置の原理構成について説明したが、次に、具体的実施の形態について説明する。図2はこの発明の実施の形態1に係る接続異常検知装置を説明する構成図で、図1と共通の部分は同一符号を付している。なお、以降の実施の形態においては、半田接続部として半田ボールを用いた場合を例に挙げて説明する。   The principle configuration of the connection abnormality detection device according to the present invention has been described above. Next, specific embodiments will be described. FIG. 2 is a block diagram for explaining a connection abnormality detection device according to Embodiment 1 of the present invention, and parts common to FIG. In the following embodiments, a case where a solder ball is used as the solder connection portion will be described as an example.

被抵抗計測半田ボール102bは抵抗値測定対象であるため、半導体パッケージ101と回路基板103との熱膨張差による機械的応力が一番大きく、理論的には図2に示すように半田接続寿命が短いとされる最外周部に位置している。なお、被抵抗計測半田ボール102bは必ずしも半導体パッケージ101の最外周部にある必要はなく、信号用半田ボール102aよりも半導体パッケージ101の中心部から遠い位置にあればよい。被抵抗計測半田ボール102bと信号用半田ボール102aとを近接させることにより、信号用半田ボール102aの接続異常を正確に検知することができ、過剰な信頼性を確保する必要は無く、比較的安価な寿命設計により長寿命を確保することができる。   Since the resistance-measured solder ball 102b is a resistance value measurement target, the mechanical stress due to the thermal expansion difference between the semiconductor package 101 and the circuit board 103 is the largest, and theoretically the solder connection life is as shown in FIG. It is located at the outermost periphery, which is supposed to be short. The resistance measuring solder ball 102b is not necessarily located at the outermost peripheral portion of the semiconductor package 101, but may be located farther from the center of the semiconductor package 101 than the signal solder ball 102a. By making the resistance measurement solder ball 102b and the signal solder ball 102a close to each other, it is possible to accurately detect the connection abnormality of the signal solder ball 102a, and it is not necessary to ensure excessive reliability and is relatively inexpensive. Long service life can be ensured by simple life design.

配線取り出し用半田ボール102cは比較的接続信頼性の高い半導体パッケージ101の中心部に位置している。中心部に近づくほど半導体パッケージ101と回路基板103との熱膨張差による変位量が小さく、半田ボール102に加わる機械的応力が小さいからである。なお、配線取り出し用半田ボール102cは必ずしも半導体パッケージ101の中心部にある必要はなく、被抵抗計測半田ボール102bよりも半導体パッケージ101の中心部に近い位置にあればよい。この場合、半導体パッケージ101の中心部の半田ボールを信号用に割り当てられる。また、配線取り出し用半田ボール102cを複数とし、IC内部配線104および回路基板103の配線により接続することで、配線取り出し用半田ボール102cの接続信頼性が増し、被抵抗計測半田ボール102bの抵抗値を正確に測定して接続異常を検知することができる。   The solder ball 102c for wiring extraction is located at the center of the semiconductor package 101 with relatively high connection reliability. This is because the closer to the center, the smaller the displacement due to the difference in thermal expansion between the semiconductor package 101 and the circuit board 103 and the smaller the mechanical stress applied to the solder ball 102. Note that the solder ball for wiring extraction 102c is not necessarily located at the center of the semiconductor package 101, but may be located closer to the center of the semiconductor package 101 than the resistance measurement solder ball 102b. In this case, the solder balls at the center of the semiconductor package 101 are assigned for signals. Further, by connecting a plurality of wiring take-out solder balls 102c and connecting them by the IC internal wiring 104 and the circuit board 103, the connection reliability of the wiring take-out solder balls 102c is increased, and the resistance value of the resistance-measurement solder balls 102b is increased. It is possible to accurately detect the connection error.

電圧選択手段であるスイッチ201は、例えばアナログスイッチやリレーなど制御信号によって出力が制御されるものである。スイッチ201は、被抵抗計測半田ボール102bの抵抗111と定電圧源105が接続されている点V1の電圧Vout1、配線取り出し用半田接続部102cと参照抵抗106が接続される点V2の電圧Vout2、および参照抵抗106と共通電位107が接続される点V3の電圧Vout3の3つの電圧を選択して入力することが可能であり、その出力は増幅手段である増幅器202にアナログ信号として入力され増幅される。増幅器202で増幅されたアナログ信号は、AD変換手段であるAD変換器203によりデジタル信号に変換される。   The output of the switch 201 serving as a voltage selection unit is controlled by a control signal such as an analog switch or a relay. The switch 201 includes a voltage Vout1 at a point V1 where the resistance 111 of the resistance-measured solder ball 102b and the constant voltage source 105 are connected, a voltage Vout2 at a point V2 where the wiring connection solder connection portion 102c and the reference resistor 106 are connected, It is possible to select and input three voltages Vout3 at the point V3 where the reference resistor 106 and the common potential 107 are connected, and the output is input as an analog signal to the amplifier 202 which is an amplifying means and amplified. The The analog signal amplified by the amplifier 202 is converted into a digital signal by the AD converter 203 which is AD conversion means.

AD変換器203においてデジタル信号に変換された信号は、マイクロコントローラ204で処理される。マイクロコントローラ204は、スイッチ201の制御を行う制御部205と、電圧Vout1、電圧Vout2、電圧Vout3、および被抵抗計測半田ボール102bの抵抗値Rrを記録するメモリ206と、メモリ206に記録されたデータをもとに抵抗値Rrを算出する抵抗値算出部207と、抵抗値算出部207で算出された抵抗値Rrと予めメモリ206に記憶された初期抵抗値Rr0を用いて抵抗変化ΔRrを算出する抵抗変化算出部208と、抵抗変化算出部208で算出された抵抗変化ΔRrに基づいて接続異常判定の信号を出力する異常判定部209とにより構成される。   The signal converted into a digital signal by the AD converter 203 is processed by the microcontroller 204. The microcontroller 204 includes a control unit 205 that controls the switch 201, a memory 206 that records the voltage Vout1, the voltage Vout2, the voltage Vout3, and the resistance value Rr of the resistance measurement solder ball 102b, and data recorded in the memory 206. The resistance change Rr is calculated using the resistance value calculation unit 207 that calculates the resistance value Rr based on the resistance value, the resistance value Rr calculated by the resistance value calculation unit 207, and the initial resistance value Rr0 stored in the memory 206 in advance. A resistance change calculation unit 208 and an abnormality determination unit 209 that outputs a connection abnormality determination signal based on the resistance change ΔRr calculated by the resistance change calculation unit 208 are configured.

図3は図2の等価回路を表している。図3では半導体パッケージ101、半田ボール102、回路基板103、IC内部配線104を省き、被抵抗計測半田ボール102bの抵抗111のみを表示している。   FIG. 3 shows the equivalent circuit of FIG. In FIG. 3, the semiconductor package 101, the solder ball 102, the circuit board 103, and the IC internal wiring 104 are omitted, and only the resistance 111 of the resistance measurement solder ball 102b is displayed.

実施の形態1に係る接続異常検知装置は上記のように構成されており、次に、抵抗値測定対象である被抵抗計測半田ボール102bの抵抗値Rrを測定する方法について数式を用いて説明する。   The connection abnormality detection device according to the first embodiment is configured as described above. Next, a method for measuring the resistance value Rr of the resistance-measured solder ball 102b, which is a resistance value measurement target, will be described using mathematical expressions. .

まず、図4を参照して増幅器202について補足説明する。図4は増幅器202の一般的構成例を表している。増幅器202は、一般的にオペアンプ401と抵抗402、403によって構成される場合が多く、この場合、増幅率は抵抗402と抵抗403の抵抗値比で決まる。   First, the amplifier 202 will be described supplementarily with reference to FIG. FIG. 4 shows a general configuration example of the amplifier 202. In general, the amplifier 202 is often configured by an operational amplifier 401 and resistors 402 and 403. In this case, the amplification factor is determined by a resistance value ratio of the resistor 402 and the resistor 403.

次に、図3および図4を参照して電圧測定点V1、V2、V3とAD変換器203の出力、つまりマイクロコントローラ204のメモリ206に記憶される電圧Vout1、Vout2、Vout3について説明する。電圧測定点V1、V2、V3と共通電位107との間の抵抗値を変数rとすれば、電圧Voutは次の式1で表される。   Next, the voltage measurement points V1, V2, and V3 and the output of the AD converter 203, that is, the voltages Vout1, Vout2, and Vout3 stored in the memory 206 of the microcontroller 204 will be described with reference to FIGS. Assuming that the resistance value between the voltage measurement points V1, V2, and V3 and the common potential 107 is a variable r, the voltage Vout is expressed by the following equation (1).

Figure 2009264959
Figure 2009264959

ここで、前記式1における各記号は下記を表している。
E:定電圧源105の電圧、
ΔE:定電圧源105の電圧誤差、
Rr:被抵抗計測半田ボール102bの抵抗111の抵抗値、
Rref:参照抵抗106の抵抗値、
Voff_anp:オペアンプ401のオフセット電圧、
A:増幅器202の増幅率、
ΔA:増幅器202の増幅率誤差、
Voff_adc:AD変換器203のオフセット電圧
Here, each symbol in Formula 1 represents the following.
E: voltage of the constant voltage source 105,
ΔE: voltage error of the constant voltage source 105,
Rr: resistance value of the resistance 111 of the resistance measurement solder ball 102b,
Rref: resistance value of the reference resistor 106,
Voff_amp: the offset voltage of the operational amplifier 401,
A: amplification factor of the amplifier 202,
ΔA: gain error of amplifier 202,
Voff_adc: offset voltage of the AD converter 203

前記式1を構成する各記号の中で、定電圧源105の電圧E、参照抵抗106の抵抗値Rref、増幅器202の増幅率Aは、設計値で既知であるのに対して、定電圧源105の電圧誤差ΔE、オペアンプ401のオフセット電圧Voff_anp、増幅器202の増幅率誤差ΔA、およびAD変換器203のオフセット電圧Voff_adcは、製造ばらつきや周囲の温度変化あるいは経年変化により変動する未知数である。また、増幅器202の増幅率誤差ΔAは増幅器202を構成する抵抗402、403の抵抗誤差も影響する。   Among the symbols constituting Equation 1, the voltage E of the constant voltage source 105, the resistance value Rref of the reference resistor 106, and the amplification factor A of the amplifier 202 are known by design values, whereas the constant voltage source A voltage error ΔE 105, an offset voltage Voff_amp of the operational amplifier 401, an amplification factor error ΔA of the amplifier 202, and an offset voltage Voff_adc of the AD converter 203 are unknown numbers that fluctuate due to manufacturing variations, ambient temperature changes, or secular changes. The amplification factor error ΔA of the amplifier 202 is also affected by the resistance error of the resistors 402 and 403 constituting the amplifier 202.

前記式1を展開して測定抵抗である変数rを含む項と含まない項に整理すると次の式2となる。   When formula 1 is developed and arranged into terms that include variable r, which is a measured resistance, and terms that do not include it, the following formula 2 is obtained.

Figure 2009264959
Figure 2009264959

前記式2における第一項の測定抵抗である変数rの係数をa、第二項をbと置くと次の式3となる。
Vout=a・r+b (式3)
When the coefficient of the variable r, which is the measurement resistance of the first term in the equation 2, is a, and the second term is b, the following equation 3 is obtained.
Vout = a · r + b (Formula 3)

前記式3からマイクロコントローラ204のメモリ206に記録される電圧Voutは測定抵抗rの一次式で表されることがわかる。前記式3の定数項a、bを求めることにより、被抵抗計測半田ボール102bの抵抗値Rrを精度よく求めることができる。   It can be seen from Equation 3 that the voltage Vout recorded in the memory 206 of the microcontroller 204 is expressed by a linear equation of the measuring resistance r. By obtaining the constant terms a and b of Equation 3, the resistance value Rr of the resistance-measured solder ball 102b can be obtained with high accuracy.

次に、被抵抗計測半田ボール102bの抵抗値Rrの算出方法について説明する。電圧測定点V1、V2、V3で観測される電圧のAD変換器203からの出力値Vout1、Vout2、Vout3は次の式4、式5、式6のように表される。
Vout1=a・(Rr+Rref)+b (式4)
Vout2=a・Rref+b (式5)
Vout3=a・0+b=b (式6)
前記式5、式6からa、bの値は次の式7で表される。
b=Vout3
a=(Vout2−Vout3)/Rref (式7)
前記式4と式5および式7により被抵抗計測半田ボール102bの抵抗値Rrは次の式8で表される。
Next, a method of calculating the resistance value Rr of the resistance measurement solder ball 102b will be described. Output values Vout1, Vout2, and Vout3 of the voltage observed at the voltage measurement points V1, V2, and V3 from the AD converter 203 are expressed as the following Expression 4, Expression 5, and Expression 6.
Vout1 = a · (Rr + Rref) + b (Formula 4)
Vout2 = a · Rref + b (Formula 5)
Vout3 = a · 0 + b = b (Formula 6)
From Equations 5 and 6, the values of a and b are expressed by the following Equation 7.
b = Vout3
a = (Vout2-Vout3) / Rref (Formula 7)
The resistance value Rr of the resistance-measurement solder ball 102b is expressed by the following expression 8 according to the expressions 4, 5 and 7.

Figure 2009264959
Figure 2009264959

以上のように、前記式8より被抵抗計測半田ボール102bの抵抗値Rrを参照抵抗106の抵抗値Rrefの誤差範囲内で高精度に測定することができる。   As described above, the resistance value Rr of the resistance-measured solder ball 102b can be measured with high accuracy within the error range of the resistance value Rref of the reference resistor 106 from the equation (8).

次に、実施の形態1に係る接続異常検知装置の動作について、図3の等価回路を参照しながら図5のフローチャートにより説明する。   Next, the operation of the connection abnormality detection device according to the first embodiment will be described with reference to the flowchart of FIG. 5 with reference to the equivalent circuit of FIG.

まず、ステップS501で点V1の電圧値を計測するために、マイクロコントローラ204の制御部205の制御信号により、スイッチ201をAにセットする。ステップS502では、このときのAD変換器203の出力Vout1をメモリ206に記憶させる。   First, in order to measure the voltage value of the point V1 in step S501, the switch 201 is set to A by the control signal of the control unit 205 of the microcontroller 204. In step S502, the output Vout1 of the AD converter 203 at this time is stored in the memory 206.

次に、ステップS503で点V2の電圧値を計測するために、マイクロコントローラ204の制御部205の制御信号により、スイッチ201をBにセットする。ステップS504では、このときのAD変換器203の出力Vout2をメモリ206に記憶させる。   Next, in order to measure the voltage value of the point V <b> 2 in step S <b> 503, the switch 201 is set to B by the control signal of the control unit 205 of the microcontroller 204. In step S504, the output Vout2 of the AD converter 203 at this time is stored in the memory 206.

ステップS505では、点V3の電圧値を計測するために、マイクロコントローラ204の制御部205の制御信号により、スイッチ201をCにセットする。ステップS506では、このときのAD変換器203の出力Vout3をメモリ206に記憶させる。   In step S505, the switch 201 is set to C by the control signal of the control unit 205 of the microcontroller 204 in order to measure the voltage value at the point V3. In step S506, the output Vout3 of the AD converter 203 at this time is stored in the memory 206.

本実施の形態では、スイッチ201をA、B、Cの順にセットして、AD変換器203の出力をVout1、Vout2、Vout3の順にメモリ206に記憶させたが、この順番にスイッチ201を切り替える必要は無く、どの順番でスイッチ201を切り替えてもよい。   In this embodiment, the switch 201 is set in the order of A, B, and C, and the output of the AD converter 203 is stored in the memory 206 in the order of Vout1, Vout2, and Vout3. However, it is necessary to switch the switch 201 in this order. The switch 201 may be switched in any order.

ステップS507では、マイクロコントローラ204の抵抗値算出部207において、前記処理にてメモリ206に記憶させたVout1、Vout2、Vout3と既知の参照抵抗106の抵抗値Rrefから被抵抗計測半田ボール102bの抵抗値Rrを前記式8により算出する。   In step S507, the resistance value calculation unit 207 of the microcontroller 204 determines the resistance value of the resistance-measured solder ball 102b from the Vout1, Vout2, and Vout3 stored in the memory 206 and the known resistance value Rref of the reference resistor 106 in the above process. Rr is calculated according to Equation 8 above.

ステップS508では、マイクロコントローラ204の抵抗変化算出部208において、抵抗値算出部207で算出した被抵抗計測半田ボール102bの抵抗値Rrと初期抵抗値Rr0との差を抵抗変化ΔRrとして算出する。なお、初期抵抗値Rr0およびステップS511の処理については後述する。   In step S508, the resistance change calculation unit 208 of the microcontroller 204 calculates the difference between the resistance value Rr of the resistance-measured solder ball 102b calculated by the resistance value calculation unit 207 and the initial resistance value Rr0 as the resistance change ΔRr. The initial resistance value Rr0 and the processing in step S511 will be described later.

ステップS509では、マイクロコントローラ204の異常判定部209において、抵抗変化ΔRrをメモリ206に格納されている予め設定された抵抗変化用許容値と比較して、抵抗変化ΔRrが抵抗変化用許容値以下なら接続異常なしとし、ステップS501に戻る。抵抗変化ΔRrが抵抗変化用許容値以上なら接続異常有りと判断して、ステップS510で接続異常検知信号を出力する。   In step S509, the abnormality determination unit 209 of the microcontroller 204 compares the resistance change ΔRr with a preset resistance change allowable value stored in the memory 206, and if the resistance change ΔRr is equal to or smaller than the resistance change allowable value. There is no connection abnormality, and the process returns to step S501. If the resistance change ΔRr is equal to or greater than the resistance change allowable value, it is determined that there is a connection abnormality, and a connection abnormality detection signal is output in step S510.

ステップS511では、マイクロコントローラ204の抵抗値算出部207で算出した被抵抗計測半田ボール102bの抵抗値Rrを初期抵抗値Rr0としてメモリ206に記憶させるか選択する。ステップS508にて測定時の抵抗値Rrとそれより以前に測定されメモリ206に記憶された初期抵抗値Rr0との差を算出することで、被抵抗計測半田ボール102bおよび参照抵抗106に接続する配線抵抗を打ち消すことが可能であり、被抵抗計測半田ボール102bの抵抗値変化のみを記録し、それを元にステップS509で接続異常判定することができる。   In step S511, it is selected whether the resistance value Rr of the resistance measurement solder ball 102b calculated by the resistance value calculation unit 207 of the microcontroller 204 is stored in the memory 206 as the initial resistance value Rr0. In step S508, by calculating the difference between the resistance value Rr at the time of measurement and the initial resistance value Rr0 measured before and stored in the memory 206, the wiring connected to the resistance-measured solder ball 102b and the reference resistor 106 It is possible to cancel the resistance, and only the change in resistance value of the resistance-measured solder ball 102b is recorded, and based on this, the connection abnormality can be determined in step S509.

ステップS512での初期抵抗値Rr0のメモリ206への格納は、例えば半導体パッケージ101および回路基板103が熱サイクル応力を繰り返し受ける前、つまり半導体パッケージ101を実装した電子機器の初期起動時に行われる。   The storage of the initial resistance value Rr0 in the memory 206 in step S512 is performed, for example, before the semiconductor package 101 and the circuit board 103 are repeatedly subjected to thermal cycle stress, that is, at the initial startup of the electronic device on which the semiconductor package 101 is mounted.

ステップS513では、初期抵抗値Rr0の格納後に、初期抵抗値Rr0とメモリ206に格納されている予め設定された初期抵抗用許容値とを比較して、初期抵抗値Rr0が初期抵抗用許容値以上ならば、接続異常検知信号を出力する(ステップS510)。これにより、初期不良を発見できる。   In step S513, after the initial resistance value Rr0 is stored, the initial resistance value Rr0 is compared with the preset initial resistance allowable value stored in the memory 206, and the initial resistance value Rr0 is equal to or greater than the initial resistance allowable value. If so, a connection abnormality detection signal is output (step S510). Thereby, an initial failure can be found.

以上のように、実施の形態1に係る接続異常検知装置によれば、半田接続部の微小な抵抗値変化を電子部品のばらつきや経年変化および温度変動によらず、精度良く測定し、接続異常を早期に検知することができる。   As described above, according to the connection abnormality detection device according to the first embodiment, a minute resistance value change in the solder connection portion is accurately measured regardless of variations in electronic components, aging, and temperature fluctuations. Can be detected early.

実施の形態2.
次に、この発明の実施の形態2に係る接続異常検知装置について説明する。図6は実施の形態2に係る接続異常検知装置を説明する構成図で、半導体パッケージのコーナー部分に設けた複数の被抵抗計測半田ボール102bの抵抗値を測定できるように拡張した実施の形態を示す図である。
Embodiment 2. FIG.
Next, a connection abnormality detection apparatus according to Embodiment 2 of the present invention will be described. FIG. 6 is a configuration diagram for explaining the connection abnormality detection device according to the second embodiment, and is an expanded embodiment that can measure the resistance values of a plurality of resistance measurement solder balls 102b provided at the corners of the semiconductor package. FIG.

図6において、図1と共通の部分は同一の符号を用いて表し、説明を省略する。また、図の簡略化のため、信号用半田ボールの表示を省略する。図6において、抵抗値測定対象の被抵抗計測半田ボール102b1、102b2、102b3、102b4が半導体パッケージ101のコーナー部分に設けられている。被抵抗計測半田ボール102b1、102b2、102b3、102b4は、IC内部配線104により半導体パッケージ101の中心付近の1つの配線取り出し用半田ボール102cに接続されており、配線取り出し用半田ボール102cは回路基板配線601を介して参照抵抗106に接続されている。配線取り出し用半田ボール102cを共通にすることにより、一般的に信号線に使うことの多い半導体パッケージ101の中心付近の半田ボールを節約でき、通常、高価である高精度の参照抵抗106を1つで実現できる利点がある。   6, parts common to FIG. 1 are denoted by the same reference numerals, and description thereof is omitted. Further, for the sake of simplification, the display of the signal solder balls is omitted. In FIG. 6, resistance-measurement solder balls 102 b 1, 102 b 2, 102 b 3, and 102 b 4 to be measured for resistance values are provided at the corners of the semiconductor package 101. The resistance measurement solder balls 102b1, 102b2, 102b3, 102b4 are connected to one wiring extraction solder ball 102c near the center of the semiconductor package 101 by the IC internal wiring 104. The wiring extraction solder ball 102c is connected to the circuit board wiring. It is connected to the reference resistor 106 via 601. By using a common solder ball 102c for wiring extraction, it is possible to save a solder ball near the center of the semiconductor package 101 that is generally used for a signal line, and one high-precision reference resistor 106 that is usually expensive. There are advantages that can be realized.

被抵抗計測半田ボール102b1、102b2、102b3、102b4は、回路基板配線602を介して配線選択手段である配線選択スイッチ603bに接続されている。配線選択スイッチ603bは、被抵抗計測半田ボール102b1、102b2、102b3、102b4のうち、どの被抵抗計測半田ボールの抵抗値を測定するかを選択するものである。   The resistance measurement solder balls 102b1, 102b2, 102b3, and 102b4 are connected to a wiring selection switch 603b, which is a wiring selection unit, via a circuit board wiring 602. The wiring selection switch 603b is for selecting which resistance measurement solder ball of the resistance measurement solder balls 102b1, 102b2, 102b3, 102b4 is to be measured.

また、回路基板配線602は配線選択手段である電位選択スイッチ603aにも接続されている。電位選択スイッチ603aは被抵抗計測半田ボール102b1、102b2、102b3、102b4の電圧V11、V12、V13、V14と参照抵抗106の両端の電圧V2、V3のいずれの電圧を測定するかを切り替えるものである。電位選択スイッチ603a、配線選択スイッチ603bともにマイクロコントローラ204の制御部205の制御信号により制御される。本実施の形態では精度の必要無い定電圧源105の電圧誤差として、配線選択スイッチ603bの内部抵抗を含めることができるので、配線選択スイッチ603bの内部抵抗を考慮する必要がない。   The circuit board wiring 602 is also connected to a potential selection switch 603a which is a wiring selection means. The potential selection switch 603a switches the voltage V11, V12, V13, V14 of the resistance measuring solder balls 102b1, 102b2, 102b3, 102b4 and the voltage V2, V3 across the reference resistor 106 to be measured. . Both the potential selection switch 603a and the wiring selection switch 603b are controlled by a control signal from the control unit 205 of the microcontroller 204. In this embodiment, since the internal resistance of the wiring selection switch 603b can be included as a voltage error of the constant voltage source 105 that does not require accuracy, there is no need to consider the internal resistance of the wiring selection switch 603b.

次に、実施の形態2に係る接続異常検知装置の動作について、図6を参照しながら図7のフローチャートにより説明する。   Next, the operation of the connection abnormality detection device according to Embodiment 2 will be described with reference to FIG.

まず、ステップS701でどの被抵抗計測半田ボール102bを観測しているかを示すカウンタ変数iに初期値1を代入する。   First, in step S701, an initial value 1 is substituted into a counter variable i indicating which resistance measurement solder ball 102b is observed.

ステップS702では、マイクロコントローラ204の制御部205の制御信号により配線選択スイッチ603bをA1に、電位選択スイッチ603aをA1にそれぞれセットする。ステップS703では、その時のAD変換器203の出力値Vout1をメモリ206に記憶させる。   In step S702, the wiring selection switch 603b is set to A1 and the potential selection switch 603a is set to A1 according to the control signal of the control unit 205 of the microcontroller 204. In step S703, the output value Vout1 of the AD converter 203 at that time is stored in the memory 206.

ステップS704では、マイクロコントローラ204の制御部205の制御信号により、配線選択スイッチ603bをBに、電位選択スイッチ603aをBにそれぞれセットする。ステップS705では、その時のAD変換器203の出力値Vout2をメモリ206に記憶させる。   In step S704, the wiring selection switch 603b is set to B and the potential selection switch 603a is set to B according to the control signal of the control unit 205 of the microcontroller 204. In step S705, the output value Vout2 of the AD converter 203 at that time is stored in the memory 206.

ステップS706では、カウンタ変数iが2以上か判断し、カウンタ変数iが1のままであれば、ステップS707に進み、カウンタ変数iが2以上の場合は、Vout3が全ての被抵抗計測半田ボール102bにおいて共通なので、Vout3を記録するステップを省略する。つまり、後述のステップS707、ステップS708を省略する。   In step S706, it is determined whether the counter variable i is 2 or more. If the counter variable i remains 1, the process proceeds to step S707. If the counter variable i is 2 or more, Vout3 is all resistance-measurement solder balls 102b. , The step of recording Vout3 is omitted. That is, step S707 and step S708 described later are omitted.

ステップS707では、マイクロコントローラ204の制御部205の制御信号により、配線選択スイッチ603bをCにセットし、電位選択スイッチ603aをCにセットする。ステップS708では、その時のAD変換器203の出力値Vout3をメモリ206に記録する。なお、本実施の形態においてもVout1、Vout2、Vout3はどの順で記憶させてもよい。   In step S707, the wiring selection switch 603b is set to C and the potential selection switch 603a is set to C by the control signal of the control unit 205 of the microcontroller 204. In step S708, the output value Vout3 of the AD converter 203 at that time is recorded in the memory 206. In this embodiment, Vout1, Vout2, and Vout3 may be stored in any order.

ステップS709では、マイクロコントローラ204の抵抗値算出部207において、被抵抗計測半田ボール102b1の抵抗値Rr1を算出し、抵抗変化算出部208において、被抵抗計測半田ボール102b1の初期抵抗値Rr01との抵抗変化ΔRr1を算出する。   In step S709, the resistance value calculation unit 207 of the microcontroller 204 calculates the resistance value Rr1 of the resistance measurement solder ball 102b1, and the resistance change calculation unit 208 calculates the resistance with the initial resistance value Rr01 of the resistance measurement solder ball 102b1. A change ΔRr1 is calculated.

ステップS710では、抵抗変化ΔRr1、カウンタ変数iをメモリ206に記憶させる。なお、このときの抵抗算出処理や初期抵抗値格納処理は、図5のフローチャートで説明したのと同様である。   In step S710, the resistance change ΔRr1 and the counter variable i are stored in the memory 206. The resistance calculation process and the initial resistance value storage process at this time are the same as those described with reference to the flowchart of FIG.

ステップS711では、抵抗変化ΔRr1と予めメモリ206に記憶されている抵抗変化用許容値を比較する。抵抗変化ΔRr1が抵抗変化用許容値以内ならば、ステップS712で、次の被抵抗計測半田ボール102b2の抵抗値を測定するためにカウンタ変数iをインクリメントしてステップS713に進み、抵抗変化ΔRr1が抵抗変化用許容値以内でなければ、ステップS714に進む。   In step S711, the resistance change ΔRr1 is compared with the resistance change allowable value stored in the memory 206 in advance. If the resistance change ΔRr1 is within the resistance change allowable value, in step S712, the counter variable i is incremented to measure the resistance value of the next resistance-measured solder ball 102b2, and the process proceeds to step S713, where the resistance change ΔRr1 is the resistance change. If it is not within the allowable value for change, the process proceeds to step S714.

ステップS713では、以上の処理を被抵抗計測半田ボール102b2、102b3、102b4に対して、つまりカウンタ変数iが4になるまで繰り返す。全ての被抵抗計測半田ボール102b1、102b2、102b3、102b4の抵抗値を測定すると、カウンタ変数iが5になるので、iに1を代入して以上の処理を繰り返す。   In step S713, the above processing is repeated for the resistance measuring solder balls 102b2, 102b3, and 102b4, that is, until the counter variable i becomes 4. When the resistance values of all the resistance measurement solder balls 102b1, 102b2, 102b3, and 102b4 are measured, the counter variable i becomes 5. Therefore, 1 is substituted for i and the above processing is repeated.

ステップS714では、被抵抗計測半田ボール102b1、102b2、102b3、102b4のうち、何れかの被抵抗計測半田ボールにおいて抵抗変化ΔRrが予めメモリ206に記録されている抵抗変化用許容値以上であれば接続異常検知信号を出力する。   In step S714, if the resistance change ΔRr in any of the resistance measurement solder balls 102b1, 102b2, 102b3, 102b4 is equal to or greater than the resistance change allowable value recorded in advance in the memory 206, the connection is made. An abnormality detection signal is output.

前記においては、被抵抗計測半田ボール102b1、102b2、102b3、102b4が4箇所の場合を例に挙げて説明したが、配線選択スイッチ603bと電位選択スイッチ603aの数を増やすことにより、任意の数の被抵抗計測半田ボール102bの抵抗値を記録し、接続異常を検知することができる。また、被抵抗計測半田ボール102bの抵抗値を102b1から順に102b4まで計測したが、必ずしもこの順番である必要はない。   In the above description, the case where the resistance measurement solder balls 102b1, 102b2, 102b3, and 102b4 are four positions has been described as an example. However, by increasing the number of wiring selection switches 603b and potential selection switches 603a, an arbitrary number of It is possible to record the resistance value of the resistance-measured solder ball 102b and detect a connection abnormality. Further, although the resistance value of the resistance-measured solder ball 102b was measured from 102b1 to 102b4 in order, it is not always necessary to be in this order.

以上のように、実施の形態2に係る接続異常検知装置によれば、図7のステップS710において、カウンタ変数iをメモリ206に記録していることにより、どの被抵抗計測半田ボール102bを測定しているかを記録しているので、検収の際に故障箇所が特定できる利点かある。また、抵抗変化ΔRrを記録すれば、接続異常箇所は勿論、それ以外の被抵抗計測半田ボール102bの抵抗変化をプロファイルとして参照することができるので故障原因究明の際に役立つ利点もある。   As described above, according to the connection abnormality detection device of the second embodiment, which resistance measurement solder ball 102b is measured by recording the counter variable i in the memory 206 in step S710 of FIG. This is an advantage that the failure location can be specified at the time of acceptance inspection. Further, if the resistance change ΔRr is recorded, it is possible to refer to the resistance change of the other resistance-measured solder ball 102b as well as the connection abnormality portion as a profile, which has an advantage that is useful when investigating the cause of the failure.

なお、前記の説明においては、被抵抗計測半田ボール102b1、102b2、102b3、102b4と定電圧源105の間の電圧を、被抵抗計測半田ボール102b1、102b2、102b3、102b4と配線選択スイッチ603bとの間の電圧V11、V12、V13、V14から取り出す構成について説明したが、図8に示すように、配線選択スイッチ603bと定電圧源105の間の電圧V1から取り出してもよく、この構成とすることにより、電位選択スイッチ603aが少なくてすむ利点があり、配線選択スイッチ603bの内部抵抗の温度変化や経年変化が影響しない程度の精度でよい場合に有効である。   In the above description, the voltage between the resistance measurement solder balls 102b1, 102b2, 102b3, 102b4 and the constant voltage source 105 is the same as the resistance measurement solder balls 102b1, 102b2, 102b3, 102b4 and the wiring selection switch 603b. Although the configuration for extracting from the voltages V11, V12, V13, and V14 has been described, the voltage V1 between the wiring selection switch 603b and the constant voltage source 105 may be extracted as shown in FIG. Thus, there is an advantage that the potential selection switch 603a can be reduced, and this is effective when the accuracy is sufficient to prevent the temperature change or aging change of the internal resistance of the wiring selection switch 603b.

実施の形態3.
次に、この発明の実施の形態3に係る接続異常検知装置について説明する。図9は実施の形態3に係る接続異常検知装置を説明する構成図で、実施の形態1の図3と共通の部分は同一の符号を用いて表し、説明を省略する。
Embodiment 3 FIG.
Next, a connection abnormality detection apparatus according to Embodiment 3 of the present invention will be described. FIG. 9 is a configuration diagram illustrating the connection abnormality detection device according to the third embodiment, and the same parts as those in FIG. 3 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図9に示すように、実施の形態3に係る接続異常検知装置は、半田ボールの抵抗111と定電圧源105の間に電圧降下用の抵抗901が挿入されている。半田ボールの抵抗111と電圧降下用の抵抗901とが接続される点の電圧V1と、参照抵抗106の両端の電圧V2、V3とを後述する方法で測定する。本実施の形態では、電圧降下用の抵抗901を挿入することにより、電圧V1の電位が下がり、定電圧源105と増幅器202の電源とを共通にしても、増幅器202が飽和することがなくなる。つまり、定電圧源105の電圧発生のための電源回路が不要になる。この場合、前記式1は次の式9となる。   As shown in FIG. 9, in the connection abnormality detection device according to the third embodiment, a voltage drop resistor 901 is inserted between a solder ball resistor 111 and a constant voltage source 105. The voltage V1 at the point where the solder ball resistor 111 and the voltage drop resistor 901 are connected and the voltages V2 and V3 across the reference resistor 106 are measured by the method described later. In this embodiment, by inserting the voltage drop resistor 901, the potential of the voltage V1 is lowered, and the amplifier 202 is not saturated even if the constant voltage source 105 and the power source of the amplifier 202 are shared. That is, a power supply circuit for generating the voltage of the constant voltage source 105 is not necessary. In this case, the formula 1 becomes the following formula 9.

Figure 2009264959
Figure 2009264959

ここで、Rは電圧降下用の抵抗901の抵抗値、ΔRは電圧降下用の抵抗901の抵抗値誤差である。また、Rは既知の設計値、ΔRは素子のばらつきや温度変化および経年変化による抵抗値誤差で未知数である。前記式9を、測定抵抗rを含む項と含まない項に整理すると次の式10となる。   Here, R is a resistance value of the voltage drop resistor 901, and ΔR is a resistance value error of the voltage drop resistor 901. Further, R is a known design value, and ΔR is an unknown value due to a resistance value error due to element variation, temperature change, and secular change. If the above equation 9 is arranged into a term including the measurement resistance r and a term not including it, the following equation 10 is obtained.

Figure 2009264959
Figure 2009264959

前記式10より、電圧降下用の抵抗901が加わってもマイクロコントローラ204のメモリ206に記録される電圧Voutは測定抵抗rの一次式で表されることがわかる。従って、前記式8と同様の計算式で被抵抗計測半田ボール102bの抵抗値Rrを精度よく測定することができる。このとき、電圧降下用の抵抗901に精度は要求されない。   From Equation 10, it can be seen that the voltage Vout recorded in the memory 206 of the microcontroller 204 is expressed by a linear expression of the measurement resistor r even when the voltage drop resistor 901 is added. Therefore, the resistance value Rr of the resistance-measured solder ball 102b can be accurately measured by the same calculation formula as the formula 8. At this time, accuracy is not required for the voltage drop resistor 901.

この実施の形態3に係る接続異常検知装置の構成については、実施の形態2で説明した図6に係る接続異常検知装置に適用することもできる。この場合、例えば電圧降下用の抵抗901は配線選択スイッチ603bと定電圧源105との間に挿入すれば、追加する電圧降下用の抵抗901は1つでよい。また、配線選択スイッチ603bの内部抵抗は精度の必要無い電圧降下用の抵抗901の誤差となるので、計算結果に影響しない。   The configuration of the connection abnormality detection device according to the third embodiment can also be applied to the connection abnormality detection device according to FIG. 6 described in the second embodiment. In this case, for example, if the voltage drop resistor 901 is inserted between the wiring selection switch 603b and the constant voltage source 105, one additional voltage drop resistor 901 may be added. In addition, the internal resistance of the wiring selection switch 603b is an error of the voltage drop resistor 901 that does not require accuracy, and thus does not affect the calculation result.

また、実施の形態2で説明した図8に係る接続異常検知装置に適用することも可能である。この場合、例えば電位測定点V1と定電圧源105の間に電圧降下用の抵抗901を挿入すると前記と同様の効果が得られる。   Moreover, it is also possible to apply to the connection abnormality detection apparatus according to FIG. 8 described in the second embodiment. In this case, for example, if a voltage drop resistor 901 is inserted between the potential measurement point V1 and the constant voltage source 105, the same effect as described above can be obtained.

実施の形態4.
次に、この発明の実施の形態4に係る接続異常検知装置について説明する。図10は実施の形態4に係る接続異常検知装置を説明する構成図で、実施の形態1の図3と共通の部分は同一の符号を用いて表し、説明を省略する。
Embodiment 4 FIG.
Next, a connection abnormality detection apparatus according to Embodiment 4 of the present invention will be described. FIG. 10 is a block diagram for explaining a connection abnormality detection device according to the fourth embodiment. The same parts as those in FIG. 3 of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

図10に示すように、実施の形態4に係る接続異常検知装置は、参照抵抗106と共通電位107の間に電流導通手段である電流導通スイッチ1001が追加されている。電流導通スイッチ1001はマイクロコントローラ204の制御部205の制御信号により制御され、被抵抗計測用半田ボールの抵抗値Rrを測定するときにONする。本実施の形態にすることにより、被抵抗計測用半田ボールの抵抗値Rrの測定時にのみ電流が流れるので、消費電流を低減することができる。例えば、この発明を実装した電子機器の電源ON時のみ電流導通スイッチ1001をONしてイニシャルチェックし、接続異常判定後にOFFする構成とすれば、電流を消費するのはイニシャルチェックのときのみとなる。   As shown in FIG. 10, in the connection abnormality detection device according to the fourth embodiment, a current conduction switch 1001 that is a current conduction means is added between the reference resistor 106 and the common potential 107. The current conduction switch 1001 is controlled by a control signal from the control unit 205 of the microcontroller 204 and is turned on when measuring the resistance value Rr of the solder ball for resistance measurement. By adopting this embodiment, current flows only when measuring the resistance value Rr of the solder ball for resistance measurement, so that current consumption can be reduced. For example, if the current conduction switch 1001 is turned on and the initial check is performed only when the power supply of the electronic device in which the present invention is installed is turned on and turned off after the connection abnormality is determined, the current is consumed only at the time of the initial check. .

電流導通スイッチ1001は、例えばAD変換器203から出力された測定電圧Vout1、Vout2、Vout3がメモリ206に格納されたときにOFFすれば、それ以降の処理において、定電圧源105から電圧測定点V1、V2、V3を通り共通電位107に至る経路に電流が流れず、結果として被抵抗計測用半田ボールの接続異常を検知する際の消費電流を低減することができる。   If the current conduction switch 1001 is turned OFF when, for example, the measurement voltages Vout1, Vout2, and Vout3 output from the AD converter 203 are stored in the memory 206, the voltage measurement point V1 from the constant voltage source 105 in the subsequent processing. , V2 and V3, the current does not flow in the path to the common potential 107, and as a result, the current consumption when detecting the connection abnormality of the solder ball for resistance measurement can be reduced.

また、電流導通スイッチ1001は3点の電圧測定点V1、V2、V3の電圧を測定する場合にのみONしてもよい。このとき、AD変換器203から出力された測定電圧Vout1、Vout2、Vout3をADコンバータ203のレジスタからメモリ206に格納する際に、定電圧源105から電圧測定点V1、V2、V3を通り共通電位107に至る経路に電流が流れず、さらなる消費電流低減効果が得られる。   Further, the current conduction switch 1001 may be turned ON only when measuring the voltages at the three voltage measurement points V1, V2, and V3. At this time, when the measured voltages Vout1, Vout2, and Vout3 output from the AD converter 203 are stored in the memory 206 from the register of the AD converter 203, the common potential passes from the constant voltage source 105 through the voltage measuring points V1, V2, and V3. No current flows in the path to 107, and a further effect of reducing current consumption can be obtained.

なお、本実施の形態では、電流導通スイッチ1001を参照抵抗106と共通電位107の間に挿入したが、電流導通スイッチ1001を被抵抗計測半田ボール111と定電圧源105の間に挿入しても同様の効果が得られる。   In this embodiment, the current conduction switch 1001 is inserted between the reference resistor 106 and the common potential 107. However, the current conduction switch 1001 may be inserted between the resistance measurement solder ball 111 and the constant voltage source 105. Similar effects can be obtained.

また、本実施の形態は、実施の形態2あるいは実施の形態3と併用しても同様の効果を得ることができる。実施の形態2の場合、図6において定電圧源105と配線選択スイッチ603bとの間に電流導通スイッチ1001を挿入すれば、電流導通スイッチ1001は1つで済むし、ON抵抗を精度の必要ない定電圧源105の電圧誤差に含めることができる。   In addition, even when this embodiment is used in combination with the second embodiment or the third embodiment, the same effect can be obtained. In the case of the second embodiment, if the current conduction switch 1001 is inserted between the constant voltage source 105 and the wiring selection switch 603b in FIG. 6, only one current conduction switch 1001 is required and the ON resistance is not required to be accurate. It can be included in the voltage error of the constant voltage source 105.

実施の形態5.
次に、この発明の実施の形態5に係る接続異常検知装置について説明する。これまでの実施の形態では配線取り出し用半田ボール102cが半導体パッケージ101の中心領域にある実施の形態について説明した。実施の形態5に係る接続異常検知装置は、図11に示すように、配線取り出し用半田ボール102cが半導体パッケージ101のコーナー付近に設けられている。なお、図11は図1に相当する図である。
Embodiment 5 FIG.
Next, a connection abnormality detection apparatus according to Embodiment 5 of the present invention will be described. In the embodiments described so far, the embodiment in which the solder ball 102c for wiring extraction is in the central region of the semiconductor package 101 has been described. In the connection abnormality detection device according to the fifth embodiment, as shown in FIG. 11, solder balls for wiring removal 102 c are provided near the corners of the semiconductor package 101. FIG. 11 corresponds to FIG.

本実施の形態によれば、理論的に接続信頼性の高い中心付近の半田ボールを信号用半田ボール102aに割り当てることができる。この場合では、被抵抗計測半田ボール102b単体の抵抗値Rr1の測定は不可能だが、半導体パッケージ101のコーナー付近の半田接続不良を、被抵抗計測半田ボール102b単体の抵抗値Rr1と配線取り出し用半田ボール102cの抵抗値Rr2との直列抵抗の増加として検知することができる。   According to the present embodiment, it is possible to assign a solder ball near the center having theoretically high connection reliability to the signal solder ball 102a. In this case, it is impossible to measure the resistance value Rr1 of the resistance-measured solder ball 102b alone, but the solder connection failure near the corner of the semiconductor package 101 is caused by the resistance value Rr1 of the resistance-measurement solder ball 102b alone and the solder for taking out the wiring. This can be detected as an increase in series resistance with the resistance value Rr2 of the ball 102c.

図12は半導体パッケージ101のコーナー付近の複数の被抵抗計測半田ボール102bを使って、個々の被抵抗計測半田ボール102bの抵抗値を算出する構成図である。複数の被抵抗計測半田ボール102b1、102b2、102b3、102b4が半導体パッケージ101のコーナー付近に配置されている。被抵抗計測半田ボール102b1、102b2、102b3、102b4は、IC内部配線104によって接続されている。   FIG. 12 is a configuration diagram for calculating the resistance value of each resistance measurement solder ball 102b using a plurality of resistance measurement solder balls 102b near the corner of the semiconductor package 101. FIG. A plurality of resistance measurement solder balls 102 b 1, 102 b 2, 102 b 3, 102 b 4 are arranged near the corners of the semiconductor package 101. The resistance measurement solder balls 102 b 1, 102 b 2, 102 b 3 and 102 b 4 are connected by the IC internal wiring 104.

複数の被抵抗計測半田ボール102b1、102b2、102b3、102b4は各々が回路基板配線1201によって第1の配線選択手段である第1の配線選択スイッチ1202と第2の配線選択手段である第2の配線選択スイッチ1203とに接続されている。第1の配線選択スイッチ1202は定電圧源105に、第2の配線選択スイッチ1203は参照抵抗106にそれぞれ接続されている。第1の配線選択スイッチ1202と第2の配線選択スイッチ1203とを切り替えることによって、異なる2つの被抵抗計測半田ボール102bの合成抵抗値を算出する。   The plurality of resistance measurement solder balls 102b1, 102b2, 102b3, and 102b4 are each a first wiring selection switch 1202 as a first wiring selection means and a second wiring as a second wiring selection means by a circuit board wiring 1201. It is connected to the selection switch 1203. The first wiring selection switch 1202 is connected to the constant voltage source 105, and the second wiring selection switch 1203 is connected to the reference resistor 106. By switching the first wiring selection switch 1202 and the second wiring selection switch 1203, the combined resistance value of two different resistance-measured solder balls 102b is calculated.

マイクロコントローラ204には、測定対象の被抵抗計測半田ボール102bおよびその抵抗に係る合成抵抗値を選択する抵抗値選択部1204と、選択された合成抵抗値から各々の被抵抗計測半田ボール102b1、102b2、102b3、102b4の抵抗値を求める抵抗値分離部1205が追加されている。前記以外の構成は図3と同じであり、3つの電圧測定点V1、V2、V3からV1とV2間の抵抗値を高精度に算出する。   The microcontroller 204 includes a resistance measurement solder ball 102b to be measured and a resistance value selection unit 1204 that selects a combined resistance value related to the resistance, and each resistance measurement solder ball 102b1 and 102b2 from the selected combined resistance value. , 102b3 and 102b4, a resistance value separation unit 1205 for adding resistance values is added. The configuration other than the above is the same as in FIG. 3, and the resistance value between V1 and V2 is calculated with high accuracy from the three voltage measurement points V1, V2, and V3.

次に、測定抵抗値から各々の被抵抗計測半田ボール102b1、102b2、102b3、102b4の抵抗値を求める原理について説明する。   Next, the principle of obtaining the resistance values of the respective resistance-measured solder balls 102b1, 102b2, 102b3, 102b4 from the measured resistance values will be described.

まず、測定したい被抵抗計測半田ボール102bを含む3つの半田ボールを選択する(例えば、102b1、102b2、102b3を選択する)。被抵抗計測半田ボール102b1の抵抗値をRr1、被抵抗計測半田ボール102b2の抵抗値をRr2、被抵抗計測半田ボール102b3の抵抗値をRr3とすると、第1の配線選択スイッチ1202と第2の配線選択スイッチ1203とをそれぞれD2、E1にセットして測定した合成抵抗値Rr12は次の式11のようになる。
Rr12=Rr1+Rr2+ron (式11)
ただし、ronは第1の配線選択スイッチ1202の内部抵抗と第2の配線選択スイッチ1203との内部抵抗の誤差である。
First, three solder balls including the resistance measurement solder ball 102b to be measured are selected (for example, 102b1, 102b2, and 102b3 are selected). When the resistance value of the resistance measurement solder ball 102b1 is Rr1, the resistance value of the resistance measurement solder ball 102b2 is Rr2, and the resistance value of the resistance measurement solder ball 102b3 is Rr3, the first wiring selection switch 1202 and the second wiring The combined resistance value Rr12 measured with the selection switch 1203 set to D2 and E1, respectively, is given by the following equation 11.
Rr12 = Rr1 + Rr2 + ron (Formula 11)
Here, ron is an error between the internal resistance of the first wiring selection switch 1202 and the internal resistance of the second wiring selection switch 1203.

同様にして第1の配線選択スイッチ1202と第2の配線選択スイッチ1203をD3とE2、およびD1とE3にセットして測定した合成抵抗値それぞれRr23、Rr31は次の式12、式13のようになる。
Rr23=Rr2+Rr3+ron (式12)
Rr31=Rr3+Rr1+ron (式13)
前記式11、式12、式13を用いて被抵抗計測半田ボール102b1の抵抗値Rr1、Rr2、Rr3を求めると次の式14、式15、式16となる。
Rr1=(Rr12−Rr23+Rr31+ron)/2 (式14)
Rr2=(Rr23−Rr31+Rr12+ron)/2 (式15)
Rr3=(Rr31−Rr12+Rr23+ron)/2 (式16)
Similarly, the combined resistance values Rr23 and Rr31 measured by setting the first wiring selection switch 1202 and the second wiring selection switch 1203 to D3 and E2, and D1 and E3, respectively, are expressed by the following expressions 12 and 13. become.
Rr23 = Rr2 + Rr3 + ron (Formula 12)
Rr31 = Rr3 + Rr1 + ron (Formula 13)
When the resistance values Rr1, Rr2, and Rr3 of the resistance-measured solder ball 102b1 are obtained by using the equations 11, 12, and 13, the following equations 14, 15, and 16 are obtained.
Rr1 = (Rr12−Rr23 + Rr31 + ron) / 2 (Formula 14)
Rr2 = (Rr23−Rr31 + Rr12 + ron) / 2 (Formula 15)
Rr3 = (Rr31−Rr12 + Rr23 + ron) / 2 (Formula 16)

内部抵抗の誤差ronについては、例えば第1の配線選択スイッチ1202をD1、第2の配線選択スイッチ1203をE1にセットし、被抵抗計測半田ボール102bおよびIC内部配線104を通らないようにして抵抗値を測定することにより求めることができる。また、残りの被抵抗計測半田ボール102b4の抵抗値Rr4については以下のようにして求める。   Regarding the error ron of the internal resistance, for example, the first wiring selection switch 1202 is set to D1, the second wiring selection switch 1203 is set to E1, and the resistance measurement solder ball 102b and the IC internal wiring 104 are not passed through. It can be determined by measuring the value. Further, the resistance value Rr4 of the remaining resistance-measured solder balls 102b4 is obtained as follows.

即ち、第1の配線選択スイッチ1202をD1、D2、D3のどれか(例えばD3)にセットし、第2の配線選択スイッチ1203をE4にセットすると、得られる合成抵抗値R34は次の式17となる。
Rr34=Rr3+Rr4+ron (式17)
前記式17において、R34は測定値、Rr3とronともに算出済みであるので、被抵抗計測半田ボール102b4の抵抗値Rr4は次の式18で求まる。
Rr4=Rr34−Rr3−ron (式18)
That is, when the first wiring selection switch 1202 is set to any one of D1, D2, and D3 (for example, D3) and the second wiring selection switch 1203 is set to E4, the resultant combined resistance value R34 is expressed by the following equation (17). It becomes.
Rr34 = Rr3 + Rr4 + ron (Formula 17)
In the above equation 17, since R34 has been calculated for both the measured value, Rr3 and ron, the resistance value Rr4 of the resistance measurement solder ball 102b4 is obtained by the following equation 18.
Rr4 = Rr34-Rr3-ron (Formula 18)

次に、図13および図14のフローチャートを参照しながら実施の形態5に係る接続異常検知装置の動作について説明する。なお、本フローチャートでは4つの被抵抗計測半田ボール102b1、102b2、102b3、102b4について、被抵抗計測半田ボール102b1、102b2、102b3の抵抗値を算出してから被抵抗計測半田ボール102b4を算出する例を示す。また、その動作説明にあたり図12を参照する。   Next, the operation of the connection abnormality detection device according to the fifth embodiment will be described with reference to the flowcharts of FIGS. 13 and 14. In this flowchart, the resistance measurement solder balls 102b4 are calculated after the resistance values of the resistance measurement solder balls 102b1, 102b2, 102b3 are calculated for the four resistance measurement solder balls 102b1, 102b2, 102b3, 102b4. Show. Also, FIG. 12 will be referred to for explaining the operation.

まず、ステップS1301では、第1の配線選択スイッチ1202をD1、第2の配線選択スイッチ1203をE2にセットする。   First, in step S1301, the first wiring selection switch 1202 is set to D1, and the second wiring selection switch 1203 is set to E2.

ステップS1302では、合成抵抗値Rr12を算出し、マイクロコントローラ204のメモリ206に記憶させる。合成抵抗値Rr12の算出方法は図5のフローチャートのステップS501からステップS507と同様である。   In step S1302, the combined resistance value Rr12 is calculated and stored in the memory 206 of the microcontroller 204. The calculation method of the combined resistance value Rr12 is the same as that in steps S501 to S507 in the flowchart of FIG.

次に、ステップS1303では、第1の配線選択スイッチ1202をD2、第2の配線選択スイッチ1203をE3にセットする。   Next, in step S1303, the first wiring selection switch 1202 is set to D2, and the second wiring selection switch 1203 is set to E3.

ステップS1304では、合成抵抗値Rr23を算出し、マイクロコントローラ204のメモリ206に記憶させる。   In step S1304, the combined resistance value Rr23 is calculated and stored in the memory 206 of the microcontroller 204.

同様に、ステップS1305では、第1の配線選択スイッチ1202をD3、第2の配線選択スイッチ1203をE1にセットする。   Similarly, in step S1305, the first wiring selection switch 1202 is set to D3, and the second wiring selection switch 1203 is set to E1.

ステップS1306では、合成抵抗値Rr31を算出し、マイクロコントローラ204のメモリ206に記憶させる。   In step S1306, the combined resistance value Rr31 is calculated and stored in the memory 206 of the microcontroller 204.

ステップS1307では第1の配線選択スイッチ1202をD3、第2の配線選択スイッチ1203をE4にセットする。   In step S1307, the first wiring selection switch 1202 is set to D3, and the second wiring selection switch 1203 is set to E4.

ステップS1308では、合成抵抗値Rr34を算出し、マイクロコントローラ204のメモリ206に記憶させる。   In step S1308, the combined resistance value Rr34 is calculated and stored in the memory 206 of the microcontroller 204.

ステップS1309では、第1の配線選択スイッチ1202をD1、第2の配線選択スイッチ1203をE1にセットする。   In step S1309, the first wiring selection switch 1202 is set to D1, and the second wiring selection switch 1203 is set to E1.

ステップS1310では、内部抵抗の誤差ronを算出し、マイクロコントローラ204のメモリ206に記憶させる。   In step S1310, the error ron of the internal resistance is calculated and stored in the memory 206 of the microcontroller 204.

ステップS1311では、前記処理でメモリに格納した合成抵抗値Rr12、Rr23、Rr31を抵抗値選択部1204により選び、合成抵抗値Rr12、Rr23、Rr31、内部抵抗の誤差ronを用いて前記式14、式15、式16に従って各々の被抵抗計測半田ボール102b1、102b2、102b3の抵抗値Rr1、Rr2、Rr3を算出し、メモリ206に記憶させる。   In step S1311, the combined resistance values Rr12, Rr23, and Rr31 stored in the memory in the above processing are selected by the resistance value selection unit 1204, and the combined resistance values Rr12, Rr23, Rr31, and the internal resistance error ron are used to calculate the above-described Expressions 14 and 15. According to Equation 16, the resistance values Rr1, Rr2, and Rr3 of the respective resistance measurement solder balls 102b1, 102b2, and 102b3 are calculated and stored in the memory 206.

ステップS1312では、算出した合成抵抗値Rr34、抵抗値Rr3を抵抗値選択部1204により選び、合成抵抗値Rr34、抵抗値Rr3、内部抵抗の誤差ronを用いて前記式18に従って被抵抗計測半田ボール102b4の抵抗値Rr4を算出する。   In step S1312, the calculated combined resistance value Rr34 and resistance value Rr3 are selected by the resistance value selection unit 1204, and the combined resistance value Rr34, resistance value Rr3, and error ron of the internal resistance are used to measure the resistance-measured solder ball 102b4 according to the above equation 18. The resistance value Rr4 is calculated.

ステップS1313以降の処理は抵抗変化ΔRrを算出して、初期抵抗値Rr0と比較し、接続異常を判定するもので、ステップS508からステップS513の処理と同様であるため説明を省略する。   The processing after step S1313 is to calculate a resistance change ΔRr and compare it with the initial resistance value Rr0 to determine a connection abnormality. Since this is the same as the processing from step S508 to step S513, the description is omitted.

なお、前記において、どの被抵抗計測半田ボール102bをどの順で算出するかは予め決めておいてもよいし、抵抗値選択部1204によって動的に決めてもよい。   In the above description, which resistance measurement solder ball 102b is calculated in which order may be determined in advance, or may be dynamically determined by the resistance value selection unit 1204.

また、本実施の形態では被抵抗計測半田ボール102bが4つの例を示したが、第1の配線選択スイッチ1202および第2の配線選択スイッチ1203の数を増やすことで、5つ以上の被抵抗計測半田ボール102bの抵抗計測も可能である。また、複数の被抵抗計測半田ボール102bの抵抗値を求める順番は任意の順でよい。更に、抵抗値を計測する2つの被抵抗計測半田ボール102bを通りさえすれば第1の配線選択スイッチ1202および第2の配線選択スイッチ1203の切り替えも任意である(例えば、第1の配線選択スイッチ1202と第2の配線選択スイッチ1203がD1、E2のときと、D2、E1のときは同じ)。   In the present embodiment, four examples of the resistance measurement solder balls 102b are shown. However, by increasing the number of the first wiring selection switches 1202 and the second wiring selection switches 1203, five or more resistances are measured. The resistance of the measurement solder ball 102b can also be measured. Further, the order of obtaining the resistance values of the plurality of resistance-measured solder balls 102b may be any order. Furthermore, the first wiring selection switch 1202 and the second wiring selection switch 1203 can be switched as long as they pass through the two resistance-measured solder balls 102b for measuring the resistance value (for example, the first wiring selection switch). 1202 and the second wiring selection switch 1203 are the same when D1 and E2, and when D2 and E1).

また、本実施の形態では、複数の被抵抗計測半田ボール102bの抵抗値を高精度で各々求める上で、演算処理は増えるものの、理論的に接続信頼性の高い中心付近の半田ボールを配線取り出し用半田ボール102cに割り当てる必要がなく、信号用半田ボール102aに割り当てることができる。   Further, in this embodiment, although calculation processing is increased to obtain each of the resistance values of the plurality of resistance-measured solder balls 102b with high accuracy, a solder ball near the center having a high connection reliability is theoretically taken out. There is no need to assign to the solder ball for signal 102c, and it can be assigned to the solder ball for signal 102a.

以上、詳述したように、この発明の各実施の形態に係る接続異常検知装置によれば、半田接続異常検知のための回路を構成する電子部品のばらつきや温度変化および経年変化による影響によらずに半田接続部の抵抗値を高精度に測定することができる。また、その結果によって、半田接続部の接続異常を早期にかつ正確に検知することができる。   As described above in detail, according to the connection abnormality detection device according to each embodiment of the present invention, it is caused by the influence of variation of electronic parts constituting the circuit for detecting the solder connection abnormality, temperature change, and aging. Therefore, the resistance value of the solder connection portion can be measured with high accuracy. Moreover, the connection abnormality of a solder connection part can be detected early and correctly by the result.

特に、この発明の各実施の形態に係る接続異常検知装置を高い信頼性が要求される車載用電子機器に用いた場合には、厳しい使用環境下での接続異常を早期に発見することができ、信頼性を向上させることができる。   In particular, when the connection abnormality detection device according to each embodiment of the present invention is used in an in-vehicle electronic device that requires high reliability, it is possible to detect a connection abnormality in a severe usage environment at an early stage. , Reliability can be improved.

ところで、前記各実施の形態では半田ボールを有する半導体パッケージについての例を示したが、この発明はピン部材やガルウイング型リードあるいはJ型リードを用いた半導体パッケージにおいても同様の効果が期待できる。   By the way, although the example about the semiconductor package which has a solder ball was shown in each said embodiment, this invention can anticipate the same effect also in the semiconductor package using a pin member, a gull-wing-type lead, or a J-type lead.

また、前記説明の抵抗測定方法は半田接続部の抵抗値を測定する場合について述べたが、その他のものの抵抗測定にも利用できることはいうまでもない。   Further, although the resistance measurement method described above has been described for measuring the resistance value of the solder connection portion, it goes without saying that it can also be used for the resistance measurement of other things.

この発明に係る接続異常検知装置およびその装置を用いた車載用電子機器は、車載用電子機器における半田接続部の接続異常を検知するのに利用できる。   The connection abnormality detection device according to the present invention and a vehicle-mounted electronic device using the device can be used to detect a connection abnormality of a solder connection portion in the vehicle-mounted electronic device.

この発明の原理構成図である。It is a principle block diagram of this invention. 実施の形態1に係る接続異常検知装置を説明する構成図である。It is a block diagram explaining the connection abnormality detection apparatus which concerns on Embodiment 1. FIG. 図2の等価回路である。It is the equivalent circuit of FIG. 図3に示す増幅器の一般的構成例である。4 is a general configuration example of an amplifier shown in FIG. 3. 実施の形態1に係る接続異常検知装置の動作を説明するフローチャートである。4 is a flowchart for explaining the operation of the connection abnormality detection device according to the first embodiment. 実施の形態2に係る接続異常検知装置を説明する構成図である。It is a block diagram explaining the connection abnormality detection apparatus which concerns on Embodiment 2. FIG. 実施の形態2に係る接続異常検知装置の動作を説明するフローチャートである。10 is a flowchart for explaining the operation of the connection abnormality detection device according to the second embodiment. 実施の形態2に係る接続異常検知装置の他の例を説明する構成図である。It is a block diagram explaining the other example of the connection abnormality detection apparatus which concerns on Embodiment 2. FIG. 実施の形態3に係る接続異常検知装置を説明する構成図である。It is a block diagram explaining the connection abnormality detection apparatus which concerns on Embodiment 3. FIG. 実施の形態4に係る接続異常検知装置を説明する構成図である。It is a block diagram explaining the connection abnormality detection apparatus which concerns on Embodiment 4. 実施の形態5に係る接続異常検知装置の原理構成図である。It is a principle block diagram of the connection abnormality detection apparatus which concerns on Embodiment 5. 実施の形態5に係る接続異常検知装置を説明する構成図である。It is a block diagram explaining the connection abnormality detection apparatus which concerns on Embodiment 5. FIG. 実施の形態5に係る接続異常検知装置の動作を説明するフローチャートである。10 is a flowchart for explaining the operation of the connection abnormality detection device according to the fifth embodiment. 実施の形態5に係る接続異常検知装置の動作を説明するフローチャートである。10 is a flowchart for explaining the operation of the connection abnormality detection device according to the fifth embodiment.

符号の説明Explanation of symbols

101 半導体パッケージ
102a 信号用半田接続部
102b、102b1、102b2、102b3、102b4 被抵抗計測半田接続部
102c 配線取り出し用半田接続部
103 回路基板
104 IC内部配線
105 定電圧源
106 参照抵抗
107 共通電位
108 電圧測定手段
109 抵抗値算出手段
110 異常判定手段
111、1101 半田接続部抵抗
201、603a、603b、1202、1203 スイッチ
202 増幅器
203 AD変換器
204 マイクロコントローラ
205 制御部
206 メモリ
207 抵抗値算出部
208 抵抗変化算出部
209 異常判定部
401 オペアンプ
402、403 抵抗
601、602、1201 回路基板配線
603a 電位選択スイッチ
603b 配線選択スイッチ
901 電圧降下用抵抗
1201 回路基板配線
1202 第1の配線選択スイッチ
1203 第2の配線選択スイッチ
1204 抵抗値選択部
1205 抵抗値分離部
101 Semiconductor Package 102a Signal Solder Connection 102b, 102b1, 102b2, 102b3, 102b4 Resistance Measurement Solder Connection 102c Wiring Extraction Solder Connection 103 Circuit Board 104 IC Internal Wiring 105 Constant Voltage Source 106 Reference Resistance 107 Common Potential 108 Voltage Measurement unit 109 Resistance value calculation unit 110 Abnormality determination unit 111, 1101 Solder connection unit resistance 201, 603a, 603b, 1202, 1203 Switch 202 Amplifier 203 AD converter 204 Microcontroller 205 Control unit 206 Memory 207 Resistance value calculation unit 208 Resistance change Calculation unit 209 Abnormality determination unit 401 Operational amplifier 402, 403 Resistor 601, 602, 1201 Circuit board wiring 603a Potential selection switch 603b Wiring selection switch 901 Voltage drop resistor 1201 Road board wiring 1202 first wire selection switch 1203 second wire selection switch 1204 resistance value selector 1205 resistance separation unit

Claims (45)

回路基板に実装される半導体パッケージと前記回路基板との半田接続部の接続異常を検知する接続異常検知装置であって、
前記半田接続部は、定電圧源に接続される被抵抗計測半田接続部と、前記半導体パッケージの内部配線により前記被抵抗計測半田接続部に接続される配線取り出し用半田接続部を含むと共に、
前記配線取り出し用半田接続部に接続される抵抗値が既知の参照抵抗と、
前記被抵抗計測半田接続部と前記定電圧源との接続点をV1、前記参照抵抗の一端をV2、前記参照抵抗の他端をV3としたとき、前記V1の電圧と前記第V2の電圧、及び前記V3の電圧をそれぞれ測定する電圧測定手段と、
前記電圧測定手段により測定される前記V1の電圧と前記V2の電圧、及び前記V3の電圧を用いて前記被抵抗計測半田接続部の抵抗値を算出する抵抗値算出手段と、
前記抵抗値算出手段により算出される前記被抵抗計測半田接続部の抵抗値の変化をもとに接続異常を判定する異常判定手段と、
を具備することを特徴とする接続異常検知装置。
A connection abnormality detection device for detecting a connection abnormality of a solder connection portion between a semiconductor package mounted on a circuit board and the circuit board,
The solder connection portion includes a resistance measurement solder connection portion connected to a constant voltage source, and a wiring connection solder connection portion connected to the resistance measurement solder connection portion by an internal wiring of the semiconductor package,
A reference resistance having a known resistance value connected to the solder connection portion for wiring extraction, and
When the connection point between the resistance measurement solder connection part and the constant voltage source is V1, one end of the reference resistor is V2, and the other end of the reference resistor is V3, the voltage of V1 and the voltage of the V2; And voltage measuring means for measuring the voltage of V3, respectively.
A resistance value calculating means for calculating a resistance value of the resistance-measured solder connection portion using the voltage of V1, the voltage of V2, and the voltage of V3 measured by the voltage measuring means;
An abnormality determination means for determining a connection abnormality based on a change in resistance value of the resistance measurement solder connection portion calculated by the resistance value calculation means;
A connection abnormality detection device comprising:
前記被抵抗計測半田接続部は、前記半導体パッケージのコーナー領域、もしくは前記半導体パッケージの信号用半田接続部より、前記半導体パッケージの中心から遠い位置に設けたことを特徴とする請求項1に記載の接続異常検知装置。   2. The resistance measurement solder connection portion is provided at a position farther from the center of the semiconductor package than a corner region of the semiconductor package or a signal solder connection portion of the semiconductor package. Connection abnormality detection device. 前記配線取り出し用半田接続部は、前記半導体パッケージの中心領域、もしくは前記被抵抗計測半田接続部よりも前記半導体パッケージの中心に近い位置に設けたことを特徴とする請求項1又は請求項2に記載の接続異常検知装置。   3. The wiring connection solder connection portion is provided in a central region of the semiconductor package or in a position closer to the center of the semiconductor package than the resistance measurement solder connection portion. The connection abnormality detection device described. 前記配線取り出し用半田接続部は、複数の半田接続部を接続することを特徴とする請求項1乃至請求項3の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to claim 1, wherein the wiring connection solder connection portion connects a plurality of solder connection portions. 前記電圧測定手段は、
前記V1の電圧と前記V2の電圧、及び前記V3の電圧を選択する電圧選択手段と、
前記電圧選択手段で選択された電圧を増幅する増幅手段と、
前記増幅手段で増幅された電圧をデジタル変換するAD変換手段と、
前記電圧選択手段による電圧の選択を制御する制御部と、
を具備することを特徴とする請求項1乃至請求項4の何れか1項に記載の接続異常検知装置。
The voltage measuring means includes
Voltage selection means for selecting the voltage of V1, the voltage of V2, and the voltage of V3;
Amplifying means for amplifying the voltage selected by the voltage selecting means;
AD conversion means for digitally converting the voltage amplified by the amplification means;
A control unit for controlling selection of a voltage by the voltage selection unit;
The connection abnormality detection device according to any one of claims 1 to 4, further comprising:
前記電圧選択手段は、制御信号により切り替えられるスイッチで構成されることを特徴とする請求項5に記載の接続異常検知装置。   The connection abnormality detection device according to claim 5, wherein the voltage selection unit includes a switch that is switched by a control signal. 前記制御信号は、前記制御部により制御されることを特徴とする請求項6に記載の接続異常検知装置。   The connection abnormality detection device according to claim 6, wherein the control signal is controlled by the control unit. 前記抵抗値算出手段は、
前記測定電圧を記憶するメモリと、
前記被抵抗計測半田接続部の抵抗値を算出する抵抗値算出部と、
を具備することを特徴とする請求項1乃至請求項7の何れか1項に記載の接続異常検知装置。
The resistance value calculating means includes
A memory for storing the measured voltage;
A resistance value calculation unit for calculating a resistance value of the resistance measurement solder connection unit;
The connection abnormality detection device according to any one of claims 1 to 7, further comprising:
前記抵抗値算出部は、前記V1の電圧をVout1、前記V2の電圧をVout2、及び前記V3の電圧をVout3、前記参照抵抗の抵抗値をRrefとした場合、前記被抵抗計測半田接続部の抵抗値Rrを、次により算出することを特徴とする請求項8に記載の接続異常検知装置。
Rr=Rref(Vout1−Vout2)/(Vout2−Vout3)
The resistance value calculation unit is configured such that when the voltage V1 is Vout1, the voltage V2 is Vout2, the voltage V3 is Vout3, and the resistance value of the reference resistance is Rref, the resistance of the resistance measurement solder connection unit The connection abnormality detection device according to claim 8, wherein the value Rr is calculated as follows.
Rr = Rref (Vout1-Vout2) / (Vout2-Vout3)
前記異常判定手段は、
前記被抵抗計測半田接続部の抵抗変化を算出する抵抗変化算出部と、
前記抵抗変化算出部により算出された抵抗変化に基づいて接続異常を判定する異常判定部と、
前記被抵抗計測半田接続部の初期抵抗値を記録するメモリと、
を具備することを特徴とする請求項1乃至請求項9の何れか1項に記載の接続異常検知装置。
The abnormality determining means includes
A resistance change calculation unit for calculating a resistance change of the resistance measurement solder connection part;
An abnormality determining unit for determining a connection abnormality based on the resistance change calculated by the resistance change calculating unit;
A memory for recording an initial resistance value of the resistance measurement solder connection portion;
The connection abnormality detection device according to any one of claims 1 to 9, further comprising:
前記抵抗変化算出部は、前記被抵抗計測半田接続部の抵抗値から初期抵抗値を引くことにより前記被抵抗計測半田接続部の抵抗変化を算出することを特徴とする請求項10に記載の接続異常検知装置。   The connection according to claim 10, wherein the resistance change calculation unit calculates a resistance change of the resistance measurement solder connection part by subtracting an initial resistance value from a resistance value of the resistance measurement solder connection part. Anomaly detection device. 前記初期抵抗値は、予め測定されてメモリに格納されている前記被抵抗計測半田接続部の抵抗値であることを特徴とする請求項11に記載の接続異常検知装置。   The connection abnormality detection device according to claim 11, wherein the initial resistance value is a resistance value of the resistance measurement solder connection portion that is measured in advance and stored in a memory. 前記初期抵抗値は、前記回路基板を具備する電子機器に初めて電源が投入された際に測定される前記被抵抗計測半田接続部の抵抗値であることを特徴とする請求項11に記載の接続異常検知装置。   The connection according to claim 11, wherein the initial resistance value is a resistance value of the resistance-measured solder connection portion measured when power is first applied to an electronic device including the circuit board. Anomaly detection device. 前記初期抵抗値と前記メモリに記録された初期抵抗用許容値とを比較し、前記初期抵抗値が前記初期抵抗用許容値を上回る場合、接続異常検知信号を出力することを特徴とする請求項13に記載の接続異常検知装置。   The initial resistance value is compared with an initial resistance allowable value recorded in the memory, and when the initial resistance value exceeds the initial resistance allowable value, a connection abnormality detection signal is output. The connection abnormality detection device according to 13. 前記異常判定部は、前記抵抗変化と前記メモリに記録された抵抗変化用許容値とを比較し、前記抵抗変化が前記抵抗変化用許容値を上回る場合、接続異常検知信号を出力することを特徴とする請求項10に記載の接続異常検知装置。   The abnormality determination unit compares the resistance change with a resistance change allowable value recorded in the memory, and outputs a connection abnormality detection signal when the resistance change exceeds the resistance change allowable value. The connection abnormality detection device according to claim 10. 前記被抵抗計測半田接続部を複数から構成し、
前記複数からなる被抵抗計測半田接続部のそれぞれの被抵抗計測半田接続部と前記定電圧源との接続を選択する配線選択手段と、
前記配線選択手段と前記それぞれの被抵抗計測半田接続部との接続点の電圧と、前記参照抵抗の両端におけるそれぞれの電圧とを選択する電圧選択手段と、
を具備することを特徴とする請求項1乃至請求項4の何れか1項に記載の接続異常検知装置。
The resistance measurement solder connection part is composed of a plurality,
Wiring selection means for selecting connection between each of the resistance measurement solder connection portions of the plurality of resistance measurement solder connection portions and the constant voltage source;
Voltage selection means for selecting a voltage at a connection point between the wiring selection means and each of the resistance measurement solder connection portions and a voltage at both ends of the reference resistance;
The connection abnormality detection device according to any one of claims 1 to 4, further comprising:
前記被抵抗計測半田接続部を複数から構成し、
前記複数からなる被抵抗計測半田接続部のそれぞれの被抵抗計測半田接続部と前記定電圧源との接続を選択する配線選択手段と、
前記配線選択手段と前記定電圧源との接続点の電圧と、前記参照抵抗の両端におけるそれぞれの電圧とを選択する電圧選択手段と、
を具備することを特徴とする請求項1乃至請求項4の何れか1項に記載の接続異常検知装置。
The resistance measurement solder connection part is composed of a plurality,
Wiring selection means for selecting connection between each of the resistance measurement solder connection portions of the plurality of resistance measurement solder connection portions and the constant voltage source;
Voltage selection means for selecting a voltage at a connection point between the wiring selection means and the constant voltage source, and respective voltages at both ends of the reference resistor;
The connection abnormality detection device according to any one of claims 1 to 4, further comprising:
前記配線選択手段は、制御信号により切り替えられるスイッチで構成されることを特徴とする請求項16又は請求項17に記載の接続異常検知装置。   The connection abnormality detection device according to claim 16 or 17, wherein the wiring selection means is configured by a switch that is switched by a control signal. 前記被抵抗計測半田接続部と前記定電圧源との間に電圧降下用抵抗を設けたことを特徴とする請求項1乃至請求項18の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to any one of claims 1 to 18, wherein a voltage drop resistor is provided between the resistance measurement solder connection portion and the constant voltage source. 前記配線選択手段と前記定電圧源との間に電圧降下用抵抗を設けたことを特徴とする請求項16乃至請求項18の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to any one of claims 16 to 18, wherein a voltage drop resistor is provided between the wiring selection unit and the constant voltage source. 前記参照抵抗と前記接続異常検知装置の共通電位との間に電流導通手段を設けたことを特徴とする請求項1乃至請求項20の何れか1項に記載の接続異常検知装置。   21. The connection abnormality detection device according to claim 1, further comprising a current conduction means provided between the reference resistance and a common potential of the connection abnormality detection device. 前記被抵抗計測半田接続部と前記定電圧源との間に電流導通手段を設けたことを特徴とする請求項1乃至請求項20の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to any one of claims 1 to 20, wherein a current conduction unit is provided between the resistance measurement solder connection part and the constant voltage source. 前記電流導通手段は、制御信号により切り替えられるスイッチで構成されることを特徴とする請求項21又は請求項22に記載の接続異常検知装置。   The connection abnormality detection device according to claim 21 or 22, wherein the current conduction means is configured by a switch that is switched by a control signal. 前記制御信号は、前記制御部により制御されることを特徴とする請求項23に記載の接続異常検知装置。   The connection abnormality detection device according to claim 23, wherein the control signal is controlled by the control unit. 前記制御部は、前記被抵抗計測半田接続部の抵抗測定時に前記スイッチがONするように前記制御信号を制御することを特徴とする請求項24に記載の接続異常検知装置。   25. The connection abnormality detection device according to claim 24, wherein the control unit controls the control signal so that the switch is turned on at the time of resistance measurement of the resistance measurement solder connection unit. 前記抵抗測定時は、前記電子機器の電源投入時であることを特徴とする請求項25に記載の接続異常検知装置。   26. The connection abnormality detection device according to claim 25, wherein the resistance measurement is a power-on time of the electronic device. 前記制御信号は、前記V1の電圧と前記V2の電圧、及び前記V3の電圧のいずれかの電圧を測定する際に前記スイッチがONするように制御されることを特徴とする請求項24に記載の接続異常検知装置。   The control signal is controlled so that the switch is turned on when any one of the voltage of V1, the voltage of V2, and the voltage of V3 is measured. Connection abnormality detection device. 前記制御信号は、前記V1の電圧と前記V2の電圧、及び前記V3の電圧のいずれかの電圧が前記メモリに記憶された時以降に、前記スイッチをOFFするように制御されることを特徴とする請求項24に記載の接続異常検知装置。   The control signal is controlled to turn off the switch after the voltage V1, the voltage V2, or the voltage V3 is stored in the memory. The connection abnormality detection device according to claim 24. 前記電流導通手段と前記定電圧源との間に電圧降下用抵抗を設けたことを特徴とする請求項22に記載の接続異常検知装置。   23. The connection abnormality detection device according to claim 22, wherein a voltage drop resistor is provided between the current conducting means and the constant voltage source. 前記配線取り出し用半田接続部は、前記半導体パッケージのコーナー領域にあることを特徴とする請求項1又が請求項2に記載の接続異常検知装置。   The connection abnormality detection device according to claim 1, wherein the wiring connection solder connection portion is in a corner region of the semiconductor package. 回路基板に実装される半導体パッケージと前記回路基板との半田接続部の接続異常を検知する接続異常検知装置であって、
前記半田接続部は、定電圧源に接続される少なくとも3個の複数の被抵抗計測半田接続部を含むと共に、
前記被抵抗計測半田接続部に接続される抵抗値が既知の参照抵抗と、
前記複数の被抵抗計測半田接続部のうち多くとも2つの半田接続部を通る電流経路を選択する電流経路選択手段と、
前記定電圧源と前記被抵抗計測半田接続部との接続点をV1、前記参照抵抗の一端をV2、前記参照抵抗の他端をV3としたとき、前記V1の電圧と前記第V2の電圧、及び前記V3の電圧をそれぞれ測定する電圧測定手段と、
前記電圧測定手段により測定される前記V1の電圧と前記V2の電圧、及び前記V3の電圧を用いて前記V1とV2間の合成抵抗値を算出する抵抗値算出手段と、
前記V1とV2間の合成抵抗値を用いて前記被抵抗計測半田接続部の抵抗値を算出する抵抗値分離手段と、
前記被抵抗計測半田接続部の抵抗値の変化をもとに接続異常を判定する異常判定手段と、を具備することを特徴とする接続異常検知装置。
A connection abnormality detection device for detecting a connection abnormality of a solder connection portion between a semiconductor package mounted on a circuit board and the circuit board,
The solder connection portion includes at least three resistance measurement solder connection portions connected to a constant voltage source,
A reference resistance with a known resistance value connected to the resistance measurement solder connection part, and
Current path selection means for selecting a current path that passes through at least two of the plurality of resistance-measured solder connection parts;
When the connection point between the constant voltage source and the resistance measurement solder connection part is V1, one end of the reference resistor is V2, and the other end of the reference resistor is V3, the voltage of V1 and the voltage of the V2; And voltage measuring means for measuring the voltage of V3, respectively.
A resistance value calculating means for calculating a combined resistance value between V1 and V2 using the voltage of V1 and the voltage of V2 measured by the voltage measuring means and the voltage of V3;
Resistance value separation means for calculating a resistance value of the resistance measurement solder connection using a combined resistance value between V1 and V2,
An abnormality determination means for determining an abnormality of connection based on a change in the resistance value of the resistance-measured solder connection part.
前記複数の被抵抗計測半田接続部は、前記半導体パッケージのIC内部配線によって、互いに接続されていることを特徴とする請求項31に記載の接続異常検知装置。   32. The connection abnormality detection device according to claim 31, wherein the plurality of resistance measurement solder connection portions are connected to each other by IC internal wiring of the semiconductor package. 前記電流経路選択手段は、
前記複数の被抵抗計測半田接続部と前記定電圧源との間に挿入された第1の配線選択手段と、
前記複数の被抵抗計測半田接続部と前記参照抵抗との間に挿入された第2の配線選択手段と、
を具備することを特徴とする請求項31に記載の接続異常検知装置。
The current path selection means includes
First wiring selection means inserted between the plurality of resistance measurement solder connection portions and the constant voltage source;
Second wiring selection means inserted between the plurality of resistance measurement solder connection portions and the reference resistance;
The connection abnormality detection device according to claim 31, comprising:
前記第1の配線選択手段と前記第2の配線選択手段は、制御信号により切り替えられるスイッチで構成されることを特徴とする請求項33に記載の接続異常検知装置。   34. The connection abnormality detection device according to claim 33, wherein the first wiring selection unit and the second wiring selection unit are configured by a switch that is switched by a control signal. 前記抵抗値分離手段は、
前記電流経路選択手段により選択され、前記抵抗値算出手段によって算出された複数の経路の合成抵抗値と、第1の配線選択手段と第2の配線選択手段との内部抵抗の誤差とを格納するメモリと、
前記複数の経路の合成抵抗値の中から1つ以上の合成抵抗値を選ぶ抵抗値選択部と、
前記複数の経路の合成抵抗値から前記複数の被抵抗計測半田接続部の各々の抵抗値を算出する抵抗値分離部と、
を具備することを特徴とする請求項31に記載の接続異常検知装置。
The resistance value separating means includes
A combined resistance value of a plurality of paths selected by the current path selection unit and calculated by the resistance value calculation unit, and an internal resistance error between the first wiring selection unit and the second wiring selection unit are stored. Memory,
A resistance value selector for selecting one or more combined resistance values from the combined resistance values of the plurality of paths;
A resistance value separation unit for calculating a resistance value of each of the plurality of resistance measurement solder connection parts from a combined resistance value of the plurality of paths;
The connection abnormality detection device according to claim 31, comprising:
前記抵抗選択部は、前記複数の被抵抗計測半田接続部の中から抵抗値が未知の3個の被抵抗計測半田接続部を選び、前期メモリから前記3個の被抵抗計測半田接続部により構成される異なる3通りの経路の合成抵抗値を選ぶことを特徴とする請求項35に記載の接続異常検知装置。   The resistance selection unit selects three resistance measurement solder connection portions with unknown resistance values from the plurality of resistance measurement solder connection portions, and is configured by the three resistance measurement solder connection portions from the previous memory. 36. The connection abnormality detection device according to claim 35, wherein a combined resistance value of three different paths is selected. 前記内部抵抗の誤差は,前記電流経路選択手段により選択された被抵抗計測半田接続部を通らない経路の合成抵抗値であることを特徴とする請求項35又は請求項36に記載の接続異常検知装置。   The connection abnormality detection according to claim 35 or 36, wherein the error of the internal resistance is a combined resistance value of a path that does not pass through the resistance measurement solder connection selected by the current path selection means. apparatus. 前記抵抗値分離部は、前記異なる3通りの経路の合成抵抗値をRr12、Rr23、Rr31、前記内部抵抗の誤差をronとした場合、前記抵抗値が未知の3個の被抵抗計測半田接続部の抵抗値をRr1、Rr2、Rr3を、次により算出することを特徴とする請求項35乃至請求項37の何れか1項に記載の接続異常検知装置。
Rr1=(Rr12−Rr23+Rr31+ron)/2
Rr2=(Rr23−Rr31+Rr12+ron)/2
Rr3=(Rr31−Rr12+Rr23+ron)/2
The resistance value separation unit has three resistance measurement solder connection portions with unknown resistance values when the combined resistance value of the three different paths is Rr12, Rr23, Rr31, and the error of the internal resistance is ron. The connection abnormality detection device according to any one of claims 35 to 37, wherein Rr1, Rr2, and Rr3 are calculated as follows:
Rr1 = (Rr12−Rr23 + Rr31 + ron) / 2
Rr2 = (Rr23−Rr31 + Rr12 + ron) / 2
Rr3 = (Rr31-Rr12 + Rr23 + ron) / 2
前記抵抗値選択部は、抵抗値が未知の被抵抗計測半田接続部1つを選び、前記メモリから前記抵抗値が未知の被抵抗計測半田接続部と、抵抗値が既知の被抵抗計測半田接続部を通る経路の合成抵抗値を選ぶことを特徴とする請求項35に記載の接続異常検知装置。   The resistance value selection unit selects one resistance measurement solder connection unit with an unknown resistance value, and a resistance measurement solder connection unit with an unknown resistance value from the memory and a resistance measurement solder connection with a known resistance value. 36. The connection abnormality detection device according to claim 35, wherein a combined resistance value of a route passing through the section is selected. 前記抵抗値分離部は、前記合成抵抗値をRr45、前記抵抗値が既知の被抵抗計測半田接続部の抵抗値をRr4、前記第1の配線選択手段と前記第2の配線選択手段との内部抵抗の誤差をronとした場合、前記抵抗値が未知の被抵抗計測半田接続部の抵抗値Rr5を次により算出することを特徴とする請求項39に記載の接続異常検知装置。
Rr5=Rr45−ron
The resistance value separation unit has Rr45 as the combined resistance value, Rr4 as the resistance value of the resistance-measurement solder connection unit whose resistance value is known, and the internal of the first wiring selection unit and the second wiring selection unit. 40. The connection abnormality detection device according to claim 39, wherein, when the resistance error is ron, the resistance value Rr5 of the resistance-measured solder connection portion whose resistance value is unknown is calculated as follows.
Rr5 = Rr45-ron
前記半田接続部は、半田ボールで構成されることを特徴とする請求項1乃至請求項40の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to any one of claims 1 to 40, wherein the solder connection portion is formed of a solder ball. 前記半導体パッケージは、ボール・グリッド・アレイであることを特徴とする請求項41に記載の接続異常検知装置。   42. The connection abnormality detection device according to claim 41, wherein the semiconductor package is a ball grid array. 前記半田接続部は、ピン部材で構成されることを特徴とする請求項1乃至請求項40の何れか1項に記載の接続異常検知方法。   41. The connection abnormality detection method according to any one of claims 1 to 40, wherein the solder connection portion includes a pin member. 前記半田接続部は、ガルウイング状リードあるいはJ型リードから構成されることを特徴とする請求項1乃至請求項40の何れか1項に記載の接続異常検知装置。   The connection abnormality detection device according to any one of claims 1 to 40, wherein the solder connection portion includes a gull wing-shaped lead or a J-type lead. 車両に搭載される車載用電子機器に、前記請求項1乃至請求項44の何れか1項に記載の接続異常検知装置を用いたことを特徴とする車載用電子機器。   45. A vehicle-mounted electronic device using the connection abnormality detection device according to any one of claims 1 to 44 for a vehicle-mounted electronic device mounted on a vehicle.
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