JP2009253313A - Plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a high-definition PDP is unable to perform image display normally due to a writing operation defect, which is caused by forcible discharge generation in an initialization period and discharge interference between adjacent cells. <P>SOLUTION: In the plasma display device, groups of agglomerated grains consisting of agglomerated crystal grains of metal oxides are arranged on the periphery of a protective layer 18, and image display is performed by driving the device by a drive system comprising, in the initialization period, the first half portion of the initialization period of applying voltage boosting gently from a first voltage to a second voltage to a second electrode and a second half portion of the initialization period of applying voltage dropping gently from a third voltage to a fourth voltage to the second electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display device used for image display such as a computer or a television.

  In recent years, plasma display panels (hereinafter referred to as PDP) used for image display of computers and televisions are not only large, thin, and lightweight, but also have high definition in order to realize higher image quality. The demand is growing.

  A conventional PDP generally has the configuration shown in FIG. In FIG. 1, the PDP is composed of a front panel PA1 and a back panel PA2.

  The front panel PA1 includes a scanning electrode 19a as a second electrode, a sustain electrode 19b as a first electrode, a black stripe (light-shielding layer) 7 and a scanning electrode 19a. A dielectric glass comprising a sustaining electrode 19b, a first dielectric glass layer 17a formed so as to cover the black stripe 7, and a second dielectric glass layer 17b formed on the first dielectric glass layer 17a. The layer 17 is composed of a laminate of a dielectric protective film layer 18 formed on the dielectric glass layer 17. Scan electrode 19a and sustain electrode 19b are composed of transparent electrode 19a1, transparent electrode 19b1, metal electrode 19a2, and metal electrode 19b2.

  The back panel PA <b> 2 surrounds the address electrodes 14, which are third electrodes arranged in a stripe pattern on the back glass substrate 12, the electrode protection layer 13 formed so as to cover the address electrodes 14, and the address electrodes 14. Thus, the barrier rib 15 is formed in a box shape on the electrode protective layer 13. A phosphor layer 16 is applied to the inner wall of the partition wall 15. Since the phosphor layer is usually a color display, phosphors of three colors of red, green and blue are arranged in order.

  The front panel PA1 and the rear panel PA2 are attached to each other, and a discharge gas is sealed in the discharge unit 20 separated by the partition walls 15. For example, a mixed gas composed of helium, neon, argon, krypton, xenon, or the like is normally sealed in the discharge unit 20 at a pressure of about 67 kPa.

  Next, a description will be given of a plasma display device including a PDP electrode arrangement and a driving circuit for driving the display of the PDP. FIG. 2 shows the electrode arrangement of the PDP. FIG. 3 is a block diagram showing the configuration of the driving circuit of the plasma display device. This plasma display device includes a panel 1, a scan electrode drive circuit 21, a sustain electrode drive circuit 22, an address electrode drive circuit 23, a timing generation circuit 24, an A / D (analog / digital) converter 25, and a scan line number conversion unit 26. , A subfield conversion unit 27, and an APL (Averaged Picture Level (average luminance level)) detection unit 28.

  In FIG. 3, the image signal VD is input to the A / D converter 25. The horizontal synchronization signal H and the vertical synchronization signal V are input to the timing generation circuit 24, the A / D converter 25, and the scanning line number conversion unit 26. The A / D converter 25 converts the image signal VD into digital image data, and outputs the image data to the scanning line number conversion unit 26 and the APL detection unit 28. The APL detection unit 28 detects the average luminance level of the image data. Based on the detected average luminance level, a drive waveform constituting one television field is controlled. The scanning line number conversion unit 26 converts the image data into image data corresponding to the number of pixels of the panel 1 and outputs the image data to the subfield conversion unit 27. The subfield will be described later. The image data divided into the subfields is output to the address electrode drive circuit 23, and the address electrode drive circuit 23 applies voltages corresponding to the address electrodes D1 to Dm to the address electrodes for each subfield.

  The timing generation circuit 24 generates a timing signal based on the horizontal synchronization signal H and the vertical synchronization signal V and outputs the timing signal to the scan electrode drive circuit 21 and the sustain electrode drive circuit 22. Scan electrode drive circuit 21 and sustain electrode drive circuit 22 apply drive voltages to scan electrode SCN1 through scan electrode SCNn and sustain electrode SUS1 through sustain electrode SUSn based on the timing signal.

  Next, the gradation expression method used in the PDP will be described. FIG. 4 shows a gradation expression method used in the PDP. When displaying a television image, the image in the NTSC system is composed of 60 frames per second. Originally, the PDP can express only two gradations of lighting or non-lighting, so that one frame period is divided into a plurality of subfield (hereinafter referred to as SF) periods to display red, green, and blue. A method is used in which lighting times of the respective colors are time-divided and intermediate colors are expressed by combinations thereof. The ratio of the number of sustain pulses applied during the discharge sustain period of each SF is, for example, “1”, “2”, “4”, “8”, “16”, “32”, “64”, “128” Are weighted in binary mode, and 256 gradations are expressed by a combination of SF8 bits.

  In this method, each SF is further divided into four periods in order to control gas discharge in the discharge unit 20. FIG. 5 shows voltage waveforms applied to scan electrode SCN, sustain electrode SUS, and address electrode D in order to drive the plasma display device in one SF. In addition, these four periods will be described with reference to FIGS.

  In the initialization period, a desired wall charge is accumulated in the address discharge by weak discharge prior to the address period 32 in which the address discharge for selecting the cell to be lit is performed. In the first SF in one television field, an all-cell initializing period 31 in which an all-cell initializing operation for generating an initializing discharge is provided for all cells that perform image display is provided. On the other hand, in the other SFs, there is provided a selective initialization period 34 in which the initializing operation for generating the initializing discharge only for the cells that have undergone the sustaining discharge in the previous SF is performed. In the address period 32, a cell to be lit by address discharge is selected. In the sustain period 33, a sustain operation is performed in which light emission is maintained only in the cells that have undergone the address discharge in the address period 32.

  In the initialization operation in the first half of the all-cell initializing period 31, all sustain electrodes SUS1 to sustain electrode SUSn and address electrode D1 to address electrode Dm are held at 0 V, and all scan electrodes SCN1 to scan electrode SCNn A ramp voltage that gradually rises is applied to a voltage Vh that is equal to or higher than a threshold voltage Vff at which discharge starts between sustain electrode SUS1 to sustain electrode SUSn and address electrode D1 to address electrode Dm that cross each other. Then, gas discharge is caused in the discharge unit 20. The discharge here is a weak discharge in which the ionization multiplication gradually progresses in time, and the electric charge generated by the weak discharge is generated inside and on the surface of the discharge portion 20 around the address electrode 14, the scan electrode 19a, and the sustain electrode 19b. It accumulates as wall charges on the wall surface surrounding the discharge part 20 so as to weaken the electric field. Negative charges are accumulated on the surface of the protective film 18 near the scanning electrode 19a, and positive charges are accumulated on the surface of the protective film 18 near the sustain electrode 19b and the phosphor layer 16 near the address electrode 14 as wall charges.

  Furthermore, in the initializing operation in the latter half of all-cell initializing period 31, all sustain electrodes SUS1 to SUSn are held at positive voltage Ve, and all scan electrodes SCN1 to SCNn are paired with them. A discharge voltage is applied by applying a ramp voltage that gradually decreases toward sustain voltage SUS1 through sustain electrode SUSn and address electrode D1 through address electrode Dm that face each other toward voltage Vbt that is equal to or lower than threshold voltage Vpf at which discharge starts. Cause gas discharge. The discharge here is also a weak discharge in which the ionization multiplication progresses gradually in time. Due to this weak discharge, the negative charge accumulated on the surface of the protective film 18 near the scan electrode 19a and the positive wall charge accumulated on the surface of the protective film 18 near the sustain electrode 19b are weakened.

  In the state where all the cells are initialized and all the electrodes are grounded, a desired potential difference (a wall potential and a wall potential) necessary for selecting a lighting cell by an address discharge between the scan electrode, the address electrode 14 and the sustain electrode 19b. Is caused by the accumulated wall charge. The initialization operation is an operation for forming a desired wall charge for controlling the address discharge by the discharge.

  In the address period 32, a voltage lower than that of the address electrode 14 and the sustain electrode 19b is applied to the scan electrode 19a, and only the address electrode 14 of the cell to be lighted has the same sign as the wall potential between the scan electrode 19a and the address electrode 14. An address discharge is caused by applying a voltage so that a voltage difference of. As a result, negative charges are accumulated on the phosphor surface and the surface of the protective layer near the sustain electrode 19b, and positive charges are accumulated on the surface of the protective layer near the scan electrode 19a as wall charges. When the address period is completed and all the electrodes are grounded, a desired wall potential necessary for causing a sustain discharge between the scan electrode 19a and the sustain electrode 19b is generated by the wall charges.

  In the sustain period 33, first, a voltage higher than that of the sustain electrode 19b is applied to the scan electrode 19a to cause discharge. Thereafter, light emission is intermittently maintained by applying a voltage so that the polarities of the scan electrode 19a and the sustain electrode 19b are alternately switched.

  In the subsequent selective initialization period 34, imperfect discharge is caused by applying a rectangular waveform erasing voltage having a narrow phase difference time width with respect to the scan electrode 19a to the sustain electrode 19b at the end of the sustain period 33 of the previous SF. The generated wall charges are partially extinguished to prepare for the next SF initialization operation. As described above, in the conventional PDP driving method, image display is performed by a series of sequences of an initialization period, an address period, and a sustain period. Note that the all-cell initialization period is not performed only in the first SF of one field, but can also be performed in another SF.

  In the PDP shown in FIG. 1, in the all-cell initialization period 31 for accumulating desired wall charges by weak discharge, ions and electrons (charged particles that are the source of ionization multiplication) that are initially present in the discharge unit 20 are stored. ) Is low, or when a phosphor or barrier that easily absorbs the charge of the charged particles surrounds the discharge portion 20, the number of charged particles that become the seed of discharge is absolutely reduced. Is likely to generate a strong discharge (hereinafter referred to as a strong discharge) that progresses rapidly in time.

  When a strong discharge occurs, a wall charge that is excessive than the desired wall charge (for example, a wall charge that substantially cancels the electric field of the discharge unit 20) accumulates, and an abnormal wall potential that is higher than the desired wall potential is generated.

  Due to the action of the abnormal wall potential, there has been a problem in that sustain light emission occurs despite the fact that it should not be lit during the sustain period, and image display cannot be performed normally (see, for example, Patent Document 1).

  In addition, when performing video display using a high-definition PDP, there are the following problems. For example, in a high-definition PDP, since the cell pitch (distance between the partition walls) is short, even if the cells are separated from each other by the partition walls, the influence of electric field interference with adjacent cells and the scattering of charged particles increase.

In the conventional PDP driving method shown in FIG. 5 (hereinafter referred to as Conventional Example 2), since the rectangular waveform voltage is applied in the selective initialization period 34, the erasing discharge becomes strong. Therefore, when driving a high-definition PDP in Conventional Example 2, the influence of discharge interference between adjacent cells in the initialization period becomes significant, and a desired wall potential cannot be accumulated in the write operation, and the write operation is normal. (For example, refer to Patent Document 2).
JP 2000-214823 A JP 2006-151295 A

  In the conventional PDP, the pixel pitch is reduced for higher definition, and the ratio of the surface area to the volume of the discharge unit 20 is increased, or the mixing ratio of discharge gas having a large atomic number such as xenon or krypton is set for higher brightness. When increased, the electron supply amount for performing a stable initialization operation is insufficient, a strong discharge is generated in the initialization period, and the abnormal wall charges accumulated by the strong discharge are not turned on in the sustain period. However, there has been a problem that the image is not normally displayed because the sustain light is emitted.

  In addition, in the conventional driving method, when driving a high-definition PDP, the influence of electric field interference between adjacent cells and scattering of charged particles during the selective initialization period becomes significant, and is maintained despite the lighting during the maintenance period. There was a problem that the image could not be displayed normally without light emission.

  The reason why the problem becomes conspicuous as the definition becomes higher will be described in detail below.

  With the increase in definition, the volume of the discharge unit 20 per cell decreases, the ratio of the surface area of the wall surface to the volume of the discharge unit 20 increases, and due to heat generation caused by reabsorption of charged particles on the wall surface and elastic collision Energy loss increases, and more power must be supplied from the outside. As a result, the number of charged particles in the discharge unit 20 before the all-cell initializing operation is decreased, and the driving voltage in each period is increased.

  When the voltage applied to the electrode rises, the electric field strength inside and on the surface of the discharge part 20 around the electrode becomes stronger, and the probability that ionization multiplication proceeds rapidly in time increases. As a result, it becomes more difficult to generate the weak discharge used in the conventional initialization operation.

  As described above, with the increase in definition, a strong discharge is likely to occur in the initialization period due to a decrease in charged particles in the discharge unit 20 and an increase in drive voltage. As a result, it becomes more difficult than before to properly select a lighted or non-lighted cell in the address period.

  Further, as the definition is increased, the size of each cell is reduced, so that the light shielding rate by the partition walls and the metal electrodes is increased, the luminance is lowered, and the image is darkened as a whole. Thus, as a method for ensuring the luminance necessary for high-quality display, a method of increasing the mixing ratio of xenon or krypton responsible for visible light emission or the total pressure of the discharge gas has attracted attention. For example, the total pressure is 180 Torr or more and 750 Torr or less, and the xenon partial pressure ratio is 10%, 15%, 20%, 30%, 50%, 80%, 90%, 95%, 98%, 100%, and the like.

  The reason why the above-mentioned problem becomes remarkable when the mixing ratio of xenon, krypton, etc. is large will be described in detail below.

  Elements with large atomic numbers, such as xenon and krypton, have a lower secondary electron emission coefficient than helium, neon, and argon, which have a higher electron energy in the outermost shell, because they have lower electron energy (first ionization energy). small. As a result, the absolute number of electrons supplied from the surface of the protective film to the discharge unit 20 decreases, and the threshold voltage necessary for starting discharge increases.

  When the voltage applied to the electrode rises, the electric field strength inside and on the surface of the discharge part 20 around the electrode becomes stronger, and the probability that ionization multiplication proceeds rapidly in time increases. As a result, it becomes more difficult to generate the weak discharge used during the initialization period.

  Even when the partial pressure ratio of xenon, krypton, or the like is increased in order to ensure the high luminance necessary for high-quality display, strong discharge tends to occur during the all-cell initialization period. When a strong discharge occurs, the intensity of light emitted by a single discharge is strong, so the contrast ratio is significantly reduced, and the image quality is significantly deteriorated when displaying an image with many low gradation representations. Further, due to the formation of an excessive wall potential, it becomes more difficult than before to select normally the lighted or non-lighted cells in the address period.

  The present invention solves the problem of the conventional PDP and the problem of the conventional driving method at the same time, and not only dramatically improves the flickering and roughness of the image, but also reduces the number of parts of the address electrode driving circuit and reduces the scanning pulse. An object of the present invention is to provide a plasma display device that can reduce the price of a scan IC by increasing the voltage and realize high definition, power saving, and low price.

  The present invention has at least one pair of a first electrode and a second electrode that are parallel to each other, a dielectric layer is formed around the first electrode and the second electrode, and a protective layer is formed on the surface of the dielectric layer And a first substrate having at least one third electrode, a second substrate having a dielectric layer formed on the periphery of the third electrode, and opposing the first substrate and the second substrate In the PDP in which the discharge gas is sealed between the two, a plurality of aggregated particle groups in which a plurality of crystal particles made of a metal oxide are aggregated are arranged in the periphery of the protective layer. Note that the dielectric layer is not limited to being in contact with the electrode, but may be disposed in the periphery of the electrode. The same effect can be obtained when the aggregated particle group is arranged on the surface or inside of the protective layer. Further, the cell structure of the PDP is not limited to the surface discharge type as shown in FIG. 1, and the same effect can be obtained in the counter discharge type PDP in which the counter electrode is formed.

  Further, in order to solve the second problem of the conventional driving method, the present invention includes one field composed of a plurality of SFs, and each SF has at least an initialization period and an address period among an initialization period, an address period, and a sustain period. The initializing period includes a first half of an initializing period in which a voltage that gradually increases from the first voltage to the second voltage is applied to the second electrode, and a slow voltage from the third voltage to the fourth voltage to the second electrode. An image is displayed by a driving method having a second half of the initializing period in which a voltage that falls in the direction is applied.

  The present invention is also a plasma display device, wherein the crystal particles have an average particle size in the range of 0.9 μm to 2 μm.

  The present invention is also a plasma display device, wherein the protective layer is made of MgO.

  Further, the present invention is a plasma display device having at least one field among fields related to image display, in which all initialization operations performed during the subfield initialization period are selective initialization operations. .

  Further, the present invention is a plasma display device, wherein the first half of the initialization period has at least two periods with different rising voltage slopes, and the slope of the later period is gentler than the preceding period. It is.

  The present invention also relates to a plasma display device, wherein the latter half of the initialization period has at least two periods with different downward voltage slopes, and the slope of the back period is gentler than that of the previous period. It is.

  In addition, the present invention is a plasma display device in which the voltage of the scan pulse applied to the second electrode is set to the same potential as the fourth voltage in the writing period.

  In addition, the present invention is a plasma display device having a period in which the voltage of the third electrode is positive in the first half of the initialization period. In addition, when the voltage of the third electrode rises to positive polarity before reaching the first half of initialization, or when it falls from positive polarity in the middle of the first half of initialization, a period of positive polarity appears multiple times Including.

  Further, the present invention is a plasma display device, wherein the rising voltage gradient in the first half of the initializing period is 20 V / μsec or less.

  Further, the present invention is a plasma display device, wherein the downward voltage gradient in the latter half of the initialization period is 20 V / μsec or less.

  Further, the present invention is a plasma display device, wherein a period of a scanning pulse applied to the second electrode is 0.5 μsec to 1.8 μsec in an address period.

  According to the plasma display device of the present invention, the density of charged particles and excited particles (hereinafter referred to as priming particles) present in the discharge part in the initial stage is increased, and the contrast ratio is significantly reduced in the initialization period preceding the writing period. There is an effect of suppressing the strong discharge.

  Further, the influence of electric field interference between adjacent cells and scattering of charged particles in the selective initialization period can be reduced, and there is an effect of suppressing image quality deterioration due to poor selection of lighting or non-lighting cells in the writing period.

  In addition, even when the number of scanning lines is increased due to high definition, it is possible to suppress a write failure due to a discharge delay and to perform a high-speed address operation, and it is possible to improve image quality by increasing the definition.

  In addition, after the initialization operation is completed, charge loss that occurs during the standby period until the write operation can be prevented, the scan voltage and write voltage applied during the write period can be reduced, and the number of parts of the scan IC and address electrode drive circuit can be reduced. Thus, a lower cost PDP can be provided.

  Also, increase the mixing ratio of gases with large atomic numbers such as xenon and krypton and the total pressure of the discharge gas from the effect of suppressing strong discharge in initialization operation, the effect of preventing charge loss, and the effect of suppressing discharge delay. Therefore, it is possible to provide a plasma display device with higher brightness, higher efficiency and lower power consumption.

  The structure and manufacturing method of the protective layer, which is a feature of the panel of the PDP device according to the present invention, will be described. In the PDP according to the present invention, as shown in FIG. 6, the protective layer 18 includes a base protective layer 18 a made of magnesium oxide (MgO) containing aluminum (Al) as an impurity on the dielectric layer 17. Then, agglomerated particle groups 18c in which a plurality of MgO crystal particles 18b as metal oxides are agglomerated are discretely dispersed on the base protective layer 18a, and a plurality of particles are adhered so as to be distributed almost uniformly over the entire surface. It is constituted by.

  Here, the aggregated particle group 18c will be described. Aggregated particle group 18c is in a state where crystal particles 18b having a predetermined primary particle size are aggregated or necked as shown in FIG. Each of the crystal particles 18b is not bonded as a solid with a strong bonding force but is bonded by static electricity or van der Waals force, and a part or all of the crystal particles 18b are crystallized by an external stimulus such as ultrasonic waves. They are bonded to the particles with a binding force that is discrete.

  The crystal particles 18b have a particle size of about 1 micrometer (μm), and the crystal particles 18b preferably have a polyhedral shape having seven or more faces such as a tetrahedron and a dodecahedron. The particle size and shape of the primary particles of the crystal particle 18b can be controlled by the manufacturing method.

  For example, when an MgO precursor such as magnesium carbonate or magnesium hydroxide is calcined and produced, the particle size can be controlled by adjusting the calcining temperature or calcining atmosphere. Generally, the firing temperature can be selected in the range of about 700 to 1500 degrees, but the primary particle size can be controlled to about 0.3 to 2 μm by setting the firing temperature to a relatively high 1000 degrees or more. Furthermore, by heating the MgO precursor to generate the crystal particles 18b, an aggregated particle group 18c in which a plurality of primary particles are bonded by a phenomenon called aggregation or necking can be created in the generation process.

  Next, a manufacturing process for forming the protective layer 18 in the PDP according to the present invention will be described. As shown in the flow of the manufacturing process in FIG. 8, a dielectric layer forming step A1 for forming the dielectric layer 17 having a laminated structure of the first dielectric layer 17a and the second dielectric layer 17b is performed.

  In the base protective layer deposition step A2, a base protective layer 18a made of MgO is formed on the second dielectric layer surface 17b by a vacuum deposition method using a MgO sintered body containing Al as an impurity as a raw material.

  A step of discretely attaching a plurality of aggregated particle groups 18c to the surface of the unfired base protective layer 18a formed in the base protective layer deposition step A2 is performed. An agglomerated particle paste is prepared by mixing crystal particles 18b having a predetermined particle size distribution in a solvent together with a resin component. In the agglomerated particle paste layer forming step A3, the agglomerated particle paste is applied onto the unfired base protective layer 18a by screen printing to form an agglomerated particle paste layer. In addition to the screen printing method, there are a spray method, a spin coat method, a die coat method, a slit coat method and the like as a method for forming the aggregated particle paste layer.

  After forming the aggregated particle paste layer, a drying step A4 for drying the aggregated particle paste layer is performed.

  Next, co-firing is performed in a firing step A5 in which the unfired base protective layer 18a formed in the base protective layer deposition step A2 and the aggregated particle paste layer subjected to the drying step A4 are heated and fired at a temperature of several hundred degrees. By performing the removal of the solvent and the resin component remaining in the aggregated particle paste layer, it is possible to form the protective layer 18 in which a plurality of aggregated particle groups 18c are adhered on the base protective layer 18a. According to this method, it is possible to adhere the plurality of aggregated particle groups 18c to the base protective layer 18a so as to be uniformly distributed over the entire surface. The plasma display panel is manufactured through the above steps.

  In addition to the above, there are a method in which crystal particles are suspended in a gas without using a solvent and the like, and a method in which the particles are settled by using gravity without spraying.

  Next, drive waveforms and drive circuits in the initialization period of the drive method in the PDP according to the present invention will be described. As shown in FIG. 9, the PDP drive waveform according to the present invention has an initialization period in which a slowly increasing voltage is applied to the scan electrode 19a from the first voltage Va1 to the second voltage Vb1 in the initialization period 34 of each SF. It is characterized in that it is provided in the initial period T1 and an initializing period which is an initial period T2 in which a slowly decreasing voltage is applied from the third voltage Vc1 to the fourth voltage Vd1.

  A sustain electrode drive circuit configuration for realizing the PDP drive waveform according to the present invention is shown in FIG. This sustain electrode drive circuit is characterized in that a power supply Vb for applying a slowly increasing voltage is prepared in the first half T1 of the initialization period, and the output of a positive voltage is controlled by a separation circuit. In addition, in the latter half of the initialization period T2, a power supply Vd for applying a slowly decreasing voltage is prepared, and the output of a negative voltage is controlled by a separation circuit.

  For the circuit A that controls the output of the sustain voltage Vsus, a separation circuit B that controls the output of the positive voltage Vb is connected to the output terminal of the circuit A, and the output of the negative voltage Vd is connected to the output terminal of the circuit B. This is a circuit configuration in which a separation circuit C for controlling is connected. Further, between the gate and drain of the high-side switch of the separation circuit B, a slope generating circuit RMP1 composed of a constant current circuit I1, a capacitor C1, a diode D1, a resistor R1, and a power supply voltage Vb is connected. Also connected between the gate and drain of the low-side switch is a ramp generating circuit RMP2 including a constant current circuit I2, a capacitor C2, a diode D2, a resistor R2, and a power supply voltage Vd. With this drive circuit configuration, it is possible to apply to the scan electrode 19a a voltage that gradually increases in the first half T1 of the initialization period and a voltage that gradually decreases in the second half T2 of the initialization period. Note that the circuit configuration shown in FIG. 10 is an example of outputting a ramp voltage, and is not limited to this.

  Next, an experiment conducted for confirming the effect in the plasma display apparatus according to the present invention will be described.

(Verification Experiment 1) Four samples of PDPs having different configurations of the protective layer 18 and the aggregated particle group 18c were manufactured.
Prototype 1: PDP with only a protective layer composed of MgO
Prototype 2: PDP with a protective layer made of MgO doped with impurities such as Al and Si
Prototype 3: PDP in which only the primary crystal composed of a metal oxide is dispersed on the surface of the base protective layer 18a made of MgO and adhered to the MgO base protective layer 18a
Prototype 4: Prototype related to the present invention, and agglomerated particle group obtained by aggregating crystal primary particles is adhered to the surface of the base protective layer 18a made of MgO so as to be distributed almost uniformly over the entire surface. PDP
It is. In prototype 3 and prototype 4, MgO single crystal particles are used as the metal oxide.

  With respect to prototype 4 according to the present invention, the aggregated particle group adhered to the surface of the base protective layer 18a was irradiated with an electron beam and the cathodoluminescence was measured, and the characteristics shown in FIG. 11 were shown.

  The PDP using four types of protective layers was measured for electron emission performance and charge retention performance. Here, the electron emission performance and the charge retention performance will be described.

  The electron emission performance is determined by the number of electrons (current density) emitted from the surface of the protective layer including the base protective layer 18a and the aggregated particle group per unit time per unit area. As a method of measuring the current density flowing from the surface of the protective layer to the discharge unit 20, the prototype is destroyed, a small sample of the front plate is placed in a vacuum chamber, and the electrons emitted into the space are captured by an external electric field to increase photoelectrons. A method of detecting by a double tube or the like is conceivable. However, it is difficult to measure the current density from the protective layer when the PDP is actually driven.

  Therefore, the statistical delay time Ts of discharge is used as a measurement amount correlated with the current density until discharge. The temporal discharge delay from when the voltage is applied until the discharge reaches its peak is interpreted as the sum of the discharge formation delay time Tf and the discharge statistical delay time Ts. The discharge delay time depends on the voltage to be applied and the electron number density in the gas before the start of discharge. The formation delay time Tf correlates with the applied voltage, and the statistical delay time Ts correlates with the electron number density in the gas before the start of discharge. The statistical delay time Ts at each time is measured as a function of time until the start of discharge. The reciprocal of the statistical delay time Ts is proportional to the current density of electrons from the protective layer surrounding the discharge gas. If the reciprocal of the statistical delay time Ts is integrated over time as a function of the time until the start of discharge, a relative comparison of the amount of electron emission from the protective layer per unit area can be performed. Here, the electron emission performance of the prototype was relatively compared by measuring the statistical delay time Ts.

  Next, the charge retention performance will be described. As an index of the charge retention performance, there is a voltage Vscn applied in the address period. A period of waiting for an address operation by applying a voltage Vscn having a polarity opposite to the wall potential to the scan electrode 19a so that a desired wall charge is not lost during the address operation after the initialization operation is completed. Reduce wall charge loss.

  When the accumulated wall charges are easily lost due to surface current on the surface of the protective film 18 or charge exchange with the discharge gas, the Vscn voltage tends to increase. The lower the Vscn voltage, the higher the charge retention performance. In the current product, an element having a withstand voltage of about 150 V is used as a semiconductor switching element such as a MOSFET for sequentially applying a scanning voltage to the panel. As the Vscn voltage, in consideration of damage due to heat generation of the switching element, It is desirable to suppress to Vscn 120V or less. Here, the minimum scan voltage Vscn required for the write operation was measured, and the charge retention performance of the prototypes was compared.

  FIG. 12 shows the results of examining the aforementioned electron emission performance and charge retention performance. The performance of the prototype was plotted with the electron emission performance on the horizontal axis and the charge retention performance on the vertical axis. Prototype 4 according to the present invention has characteristics of an electron emission performance of 6 or more and a charge retention performance of Vscn voltage of 120 V or less. In the prototype 2 and the prototype 3 with high electron emission performance, the Vscn voltage is 120 or more, and the charge retention performance is poor. On the other hand, in the prototype 1 having high charge retention performance, the electron emission performance is 2 or less, and the electron emission performance is poor.

  (Verification Experiment 2) Prototype 5 (with a different doping amount from Prototype 2) in which a protective layer made of MgO doped with impurities such as Al and Si was formed, and crystals on the surface of the protective layer made of MgO Prototype 6 (repeat product of prototype 4) in which the aggregated particle group obtained by aggregating the primary particles was adhered so as to be distributed almost uniformly over the entire surface was manufactured as a prototype.

  For these prototypes, the ease of occurrence of strong discharge in the all-cell initialization period was compared, and the effect of suppressing strong discharge in the all-cell initialization period by the prototype 6 according to the present invention was verified.

  In this experiment, a near-infrared photodiode (hereinafter referred to as APD) used as an optical signal receiver as a measuring instrument was used. The strength of discharge during the all-cell initialization period was observed by the output of the APD. The intensity of the discharge can be identified by the amount of generated near infrared rays emitted from the transition between the excited states of xenon. When the discharge is strong, the generation amount of near infrared rays increases.

  As an example, FIG. 13 shows a schematic diagram of an APD output waveform when a weak discharge occurs in the all-cell initialization period, and FIG. 14 shows a schematic diagram of an APD output waveform when a strong discharge occurs in the all-cell initialization period.

  In FIG. 13, in the first half T1 of the initialization period, a positive voltage is applied to the scan electrode 19a, and the potential difference including the wall potential inside or on the surface of the discharge unit 20 around the electrode is higher than the potential difference at the start of discharge. Here, the weak discharge which progresses slowly rather than rapid ionization multiplication with time occurs stably. In the second half of the initialization period T2 in which the applied voltage of the scan electrode 19a is switched from the positive voltage to the negative voltage, unnecessary wall charges are removed from the wall charges accumulated in the first half T1 of the initialization period, and the wall charges are adjusted. Due to the weak discharge in the first half T1 and the second half T2 of the initialization period, desired wall charges can be accumulated in the address discharge in the discharge portions 20 around the scan electrodes 19a and the address electrodes 14.

  In FIG. 14, in the first half T1 of the initialization period, a positive voltage is applied to the scan electrode 19a, and the potential difference including the wall potential inside or on the surface of the discharge unit 20 around the electrode is higher than the potential difference at the start of discharge. Here, rapid ionization multiplication progresses in time, and strong discharge is generated. In the latter half T2 of the initialization period in which the applied voltage of the scan electrode 19a is switched from the positive voltage to the negative voltage, the voltage of the scan electrode 19a falls from the peak voltage due to excessive wall charges accumulated in the first half T1 of the initialization period. Sometimes a strong discharge occurs.

  In this way, while monitoring whether or not a strong discharge has occurred in the all-cell initialization period, the panel temperature was changed for the prototype 5 and the prototype 6 while monitoring the strong discharge in the first half of the initialization. The limit slope of the generated ramp voltage was measured. Here, the constant current circuit I1 of the ramp voltage generation circuit RMP1 was controlled by a circuit configuration combining a p-type semiconductor, a MOSFET, and a volume resistor. Further, when a strong discharge is generated in a certain cell, light emission is stronger than other cells that are weakly discharged, and the occurrence of a strong discharge can be confirmed visually. Therefore, strong discharge was monitored by both APD and visual observation.

  The electron emission performance at each panel temperature is known by a preliminary experiment described later, and the relationship between the electron emission performance and the limit slope has been clarified by this experiment. The results are shown in FIG.

  In Prototype 5, it can be seen that when the panel temperature is low, the electron emission performance is remarkably deteriorated, and the slope of the ramp voltage must be made gentler. On the other hand, in Prototype 6, no strong discharge occurred regardless of the panel temperature even when the slope of the ramp voltage was set to 20 V / μsec, which is the measurement limit of the evaluation device. In FIG. 15, the limit slope of the prototype 6 is plotted as 20 V / μsec.

  In Prototype 5, in order to prevent strong discharge in the all-cell initialization period, the gradient of the ramp voltage must be made gentler, and the initialization period must be extended. Therefore, means for shortening the sustain period and the writing period can be considered.

  However, the shortening of the maintenance period becomes a serious problem when the definition is increased. In the high-definition PDP, the cell pitch is reduced, the ratio of the metal electrodes and partition walls in the pixel is increased, the aperture ratio is decreased, and the luminance is decreased. Further, if the initializing period is extended to prevent the above-mentioned strong discharge and the sustain period is shortened, the maximum number of sustain pulses is reduced and the peak luminance is lowered. Overlapping the above, in the high-definition PDP, the bright place contrast is remarkably deteriorated, and the image quality is extremely deteriorated.

  If the address period is shortened, the scan voltage period becomes shorter than the discharge delay time, and the address operation cannot be performed normally. As an example, FIG. 16 shows the relationship between the electron emission performance and the write operation error occurrence rate when the scan voltage cycle is set to 1.2 μsec. In Prototype 5, when the panel temperature becomes low, the electron emission performance deteriorates, the discharge delay time becomes long, and the address operation cannot be performed normally. On the other hand, in the prototype 6 according to the present invention, a writing operation error does not occur and a stable writing operation can be performed.

  From the above, the prototype 5 cannot achieve both strong discharge prevention in the initialization period and time restrictions on the sustain period and the address period.

  Here, the aforementioned preliminary experiment will be described. In the preliminary experiment, the relationship between the relative value of the electron emission performance calculated from the reciprocal of the statistical delay time Ts and the panel temperature was examined. The results are shown in FIG. Here, in the electron emission performance, the electron emission performance at the panel temperature of 30 ° C. was set to 1 in the prototype 5, and the relative values of the other panel temperatures and the electron emission performance of the prototype 6 were calculated.

  FIG. 17 shows that the electron emission performance per unit time deteriorates rapidly as the panel temperature decreases. On the other hand, Prototype 6 stably maintains high electron emission performance regardless of the panel temperature.

  (Verification Experiment 3) In the prototype 6 related to the present invention, the driving waveform 1 related to the conventional driving method and the driving waveform 2 related to the present invention were applied, and the lighting failure due to the discharge interference between adjacent cells was compared. . In the driving waveform 1 related to the conventional driving method, an erasing voltage having a rectangular waveform having a rising edge of 37 V / μsec was applied in the selective initialization period. In the driving waveform 2, a ramp voltage that gradually rises to 10 V / μsec was applied in the first half of the selective initialization period. A lighting photograph with the driving waveform 1 is shown in FIG. 18, and a lighting photograph with the driving waveform 2 is shown in FIG.

  As can be seen from FIG. 18, in the driving method 1 in which a rectangular waveform was applied during the selective initialization period, a large number of cells that caused lighting failures were observed. On the other hand, as shown in FIG. 19, in the driving waveform 2 to which a ramp voltage that gradually increases during the selective initialization period was applied, no cell causing a lighting failure was observed. In the drive waveform 1, strong discharge occurs in the selective initialization period, and discharge interference between adjacent cells is large. In the drive waveform 2, weak discharge occurs in the selective initialization period, and discharge interference between adjacent cells is small. The strength of the discharge during the selective initialization period in each drive waveform was confirmed by APD.

  Regarding Prototype 6, as a result of investigating the slope of the ramp voltage in the first half of the selective initialization period when the degree of discharge interference varies due to variations in the dielectric layer thickness within the panel surface, and the video display fails, The slope limit of the slope voltage was 25 V / [mu] sec to 35 V / [mu] sec in both cases.

  According to the present invention, regardless of the all-cell initializing period and the selective initializing period, the occurrence of strong discharge in the initializing period can be suppressed, and a stable address operation can be performed at a Vscn voltage of 120 V or less. A high-quality, low-cost plasma display device can be provided.

Example 1
A plasma display device using a PDP in which the crystal grains 18b of the protective layer 18 have an average particle size in the range of 0.9 μm to 2 μm will be described. In the following description, the particle diameter means an average particle diameter, and the average particle diameter represents a volume cumulative average diameter (D50). The particle size can be measured by observing the crystal particles with an SEM.

  In the prototype 4 of the present invention described with reference to FIG. 12, the electron emission performance was examined by changing the particle diameter of the MgO crystal particles. The results are shown in FIG.

  When the particle size was reduced to about 0.3 μm, the electron emission performance was lowered. When the particle size was about 0.9 μm or more, high electron emission performance was obtained.

  Next, in Prototype 4 of the present invention described with reference to FIG. 12, a certain number of crystal particles having different particle diameters were dispersed on the surface of the protective layer 18 per unit area, and the probability of breakage of the partition walls was examined. The results are shown in FIG. In order to increase the number of electrons emitted in the discharge cell, it is desirable that the number of crystal grains per unit area on the protective layer 18 is large. However, when crystal particles are present between the tops of the partition walls 15 of the back plate PA2 that are in close contact with the protective layer 18 of the front plate PA1, some of the partitions are damaged when the front plate PA1 and the back plate PA2 are sealed. . A part of the damaged barrier rib material falls into the discharge part 20, and a defect that the cell does not normally turn on and off occurs. Defects due to the breakage of the partition walls are conspicuous when a large number of crystal particles are present on the tops of the partition walls. Therefore, if the number of attached crystal particles is increased, the probability of the breakage of the partition walls is increased.

  As can be seen from FIG. 21, when the grain size of the crystal particles increases to about 2.5 μm, the probability of partition wall breakage increases rapidly. On the other hand, if the grain size is smaller than 2.5 μm, the probability of partition wall breakage can be kept relatively small.

  Based on the above results, considering the manufacturing variation of the crystal particles 18b and the process variation when forming the protective layer 18, it is desirable that the crystal particles have a particle size of 0.9 μm or more and 2.0 μm or less.

  In order to suppress damage to the underlying protective layer 18a due to ion sputtering of the discharge gas, the aggregated particle group and the underlying protective layer 18a are preferably made of the same material in the process of recrystallization after ion sputtering. Therefore, the base protective layer 18a is also preferably composed of MgO of the same quality as the crystal particles 18b.

  According to (Example 1) of the present invention, an electron emission performance of 6 or more and a charge retention performance of a Vscn voltage of 120 V or less can be obtained. Both of the charge holding ability can be satisfied, whereby a PDP having high definition and high luminance display performance and low power consumption can be realized.

(Example 2)
The driving method according to the present invention has a field in which at least one of the fields related to image display has at least one field in which the initialization operation performed during the initialization period of each SF is a selective initialization operation. It relates to the device. Here, FIG. 22 shows drive waveforms to be implemented.

  Hereinafter, the verification of the effect of this embodiment will be described. The PDP used in this verification is prototype 5 and prototype 6.

  First, by using the drive waveform of FIG. 9 according to the present invention, the second voltage Vb1 in the all-cell initialization period was changed, and the luminance at the time of black display was measured. At that time, the total of the voltages related to the discharge in the first half of the initialization period and the latter half of the initialization period was measured as the initialization jump-out voltage. Specifically, in the first half of the initialization period, the voltage between the first voltage Va1 and the second voltage Vb1 is Vf1, the voltage at which discharge starts, and in the second half of the initialization period, the third voltage Vc1 and the fourth voltage. When the voltage between Vd1 and the voltage at which discharge starts is Vf2, the initialization jump-out voltage is (Vb1-Vf1) + (Vf2-Vd1). A schematic diagram regarding the measurement of the initialization jump-out voltage is shown in FIG.

  FIG. 24 shows a plot of initialization pop-up voltage on the horizontal axis and luminance during black display (hereinafter referred to as black luminance) on the vertical axis. Here, the slopes of the ramp voltages in the first half of the initialization period and the second half of the setup period are both set to 2 V / μsec, the third voltage Vc1 is set to 210 V, and the fourth voltage is set to 132 V. According to the study by the present inventors, the relationship between the voltage related to the weak discharge (initialization jump-out voltage) and the light emission amount due to the weak discharge is higher than the composition of the protective layer 18 when the cell structure such as the electrode distance and the cell pitch is the same. The dependence of the discharge gas was significant. In the prototype 5 and the prototype 6, the same cell structure and the same discharge gas are used, and the configuration of the protective layer 18 is different, so that the same tendency is obtained in the black luminance characteristics.

  In the PDP according to the present invention and the driving method of FIG. 9, when the cell write operation is performed in the field preceding the field, the initialization jump-out voltage in the all-cell initialization operation in the field is selected. It will be larger by Vb1-Vb2 at the maximum than the initialization jump-out voltage in the initialization operation. In the SF before the SF, the cell that has performed the write operation is in a state in which more wall charges are accumulated than the cell that has not performed the write operation, and the second voltage applied during the all-cell initialization operation The initialization operation (here, the selective initialization operation) can be performed with the second voltage Vb2 lower than Vb1.

  However, if the charge retention performance is low, the accumulated wall charge is gradually lost during the rest period from the writing operation to the selective initialization operation, and the selective initialization operation is performed normally. It becomes impossible to do.

  For example, in the prototype 2 and the prototype 5, when the panel temperature is increased by continuously displaying, the charge retention performance is deteriorated, and the minimum scan voltage Vscn necessary for the write operation is rapidly increased. In prototype 3, the minimum scan voltage Vscn greatly exceeds the reference value 120V regardless of the panel temperature. On the other hand, in the prototype 4 and the prototype 6, the minimum scan voltage Vscn does not increase regardless of the panel temperature, and is lower than the reference value 120V.

  Actually, when the driving method according to the present invention shown in FIG. 22 is applied to the prototype 2, the prototype 3, and the prototype 5, the selective writing operation cannot be performed due to a lack of wall charges depending on the cell, and the image is normally displayed. Cannot display. On the other hand, when the driving method according to the present invention shown in FIG. 22 is performed on the prototype 4 and the prototype 6, the strong discharge in the initialization operation can be suppressed and the selective addressing operation can be performed.

  Therefore, in a PDP related to a conventional example with low charge retention performance, a desired wall charge is accumulated in the write operation by the initialization operation unless the all-cell initialization operation having a high peak value is performed at least once for each field. I can't. In the PDP according to the present invention, the charge retention performance is stable and high regardless of the panel temperature, so that it is not necessary to perform the all-cell initialization operation for each field.

  In the PDP according to the present invention and the driving method shown in FIG. 9, in the cell in which the write operation is performed as described above, an extra voltage of Vb1-Vb2 is applied at the maximum during the all-cell initialization operation. For example, in the driving method of FIG. 9 in which Vb1−Vb2 = 100 V is set, when the all-cell initializing operation is performed on the cell on which the writing operation has been performed, the black luminance increases by 89% at the maximum. Therefore, in the PDP having high charge holding performance according to the present invention, the number of all cell initialization operations can be reduced as shown in FIG. 22, and the black luminance can be lowered as compared with FIG. Can be provided.

(Example 3)
FIG. 26 shows an example of a drive circuit in this embodiment, and FIG. 25 shows an operation waveform, which relates to a plasma display device characterized in that the slope of the ramp voltage changes midway in the drive system according to the present invention.

  The drive circuit of the present embodiment is configured to use the power supply voltage Vic of the scan IC as one of the slowly rising ramp voltages. A constant current circuit I3, a capacitor C3, a diode D3, a resistor R3, a switch SW7, a slope generating circuit RAMP3 composed of a power supply voltage Vb, a scan IC in which a high side switch SW10 and a low side switch SW11 are connected in series, a power supply voltage for writing operation The scan voltage selection circuit D includes a switch SW8 and a switch SW9 connected in series at both ends of Vscn, and a scan potential raising circuit E including a voltage comparator. The output terminal of the ramp generation circuit RAMP3 and the midpoint of the scan voltage selection circuit D are connected to the power input terminal of the scan IC. Further, the negative electrode of the power supply Vscn and the other end of the switch SW9 are connected to the GND of the scan IC and also connected to the power supply Vs. Finally, the middle point of the scan IC is output to the scan electrode 19. Note that one scan IC is arranged in parallel for each scan electrode 19a, and the scan voltage selection circuit D is a circuit for controlling on / off of a scan pulse in an address period.

  Hereinafter, an operation of the drive circuit in the initialization period will be described. First, only the low-side switch SW11 of the scan IC is turned on (more precisely, via a diode), and the voltage Vs is applied to the scan electrode 19a. The voltage Vs here is 0V. Next, high is input to the signal S3, and the power supply voltage Vb for generating the ramp voltage is applied to the scan IC via the switch SW7. However, the switch SW8, the switch SW9, and the switch SW10 are off and are not output to the scan electrode 19a. During this time, the main voltage Vs is rapidly increased from 0 V to Va and applied to the scanning electrode 19a.

  Next, the low side switch SW11 of the scan IC is turned off and the high side switch SW10 is turned on. At this time, since the charging current from the constant current circuit I3 charges the parasitic capacitances of the switch SW9 and the switch SW10, the high-side switch SW10 is turned on until the voltage applied to the scan IC is charged to the operation start voltage. Instead, the voltage is held at Va. When the voltage of the scan IC exceeds the operation start voltage, the switch SW10 starts to be turned on, and the voltage applied to the scan IC by the charging current becomes a ramp voltage and increases from the voltage Va to the voltage (Va + Vic). After a voltage equal to or higher than Vic is applied to the scan IC and the switch SW10 is completely turned on, the voltage is output until the ramp voltage becomes the voltage Vb according to the ramp voltage generation circuit RMP3.

  After the ramp voltage reaches the power supply voltage Vb, the signal S3 is turned off, the switch SW8 is turned on, and falls to the voltage (Va + Vscn) via the switches SW8 and SW10. Next, the switch SW9 and the switch SW11 are turned on, the voltage of the scan IC becomes 0V, and falls to the voltage Va.

  With the above-described circuit configuration, two periods with different slopes of the ramp voltage can be provided, and a voltage waveform in which the back ramp voltage has a gentler slope than the previous ramp voltage can be generated. Note that the circuit configuration shown in FIG. 26 is an example of output of ramp voltages having two different slopes, and is not limited to this.

  According to the present embodiment, the slope of the ramp voltage is set gradually gradually in the first half of the initialization period. When the opening and closing of the shutter is controlled by the gate signal generator and the state of discharge spreading during the initialization operation is observed from the front of the panel using a high-sensitivity CCD camera, the first voltage Va in the initialization operation using the ramp voltage is observed. As the voltage changes to the second voltage Vb, the sustain electrode 19b and the address electrode 14 are used as the negative electrode, the scan electrode 19a is used as the positive electrode, and from the inner side (the side closer to the center of the discharge cell) to the outer side (the side closer to the discharge cell partition). It was found that the discharge progressed to.

  The PDP according to the present invention has excellent electron emission characteristics and can suppress a strong discharge during the initialization operation. However, when the discharge spreads outward, an excess is present in the barrier ribs and the phosphors in the vicinity of the barrier ribs. There is a case where charging occurs, the writing operation after the initialization operation is abnormal, and the image display cannot be performed normally. Therefore, by gradually reducing the slope of the ramp voltage, it is possible to weaken the discharge in the time zone in which the discharge spreads outward and to alleviate excess charging on the side wall. Furthermore, by providing a period in which the voltage of the address electrode 14 is positive in the first half of the initialization period, it is possible to suppress the spread of discharge and alleviate excess charging on the side wall.

  In addition, by increasing the slope in the first time zone of the ramp voltage, the time required for the initialization operation can be shortened, and the write operation related to the stability of the image display and the maintenance operation related to the brightness of the image are more frequent. Will be able to spend more time.

  As described above, in the PDP according to the present invention, in the plasma display device using the driving method according to the present invention, the long-term reliability of the protective layer 18 serving as the electron emission source, the manufacturing variation of the PDP and the driving circuit, the initialization operation In consideration of image quality deterioration due to the occurrence of strong discharge at the time and image quality deterioration due to excessive charging on the side wall, it is preferable to set the gradient of the ramp voltage to 20 V / μsec or less.

Example 4
The driving method according to the present invention is a plasma display characterized in that the scan potential raising circuit E is removed from the circuit configuration shown in FIG. 26, and the potential of the scan pulse applied to the scan electrode 19a is the same potential as the fourth voltage Vd. It relates to the device. In the PDP according to the present invention, the charge holding performance is stable, and the loss of wall charges in the pause period waiting for the write operation is small. Therefore, it is possible to omit the voltage Vset2 inserted to compensate for the voltage corresponding to the lost charge. There are cases where it is possible. In this case, the scan potential raising circuit E can be eliminated, and a lower cost plasma display device can be provided.

  The plasma display device according to the present invention is a plasma display panel having a plurality of aggregated particle groups in which a plurality of crystal particles made of a metal oxide are aggregated in the periphery of the protective layer 18, and the initialization period is the second period The first half of the initialization period in which a voltage that gradually increases from the first voltage to the second voltage is applied to the electrode, and the second half of the initialization period in which the voltage that gradually decreases from the third voltage to the fourth voltage is applied to the second electrode It is useful as an image display device that displays an image with good image quality by a drive system having a portion. Further, it can be applied to uses such as an image display device using a plasma display improved in efficiency by a high Xe partial pressure ratio and a high total pressure, and a full-spec high-definition plasma display.

The perspective view which shows the main part of the panel used for embodiment of this invention Electrode wiring diagram of panel in the embodiment of the present invention Configuration diagram of plasma display device using the same PDP SF configuration diagram of one television field in the PDP driving method Timing chart of drive voltage applied to each electrode of the PDP Explanatory drawing which expands and shows the protective layer part of the PDP Enlarged view for explaining aggregated particles in the protective layer of the PDP Process drawing which shows the process of protective layer formation in the manufacturing method of PDP concerning this invention Timing chart of driving voltage applied to each electrode of the PDP in the driving system according to the present invention The figure which shows an example of the drive circuit structure for outputting the drive waveform Characteristic diagram showing the results of cathodoluminescence measurement of crystal particles FIG. 5 is a characteristic diagram showing the relationship between the electron emission performance and the Vscn lighting voltage indicating the charge retention performance in an experiment for verifying the effect of the plasma display device according to the present invention. The figure which shows the APD output voltage in the case of weak discharge in the all-cell initialization period The figure which shows the APD output voltage in the case of a strong discharge in the all-cell initialization period FIG. 5 is a characteristic diagram showing the relationship between the electron emission performance and the limit gradient of the initialization ramp voltage in an experiment for verifying the effect of the plasma display device according to the present invention. FIG. 5 is a characteristic diagram showing the relationship between the electron emission performance and the limit gradient of the initialization ramp voltage in an experiment for verifying the effect of the plasma display device according to the present invention. FIG. 5 is a characteristic diagram showing the relationship between the panel temperature and the electron emission performance in an experiment for verifying the effect of the plasma display device according to the present invention. In an experiment for verifying the effect of the plasma display device according to the present invention, a photograph showing an image in which a display state when a drive waveform 1 is applied is displayed on the display In an experiment for verifying the effect of the plasma display device according to the present invention, a photograph showing an image in which the display state when the driving waveform 2 according to the present invention is applied is displayed on the display Characteristic diagram showing the relationship between crystal grain size and electron emission characteristics Characteristic diagram showing the relationship between the grain size of crystal grains and the incidence of partition wall breakage Timing chart of drive voltage applied to each electrode in Example 2 of the present invention Diagram for explaining initialization pop-out voltage FIG. 6 is a characteristic diagram showing the relationship between the initialization jump-out voltage and the black luminance in the experiment for verifying the effect of the plasma display device according to the present invention. FIG. 10 is a diagram illustrating an example of a driving waveform applied to the scan electrode 19a in the first half of the initialization period and the second half of the initialization period in the third embodiment of the present invention. FIG. 10 is a diagram illustrating an example of a scan electrode driving circuit for outputting the driving waveform in the third embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display panel 11 Front glass substrate 12 Rear glass substrate 13 Base dielectric layer 14 Address electrode 15 Partition 16 Phosphor layer 17 Dielectric layer 17a First dielectric layer 17b Second dielectric layer 18 Protective layer 18a Base protection Layer 18b Crystal particle 18c Aggregated particle group 19a1 Sustain transparent electrode 19a2 Sustain metal electrode 19b1 Scan transparent electrode 19b2 Scan metal electrode 20 Discharge unit 21 Scan electrode drive circuit 22 Sustain electrode drive circuit 23 Address electrode drive circuit 24 Timing generation circuit 25 A / D Converter 26 Scanning line number conversion unit 27 Subfield conversion unit 28 APL detection unit 31 All-cell initialization period 32 Write period 33 Maintenance period 34 Select initialization period 35 Initialization period

Claims (11)

Having at least one pair of first electrode and second electrode in parallel, forming a dielectric layer around the first electrode and the second electrode, forming a protective layer on the surface of the dielectric layer; A first substrate in which a plurality of aggregated particle groups in which a plurality of crystal particles made of metal oxide are aggregated is arranged in the periphery of the protective layer, and at least one third electrode, and a dielectric in the periphery of the third electrode In a plasma display panel in which a second substrate on which a layer is formed is arranged oppositely, and a discharge gas is sealed between the opposing first substrate and second substrate
One field is composed of a plurality of subfields, and each subfield has at least an initialization period and an address period among an initialization period, an address period, and a sustain period, and the initialization period is connected to the second electrode. A first half of an initialization period in which a voltage that gradually increases from one voltage to a second voltage is applied; and a second half of an initialization period in which a voltage that gradually decreases from a third voltage to a fourth voltage is applied to the second electrode; An image display is performed by a driving method including: a plasma display device. 2. The plasma display device according to claim 1, wherein the crystal particles have an average particle size in a range of 0.9 μm to 2 μm. The plasma display device according to claim 1, wherein the protective layer is made of magnesium oxide (MgO). 4. The plasma display device according to claim 1, further comprising at least one field in which all initialization operations performed during the initialization period are selective initialization operations. 5. The first half of the initialization period has at least two or more periods in which the slope of the rising voltage is different, and the slope of the subsequent period is gentler than that of the previous period. The plasma display device according to any one of the above. 6. The initial period includes at least two periods having different slopes of the voltage falling, and the slope of the later period is gentler than that of the previous period. The plasma display device according to any one of the above. 7. The plasma display device according to claim 1, wherein the voltage of the scan pulse applied to the second electrode is the same potential as the fourth voltage in the address period. 8. The plasma display device according to claim 1, wherein the first half of the initialization period includes a period in which the voltage of the third electrode is positive. 9. The plasma display device according to claim 1, wherein the rising voltage slope in the first half of the initialization period is 20 V / μsec or less. 10. The plasma display device according to claim 1, wherein the slope of the voltage that falls in the latter half of the initialization period is 20 V / μsec or less. 11. The plasma display device according to claim 1, wherein a period of a scan pulse applied to the second electrode in the address period is 0.5 μsec to 1.8 μsec.