JP2009253240A5 - - Google Patents
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- JP2009253240A5 JP2009253240A5 JP2008103146A JP2008103146A JP2009253240A5 JP 2009253240 A5 JP2009253240 A5 JP 2009253240A5 JP 2008103146 A JP2008103146 A JP 2008103146A JP 2008103146 A JP2008103146 A JP 2008103146A JP 2009253240 A5 JP2009253240 A5 JP 2009253240A5
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- Prior art keywords
- substrate
- single crystal
- crystal semiconductor
- protective layer
- semiconductor substrate
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Claims (6)
前記第二の面からイオンを注入して、前記単結晶半導体基板の所定の深さに脆化領域を形成する工程と、
前記単結晶半導体基板の前記第二の面と、支持基板と、を貼りあわせる工程と、
前記脆化領域内にて、前記支持基板と、前記単結晶半導体基板とを分離し、前記支持基板上に単結晶半導体層を形成する工程と、
前記保護層が形成された状態で、前記単結晶半導体基板の表面を酸化し、酸化膜を形成する工程と、
前記保護層が形成された状態で、前記酸化膜を除去する工程と、を有することを特徴とする半導体装置の作製方法。 Forming a protective layer on the first surface of the single crystal semiconductor substrate so that the second surface facing the first surface is warped in a convex shape;
Implanting ions from the second surface to form an embrittled region at a predetermined depth of the single crystal semiconductor substrate ;
Wherein said second surface of the single crystal semiconductor substrate, and the supporting substrate, a step of bonding the,
Separating the support substrate and the single crystal semiconductor substrate in the embrittlement region, and forming a single crystal semiconductor layer on the support substrate;
In a state in which the protective layer is formed by oxidizing the surface of the single crystal semiconductor substrate, forming a oxidation layer,
Wherein in a state where the protective layer is formed, a method for manufacturing a semiconductor device characterized by having the steps of removing the oxidation film.
前記第一の面に対向する第二の面からイオンを注入して、前記単結晶半導体基板の所定の深さに脆化領域を形成する工程と、
前記単結晶半導体基板の前記第二の面と、支持基板と、を貼りあわせる工程と、
前記脆化領域内にて、前記支持基板と、前記単結晶半導体基板とを分離し、前記支持基板上に単結晶半導体層を形成する工程と、
前記保護層が形成された状態で、前記単結晶半導体基板の表面を酸化し、酸化膜を形成する工程と、
前記保護層が形成された状態で、前記酸化膜を除去する工程と、を有することを特徴とする半導体装置の作製方法。 Forming a protective layer having a tensile stress on the first surface of the single crystal semiconductor substrate;
Implanting ions from a second surface facing the first surface to form an embrittled region at a predetermined depth of the single crystal semiconductor substrate;
Wherein said second surface of the single crystal semiconductor substrate, and the supporting substrate, a step of bonding the,
Separating the support substrate and the single crystal semiconductor substrate in the embrittlement region, and forming a single crystal semiconductor layer on the support substrate;
In a state in which the protective layer is formed by oxidizing the surface of the single crystal semiconductor substrate, forming a oxidation layer,
Wherein in a state where the protective layer is formed, a method for manufacturing a semiconductor device characterized by having the steps of removing the oxidation film.
前記保護層は導電性薄膜であることを特徴とする半導体装置の作製方法。 In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the protective layer is a conductive thin film.
前記保護層は複数の層から成り、前記保護層の表面は導電性を有することを特徴とする半導体装置の作製方法。 In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the protective layer includes a plurality of layers, and a surface of the protective layer has conductivity.
前記支持基板はガラス基板、セラミック基板、石英基板、サファイア基板、導電性基板、または半導体基板であることを特徴とする半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the supporting substrate is a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, a conductive substrate, or a semiconductor substrate.
前記イオンはＨThe ion is H ＋+ 、Ｈ, H ２2 ＋+ 、Ｈ, H ３3 ＋+ 、またはこれらの組み合わせであることを特徴とする半導体装置の作製方法。Or a combination of these. A method for manufacturing a semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008103146A JP5264018B2 (en) | 2008-04-11 | 2008-04-11 | Method for manufacturing semiconductor substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008103146A JP5264018B2 (en) | 2008-04-11 | 2008-04-11 | Method for manufacturing semiconductor substrate |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009253240A JP2009253240A (en) | 2009-10-29 |
| JP2009253240A5 true JP2009253240A5 (en) | 2011-03-31 |
| JP5264018B2 JP5264018B2 (en) | 2013-08-14 |
Family
ID=41313603
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2008103146A Expired - Fee Related JP5264018B2 (en) | 2008-04-11 | 2008-04-11 | Method for manufacturing semiconductor substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP5264018B2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP6005364B2 (en) * | 2012-02-06 | 2016-10-12 | ラピスセミコンダクタ株式会社 | Semiconductor device manufacturing method and semiconductor device |
| WO2013187079A1 (en) * | 2012-06-15 | 2013-12-19 | 住友化学株式会社 | Method for producing composite substrate and composite substrate |
| JP6254234B2 (en) * | 2016-09-07 | 2017-12-27 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| JP2018032877A (en) * | 2017-11-29 | 2018-03-01 | ラピスセミコンダクタ株式会社 | Semiconductor device |
| JP2020077710A (en) * | 2018-11-06 | 2020-05-21 | 信越半導体株式会社 | Manufacturing method of semiconductor substrate for light emitting element and manufacturing method of light emitting element |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2751261B2 (en) * | 1988-11-16 | 1998-05-18 | ソニー株式会社 | Semiconductor substrate bonding method |
| JP3943782B2 (en) * | 1999-11-29 | 2007-07-11 | 信越半導体株式会社 | Reclaimed wafer reclaim processing method and reclaimed peeled wafer |
| JP4289837B2 (en) * | 2002-07-15 | 2009-07-01 | アプライド マテリアルズ インコーポレイテッド | Ion implantation method and method for manufacturing SOI wafer |
| JP4624131B2 (en) * | 2005-02-22 | 2011-02-02 | 三洋電機株式会社 | Nitride semiconductor device manufacturing method |
-
2008
- 2008-04-11 JP JP2008103146A patent/JP5264018B2/en not_active Expired - Fee Related
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