JP2009251389A - Display device and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To shorten the time from when display of an image is instructed to when the image is displayed. <P>SOLUTION: A display device, when instructed to display the image, stores image data representing the image in a nonvolatile first VARM in a normal mode, stores image data representing a related image having predetermined relation with the image in a second VRAM other than the first VRAM, and makes a memory type display body display the image corresponding to the image data stored in the first VRAM. Further, the display device, when instructed to display the related image, makes the memory type display body display the related image corresponding to the image data stored in the second VRAM in the normal mode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique for storing image data of an image to be displayed.

A technique for buffering image data representing an image for one screen in a high-speed memory for image data called VRAM (Video Random Access Memory) when displaying an image on a display screen of a display device is known. Patent Document 1 discloses a technique for displaying an image according to image data when the computer apparatus is started or terminated by storing the image data in a non-volatile VRAM.
Japanese Patent Laid-Open No. 2004-127022

By the way, a display device using cholesteric liquid crystal or electrophoresis has a so-called display memory property that can maintain an image display state even when power is not supplied. By taking advantage of the memory property of this display, the power consumption of the display device can be suppressed. For example, when a new image is displayed, the display device is operated in the normal mode in which power is supplied to each component of the display device, and no operation is performed after the image is displayed for a predetermined time. For example, a transition is made to a standby mode in which power is supplied only to a specific configuration of the display device. In this case, after the transition to the standby mode, for example, when an operation for instructing page turning is performed by the operator, the display device displays image data representing an image of the next page of the displayed image, such as a flash memory. The image data is read from the non-volatile storage means and expanded in the VRAM, the image data is read from the VRAM, and each electrophoretic element is driven based on the read image data to display the image of the next page. That is, when the image is displayed after returning from the standby mode to the normal mode, the image data is read from the nonvolatile storage means, the image data is expanded to the VRAM, and the image data is read from the VRAM. There must be. Therefore, assuming that the number of pixels on the display screen is 3104 × 4128, for example, it takes about 200 to 300 msec from the time when the operator performs an operation to instruct page turning until the next page image is actually displayed. It is known that it will take.
The present invention has been made in view of such a background, and an object thereof is to shorten the time from when an image display is instructed to when the image is displayed.

The present invention has a plurality of storage means for maintaining a state in which data is stored without receiving power supply, and a plurality of display elements, and power is supplied during a period until the display elements are driven to display an image. After the image is displayed and the image is displayed, the display unit continues to display the image even when power is not supplied, and after the image is displayed on the display unit, the storage unit and the display unit State transition to a power supply state in which power is supplied to the storage means and the display means when a new image is displayed on the display means. And when instructed to display any one of the plurality of images, the image data representing the image instructed to be displayed in any of the plurality of storage units in the power supply state. is there Memory that is stored in one storage unit and that stores image data representing a related image having a predetermined relationship with respect to the display order of the image in a second storage unit that is the storage unit other than the first storage unit When instructed to display one of a plurality of images by the control means and image data representing the image is stored in the first storage means by the storage control means, the display means When the display device is driven to display an image corresponding to the image data on the display means and when the instruction to display the related image is given, the display device of the display means is driven and the second storage means And a display control unit that displays the related image corresponding to the image data stored in the display unit.
Thereby, it is possible to shorten the time from when the display of the image is instructed to when the image is displayed.

Further, the present invention includes a plurality of storage means for maintaining a state in which data is stored without receiving power supply and a plurality of display elements, and the display element is driven to display an image in a period until the display is performed. After the power is supplied and the image is displayed, the computer of the display device including the display unit that continues to display the image even when the power is not supplied, after the image is displayed on the display unit, When the storage means and the display means are shifted to a non-power supply state in which no power is supplied and a new image is displayed on the display means, power is supplied to the storage means and the display means. Image data representing the image instructed to be displayed in the power supply state when instructed to display the state transition means for transitioning to the power supply state and any one of the plurality of images The image data representing a relation image having a predetermined relationship with the image with respect to the display order is stored in a storage other than the first storage means, stored in a first storage means that is one of the plurality of storage means. Storage control means to be stored in the second storage means, and image data representing the image that is instructed to be displayed is displayed by the storage control means. When stored in the first storage means, the display element of the display means is driven to display an image corresponding to the image data on the display means, and when the instruction to display the related image is given, A program for driving a display element of the display means to function as a display control means for causing the display means to display the related image according to the image data stored in the second storage means. To provide.
Thereby, it is possible to shorten the time from when the display of the image is instructed to when the image is displayed.

[First Embodiment]
First, a first embodiment of the present invention will be described.
<Configuration>
FIG. 1 is a diagram illustrating an appearance of a display device 1 according to the first embodiment, and FIG. 2 is a block diagram illustrating a configuration of the display device 1. The display device 1 is so-called electronic paper configured to be small and lightweight. As shown in the figure, the display device 1 includes a power supply unit 10, a CPU (Central Processing Unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory) 13, a flash memory 14, a VRAM 15A, 15B and 15C, the display control part 16, the memory | storage property display body 17, and the operation part 18 are provided. In the following description, the VRAMs 15A, 15B, and 15C are collectively referred to as “VRAM 15” when it is not necessary to distinguish between them.

  The power supply unit 10 is a rechargeable battery, for example, and supplies power to each unit of the display device 1. The CPU 11 performs various processes according to programs stored in the ROM 12 or the flash memory 14. The ROM 12 stores programs and the like used by the CPU 11. The RAM 13 is, for example, a dynamic random access memory (DRAM) and is used as a work area for the CU 11.

  The flash memory 14 is, for example, a NAND flash memory, and stores programs used by the CPU 11 and various data. The flash memory 14 stores a plurality of image data and a plurality of memory IDs. Image data is data representing an image for each page. This page is an image divided for each screen, which is a range displayed on the memory display 17 at a time. Each image data is associated with a display order corresponding to the page of the image represented by the image data. Thus, the fact that the display order is determined according to the number of pages means that one display order is scheduled by the creator of the image data. That is, each image data has a predetermined relationship regarding the display order. The memory ID is identification information assigned to each VRAM 15. The flash memory 14 stores “01” which is a memory ID assigned to the VRAM 15A, “02” which is a memory ID assigned to the VRAM 15B, and “03” which is a memory ID assigned to the VRAM 15C. It is assumed that

  Each of the VRAMs 15A, 15B, and 15C is a nonvolatile storage unit that stores image data representing an image for one page displayed on the storage-type display body 17. This non-volatile storage means is a storage means that maintains a state in which data is stored without receiving power supply. The VRAM 15 is, for example, an FeRAM (Ferroelectric Random Access Memory) that reads and writes at high speed using a ferroelectric, or an MRAM (Magnetoresistive Random Access Memory) that uses magnetism. When this MRAM is employed, it is desirable to use a spin injection type MRAM that can read and write a large amount of data at high speed. The VRAM 15 is preferably a dual port RAM that can simultaneously perform data writing by the CPU 11 and data reading by the display control unit 16.

  The display control unit 16 is a display control unit that drives the display element of the memory display 17 based on the image data stored in any one of the VRAMs 15 and displays an image corresponding to the image data. The display control unit 16 is, for example, an FPGA (Field Programmable Gate Array) circuit. The memory display 17 includes a plurality of display elements such as cholesteric liquid crystal and electrophoresis, and is a display unit that displays an image by driving these display elements by the display control unit 16. The memory display 17 requires electric power during a driving period from when the display element is driven until an image is displayed. However, after the driving period elapses and an image is displayed, electric power is supplied. Even if it is not done, the image can be continuously displayed. Hereinafter, this is referred to as display memory.

  The operation unit 18 includes a plurality of operation buttons, and is an operation unit that receives an operation by an operator and supplies operation information corresponding to the operation to the CPU 11. As shown in FIG. 1, the operation buttons include a page feed button Br for instructing page feed, a page return button Bl for instructing page return, and the like.

  Here, the operation mode of the display device 1 will be described. The display device 1 operates in either the normal mode or the standby mode. The normal mode is a power supply state in which power is supplied to each unit of the display device 1 including the VRAM 15 and the memory display body 17 by the power supply unit 10. In this normal mode, for example, a process for displaying a new image on the memory display 17 is performed. The standby mode is a power non-supply state in which power consumption is less than that in the normal mode, and power is supplied only to limited parts of the display device 1 by the power supply unit 10. In the standby mode, no power is supplied to the CPU 11 and the display control unit 16, or less power is supplied than in the normal mode, and no power is supplied to the VRAM 15 and the memory display 17.

  The transition from the normal mode to the standby mode is performed, for example, when the operation unit 18 is not operated for a predetermined time after an image is displayed on the memory display 17 in the normal mode. The transition from the standby mode to the normal mode is performed, for example, when the operation unit 18 is operated in the standby mode and a display of a new image is instructed on the memory display 17. That is, after the image is displayed on the memory display 17, the CPU 11 shifts to a power non-supply state in which power is not supplied to the VRAM 15 and the memory display 17, and a new image is displayed on the memory display 17. When displayed, it functions as a state transition means for shifting to a power supply state in which power is supplied to the VRAM 15 and the memory display 17.

<Operation>
Next, the operation of the display device 1 will be described. When it is desired to display an image on the display device 1, the operator uses the operation unit 18 to specify an image to be viewed and to perform an operation for instructing the display.
FIG. 3 is a flowchart showing display processing performed at this time. When the operation unit 18 receives an operation for instructing display of an image, the CPU 11 acquires a display instruction corresponding to the operation (step SA10). Subsequently, the CPU 11 displays an image (hereinafter referred to as “display image”) in which a page of an image (hereinafter referred to as “instruction image”) designated as an image to be displayed in the display instruction is displayed on the memory display 17. ) Is determined whether the page is before or after (step SA20). When the page of the instruction image is not a page before or after the display image, or when the image is not displayed on the memory display 17, the CPU 11 determines that the page of the instruction image is not a page before or after the display image. (Step SA20: NO), non-front and back page display processing is performed (Step SA30). On the other hand, when the page of the instruction image is a page before and after the display image (step SA20: YES), the CPU 11 performs a front and rear page display process (step SA40).

(Non-front and back page display processing)
For example, it is assumed that a display instruction for instructing the display of the image of the first page is acquired in a state where the image is not displayed on the memory-type display body 17 in Step SA10 described above. In this case, since the image is not displayed on the memory display 17 in step SA20 described above, it is determined that the page of the instruction image is not a page before or after the display image (step SA20: NO), and in subsequent step SA30. Non-front and back page display processing is performed.

  FIG. 4 is a flowchart showing the non-front / rear page display processing. First, the CPU 11 reads image data representing an instruction image from the flash memory 14 and stores it in one of the VRAMs 15 (step SA110). In this example, since the instruction image is the first page image, image data representing the first page image is stored in the VRAM 15A. Subsequently, the CPU 11 creates a queue list for managing the storage contents of the VRAM 15 and stores it in the flash memory 14 (step SA120).

  FIG. 5A shows the queue list q1 created at this time. As shown in the figure, the queue list q1 is associated with the memory ID of the VRAM 15 in which the image data is stored in step SA110 and the page ID for identifying the page of the image data stored in the VRAM 15. Stored. In this example, the memory ID “01” of the VRAM 15A is stored in association with “Page1” which is the page ID of one page. Further, the memory ID “01” is associated with a pointer “current” indicating that the image data of the image displayed on the memory display 17 is stored in the VRAM 15 to which the memory ID is assigned. . Furthermore, the memory ID “01” and the page ID “Page1” are associated with a pointer “head” indicating the head of the queue and a pointer “tail” indicating the end of the queue.

  Subsequently, the CPU 11 supplies the memory ID of the VRAM 15 in which the image data is stored in Step SA110 to the display control unit 16 (Step SA130). Specifically, the CPU 11 supplies the display control unit 16 with the memory ID associated with the pointer “current” in the queue list q 1 of the flash memory 14. As shown in FIG. 5A, in the queue list q1, since the pointer “current” is associated with the memory ID “01”, the memory ID “01” is supplied to the display control unit 16.

  When the memory ID is supplied by the CPU 11, the display control unit 16 refers to the correspondence relationship between the memory ID stored in the flash memory 14 and the VRAM 15, and specifies the VRAM 15 to which the memory ID is assigned. The image corresponding to the image data stored in the VRAM 15 is displayed on the storage-type display body 17 (step SA140). In this example, since the memory ID “01” is supplied by the CPU 11, the VRAM 15A to which the memory ID “01” is assigned is specified, and an image corresponding to the image data stored in the VRAM 15A is displayed in the memory display 17. Is displayed. As described above, the image data representing the image of the first page is stored in the VRAM 15A. Accordingly, the first page image instructed to be displayed by the operator is displayed on the memory display 17.

  In parallel with this, the CPU 11 reads out image data representing the images of the pages before and after the instruction image from the flash memory 14 and stores them in the VRAM 15 in which no image data is stored in step SA110 described above (step SA150). Here, the instruction image is an image selected by the operator from a plurality of images in which the display order is determined, and the images on the pages before and after the instruction image are one image before the instruction image instructed to be displayed. Or it is a related image of the display order of one back. In other words, when the CPU 11 is instructed to display any one of the plurality of images, the CPU 11 outputs the image data representing the image instructed to be displayed in any of the plurality of VRAMs 15 in the normal mode in the power supply state. Is stored in the first storage means, and image data representing a relation image having a predetermined relationship with respect to the image and the display order is stored in the second storage means which is the VRAM 15 other than the first storage means. It functions as a storage control means. The processing in step SA150 is performed until the instruction image is displayed on the memory display 17 in step SA140 described above.

  More specifically, first, the CPU 11 refers to the queue list q1 of the flash memory 14 and specifies a VRAM 15 in which image data is not stored (hereinafter referred to as “free VRAM”). As shown in FIG. 5A, since only the memory ID “01” of the VRAM 15A is stored in the queue list q1, the VRAM 15B and the VRAM 15C are specified as free VRAMs. Subsequently, the CPU 11 reads out the image data representing the images of the pages before and after the instruction image from the flash memory 14 and stores them in the empty VRAM. In this example, since the instruction image is the image of the first page without the previous page, only the image data of the second page, which is the next page of the instruction image, is read from the flash memory 14 and is one of the free VRAMs. It is stored in a certain VRAM 15B.

  Although the example in which the instruction image is the first page image without the previous page has been described here, the instruction image for which the display instruction is first given is, for example, the fifth page image with the previous and next pages. In some cases, the image data of the sixth page, which is the next page of the instruction image, is stored in the VRAM 15B, which is one of the free VRAMs, and the image data of the fourth page, which is the previous page of the instruction image, remains. Are stored in the VRAM 15C, which is an empty VRAM.

Subsequently, the CPU 11 updates the queue list stored in the flash memory 14 (step SA160).
FIG. 5B shows the updated queue list q2. As shown in the figure, in this update, the memory ID “02” of the VRAM 15B in which the image data is stored in the above-described step SA150 and the VRAM 15B are stored in the queue list q1 shown in FIG. “Page2” which is the page ID of the second page of image data is added. Further, the memory ID “02” and the page ID “Page2” are associated with a pointer “tail” indicating the end of the queue.

(Previous page display process when performing page feed)
Next, it is assumed that after the first page image is displayed on the memory display 17 as described above, the page feed button Br of the operation unit 18 is pressed and a page feed instruction is issued. . In this case, in step SA10 described above, a page feed instruction is acquired as a display instruction. In step SA20, since the display image is the first page image and the instruction image is the next second page image, it is determined that the page of the instruction image is a page before and after the display image ( Step SA20: YES), and subsequent page display processing is performed in the subsequent step SA40.

  FIG. 6 is a flowchart showing the front and rear page display processing. First, the CPU 11 determines whether or not the page of the instruction image is the next page of the display image (step SA210). In this example, since the page of the display image is the first page and the page of the instruction image is the second page after that, it is determined that the page of the instruction image is the next page of the display image (step SA210). : YES) Subsequently, the CPU 11 supplies the memory ID of the VRAM 15 in which the image data of the instruction image is stored to the display control unit 16 (Step SA220). Specifically, the CPU 11 supplies the memory ID associated with the page ID of the page of the instruction image in the queue list q2 of the flash memory 14 to the display control unit 16. In this example, since the page of the instruction image is the second page, in the queue list q2 shown in FIG. 5B, the memory ID “02” associated with “Page2” which is the page ID of the second page. Is supplied to the display control unit 16.

  When the memory ID is supplied by the CPU 11, the display control unit 16 specifies the VRAM 15 to which the memory ID is assigned and stores an image corresponding to the image data stored in the specified VRAM 15 in the same manner as described above. Display on the sex display 17 (step SA230). The image displayed at this time corresponds to the related image described above. Therefore, when the display control unit 16 is instructed to display the related image, the display control unit 16 drives the display element of the memory-type display body 17 in the normal mode which is the power supply state, and stores the display element in the above-described second storage unit. The related image corresponding to the image data thus displayed is displayed on the memory display 17. In this example, since the memory ID “02” is supplied by the CPU 11, the VRAM 15 B to which the memory ID “02” is assigned is specified, and an image corresponding to the image data stored in the VRAM 15 B is displayed in the memory display 17. Is displayed. As described above, the image data representing the image of the second page is stored in the VRAM 15B. Therefore, the second display image instructed to be displayed by the operator is displayed on the memory display 17.

  In parallel with this, the CPU 11 reads out the image data representing the image of the next page of the instruction image from the flash memory 14, and is a free VRAM in which no image data is stored or a memory associated with a pointer “head”. It is stored in one of the VRAMs 15 (hereinafter referred to as “overwrite VRAM”) to which the ID is assigned (step SA240). At this time, the VRAM 15 to which the memory ID associated with the pointer “head” is assigned is used as the overwriting VRAM because the VRAM 15 stores image data representing an already displayed image. is there. As described above, the images on the pages before and after the instruction image are related images having a predetermined relationship with the instruction image. In other words, when the CPU 11 is instructed to display any one of the plurality of images, the CPU 11 outputs the image data representing the image instructed to be displayed in any of the plurality of VRAMs 15 in the normal mode in the power supply state. Is stored in the first storage means, and image data representing a relation image having a predetermined relationship with respect to the image and the display order is stored in the second storage means which is the VRAM 15 other than the first storage means. . The process of step SA240 is performed until the instruction image is displayed on the memory display 17 in step SA230 described above.

  Specifically, first, the CPU 11 refers to the queue list q2 stored in the flash memory 14, and specifies either a free VRAM or an overwrite VRAM. As shown in FIG. 5B, since the memory ID “03” of the VRAM 15C is not stored in the queue list q2, the VRAM 15C is specified as an empty VRAM. At this time, the empty VRAM is preferentially used over the overwrite VRAM because the image data already stored in the VRAM 15 does not have to be erased. Subsequently, the CPU 11 reads out the image data representing the image of the next page of the instruction image from the flash memory 14 and stores it in the specified VRAM 15C. In this example, since the page of the instruction image is the second page, the image data of the next third page is stored in the VRAM 15C.

Subsequently, the CPU 11 updates the queue list stored in the flash memory 14 (step SA250).
FIG. 5C shows the updated queue list q3. In this update, for the queue list q2 shown in FIG. 5B, the memory ID “03” of the VRAM 15C in which the image data is stored in step SA240 described above, and the image data of the third page stored in the VRAM 15C. The page ID “Page3” is added. The memory ID “03” and the page ID “Page3” are associated with a pointer “tail” indicating the end of the queue. Further, the pointer “current” described above is associated with the memory ID “02” supplied to the display control unit 16 in step SA220 described above.

(Previous page display processing when returning from standby mode)
Here, it is assumed that the operator does not operate the operation unit 18 for a predetermined time after the second page image is displayed on the memory display 17 as described above. In this case, the CPU 11 shifts its operation mode from the normal mode to the standby mode. As described above, when shifting to the standby mode, almost no power is supplied to the CPU 11 and the display control unit 16, and no power is supplied to the memory display 17 and the VRAM 15. However, as described above, since the memory display 17 has display memory, the state where the image of the second page is displayed is maintained. Further, since the VRAM 15 is a non-volatile storage unit, it maintains a state where image data is stored. Specifically, the VRAM 15A maintains the state where the image data of the first page is stored, the VRAM 15B maintains the state where the image data of the second page is stored, and the VRAM 15C stores the state of storing the image data of the third page. maintain.

  It is assumed that after the transition to the standby mode in this way, the page feed button Br of the operation unit 18 is pressed by the operator and a page feed instruction is issued. When the page feed button Br of the operation unit 18 is pressed, the CPU 11 shifts the operation mode of the own apparatus from the standby mode to the normal mode. When the mode is shifted to the normal mode, the power supply to each part of the display device 1 is resumed, and the display process described above is started. In this case, in step SA10 described above, a page feed instruction is acquired as a display instruction. In subsequent step SA20, since the display image is the image of the second page and the instruction image is the image of the next third page, it is determined that the page of the instruction image is a page before and after the display image (step SA20). : YES), a subsequent page display process is performed in the subsequent step SA40.

  At this time, in step SA210 described above, since the page of the display image is the second page and the page of the instruction image is the third page, it is determined that the page of the instruction image is the next page of the display image (step). SA210: YES). In the subsequent step SA220, since the page of the instruction image is the third page, in the queue list q3 shown in FIG. 5C, the memory ID “03” associated with the page ID “Page3” of the third page. Is supplied to the display control unit 16. In the subsequent step SA230, the VRAM 15C to which the memory ID “03” is assigned is specified, and an image corresponding to the image data of the third page stored in the VRAM 15C is displayed on the memory display 17. Thereby, the image of the third page instructed to be displayed by the operator is displayed on the memory display 17.

  In parallel with this, in step SA240 described above, the image data of the next page of the instruction image is read from the flash memory 14 and stored in either the empty VRAM or the overwrite VRAM. As shown in FIG. 5C, the queue list q3 stores all the memory IDs of the VRAMs 15A to 15C, and there is no free VRAM, so the memory ID “head” associated with the pointer “memory” “ The VRAM 15A to which “01” is assigned is specified as the overwrite VRAM. Subsequently, since the page of the instruction image is the third page, the image data of the fourth page, which is the next page, is read from the flash memory 14 and stored in the specified VRAM 15A. In step SA250, the queue list stored in the flash memory 14 is updated.

  FIG. 5D shows the updated queue list q4. In this update, first, the page ID “Page1” and the memory ID “01” stored in the queue list q3 shown in FIG. 5C are deleted, and the page ID “Page2” that is the page ID of the second page is deleted. ”And the memory ID“ 02 ”are associated with a pointer“ head ”indicating the head of the queue. Subsequently, the memory ID “01” of the VRAM 15A in which the image data is stored in step SA240 described above and “Page 4” which is the page ID of the fourth page of image data newly stored in the VRAM 15A are added. The memory ID “01” and the page ID “Page4” are associated with a pointer “tail” indicating the end of the queue. Further, the above-described pointer “current” is associated with the memory ID “03” supplied to the display control unit 16 in step SA220.

(Previous page display process when performing page return)
Next, after the image of the third page is displayed on the memory display 17 as described above, the page return button Bl of the operation unit 18 is pressed by the operator and the page return instruction is issued. Is assumed. In this case, in step SA10 described above, a page return instruction is acquired as a display instruction. In subsequent step SA20, since the display image is the image of the third page and the instruction image is the image of the second page before that, it is determined that the page of the instruction image is a page before and after the display image (step SA20). : YES), a subsequent page display process is performed in the subsequent step SA40. At this time, in step SA210 described above, since the page of the display image is the third page and the page of the instruction image is the second page, it is determined that the page of the instruction image is not the next page of the display image (step SA210: NO). In this case, the CPU 11 supplies the memory ID of the VRAM 15 in which the image data of the instruction image is stored to the display control unit 16 (step SA260). In this example, since the page of the instruction image is the second page, the memory ID “02” associated with the page ID “Page2” of the second page is displayed in the queue list q4 illustrated in FIG. It is supplied to the control unit 16.

  When the memory ID is supplied by the CPU 11, the display control unit 16 specifies the VRAM 15 to which the memory ID is assigned in the same manner as described above, and stores an image corresponding to the image data stored in the specified VRAM 15. It is displayed on the display body 17 (step SA270). In this example, since the memory ID “02” is supplied by the CPU 11, the VRAM 15B to which the memory ID “02” is assigned is specified, and an image corresponding to the image data stored in the VRAM 15B is displayed on the memory-type display body 17. Is displayed. As described above, the image data representing the image of the second page is stored in the VRAM 15B. Therefore, the second display image instructed to be displayed by the operator is displayed on the memory display 17. Subsequently, the CPU 11 updates the queue list stored in the flash memory 14 in step SA250. In this example, in the queue list q4 shown in FIG. 5D, the above-described pointer “current” is associated with the memory ID “02” supplied to the display control unit 16 in step SA220.

  According to the embodiment described above, the image data of the pages before and after the display image is stored in the VRAM 15 in advance, so that the display of the pages before and after the display of the pages before and after the display image is instructed is displayed. Time can be shortened. Further, since the VRAM 15 is a non-volatile storage unit, the image data of the pages before and after the display image can be continuously stored even when the standby mode in which no power is supplied is entered. Thereby, after returning from the standby mode to the normal mode, the images of the pages before and after the display image can be displayed more quickly than in the case where the VRAM 15 is a volatile storage unit.

[Second Embodiment]
Next, a second embodiment of the present invention will be described. In the first embodiment described above, the case where the image data stored in the VRAM 15 has a structure in which the display order is determined has been described. In the second embodiment, a case where the image data has a hierarchical structure will be described.

<Configuration>
First, the configuration of the display device 2 according to the second embodiment will be described.
FIG. 7 is a block diagram illustrating a configuration of the display device 2. As shown in the figure, the display device 2 includes a VRAM 15D in addition to the VRAMs 15A to 15C described above. Other configurations of the display device 2 are the same as the configurations shown in FIGS. 1 and 2. The flash memory 14 stores a plurality of memory IDs, a plurality of image data, and a management list. First, the contents of the memory ID will be described. The memory ID is identification information assigned to each VRAM 15 as in the first embodiment described above. It is assumed that “04”, which is a memory ID assigned to the VRAM 15D, is stored in the flash memory 14 in addition to the memory IDs “01” to “03” described above.

Next, the contents of the image data will be described. This image data is data representing each hierarchically connected image, for example, PDF (Portable Document Format) data to which a link is added, HTML (HyperText Markup Language) data representing a Web page, and the like. Thus, the fact that the image data has a hierarchical structure means that one display order is scheduled by the creator of the image data. That is, each image data has a predetermined relationship regarding the display order.
FIG. 8 is a diagram schematically showing a hierarchical structure of image data. The image data A belongs to the 0th hierarchy which is the highest hierarchy. Image data B to E, which are child nodes of the image data A, belong to the first hierarchy that is one level below the 0th hierarchy. Image data F, which is a child node of image data C, and image data G and H, which are child nodes of image data D, belong to the second layer, which is one layer below the first layer.

Next, the contents of the management list will be described. The management list is information for managing the storage contents of each VRAM 15.
FIG. 9A shows the management list 11 when no image data is stored in any of the VRAMs 15A to 15D. The management list l1 stores the memory IDs “01” to “04” of the VRAMs 15A to 15D, and the image data is not stored in the VRAM 15 to which the memory ID is assigned for each memory ID. Is associated with a flag “free”. When image data is stored in the VRAM 15, the memory ID of the VRAM 15 is associated with a data ID for identifying the stored image data and a flag “used” indicating that the image data is stored. Are associated with each other.

<Operation>
Next, the operation of the display device 2 will be described. When it is desired to display an image on the display device 2, the operator uses the operation unit 18 to specify an image to be viewed and to perform an operation for instructing the display.
FIG. 10 is a flowchart showing display processing performed at this time. When the operation unit 18 receives an operation for instructing display of an image, the CPU 11 acquires a display instruction corresponding to the operation (step SB10). Subsequently, the CPU 11 determines whether or not the node of the instruction image specified as the image to be displayed in the display instruction is a parent or child node of the display image (step SB20). When the node of the instruction image is not the parent or child node of the display image, or when the image is not displayed on the memory display 17, the CPU 11 determines that the node of the instruction image is the parent or child node of the display image. It is determined that there is not (step SB20: NO), and non-parent / child node display processing is performed (step SB30). On the other hand, when the node of the instruction image is a parent or child node of the display image (step SB20: YES), the CPU 11 performs a parent-child node display process (step SB40).

(Non-parent / child node display process)
For example, it is assumed that in step SB10 described above, a display instruction for instructing display of an image represented by the image data A is acquired in a state where no image is displayed on the memory-type display body 17. In this case, in step SB20 described above, no image is displayed on the memory display 17, so it is determined that the node of the instruction image is not the parent or child node of the display image (step SB20: NO), and the following step In SB30, non-parent / child node display processing is performed.

FIG. 11 is a flowchart showing the non-parent / child node display processing. First, the CPU 11 reads image data representing an instruction image from the flash memory 14 and stores it in one of the VRAMs 15 (step SB110). In this example, since the instruction image is an image of the image data A, the image data A is stored in the VRAM 15A. Subsequently, the CPU 11 updates the management list stored in the flash memory 14 (step SB120).
FIG. 9B is a diagram showing the updated management list l2. In the management list l2, the memory ID “01” of the VRAM 15A in which the image data is stored in step SB110 and the data ID “Data A” of the image data A stored in the VRAM 15A are stored in association with each other. . The memory ID “01” is associated with a flag “used” indicating that image data is stored.

  Subsequently, the CPU 11 supplies the memory ID of the VRAM 15 in which the image data is stored in step SB110 to the display control unit 16 (step SB130). Specifically, the CPU 11 supplies the display control unit 16 with a memory ID associated with the data ID representing the image data of the instruction image in the management list 12 of the flash memory 14. In this example, since the image data of the instruction image is the image data A, the memory ID “01” associated with the data ID “DataA” of the image data A in the management list l2 illustrated in FIG. It is supplied to the display control unit 16.

  When the memory ID is supplied by the CPU 11, the display control unit 16 specifies the VRAM 15 to which the memory ID is assigned, according to the image data stored in the specified VRAM 15, as in the first embodiment. The displayed image is displayed on the memory display 17 (step SB140). In this example, since the memory ID “01” is supplied by the CPU 11, the VRAM 15A to which the memory ID “01” is assigned is specified, and an image corresponding to the image data stored in the VRAM 15A is displayed on the memory display body 17. Is done. As described above, the image data A is stored in the VRAM 15A. Therefore, an image of the image data A instructed to be displayed by the operator is displayed on the memory display 17.

  In parallel with this, the CPU 11 reads the image data of the parent and child nodes of the instruction image from the flash memory 14 and stores them in the VRAM 15 in which no image data is stored in step SB110 described above (step SB150). Here, the instruction image is an image selected by the operator from a plurality of images in which an image corresponding to the parent node and an image corresponding to the child node are hierarchically connected. The image of the node is a related image directly connected by a link to the instruction image that is instructed to be displayed. In other words, when the CPU 11 is instructed to display any one of the plurality of images, the image data representing the image instructed to be displayed is displayed in any one of the plurality of VRAMs 15 in the normal mode in which the power is supplied. The image data representing the relationship image having a predetermined relationship with the image is stored in the second storage unit which is the VRAM 15 other than the first storage unit. The processing in step SB150 is performed until the instruction image is displayed on the memory display 17 in step SB140 described above.

  Specifically, first, the CPU 11 refers to the management list 12 of the flash memory 14 and specifies an empty VRAM in which no image data is stored. As shown in FIG. 9B, in the management list l2, since the flag “free” indicating that no image data is displayed is associated with the memory IDs “02” to “04”, the VRAM 15B to 15D is specified as an empty VRAM. Subsequently, the CPU 11 reads the image data of the parent and child nodes of the instruction image from the flash memory 14 and stores them in the specified empty VRAM. As shown in FIG. 8, in this example, since the instruction image is an image represented by the image data A in the highest hierarchy without a parent node, only image data of child nodes of the image data A is read sequentially from the left side in the figure. And stored in the empty VRAM. Specifically, the image data B is stored in the VRAM 15B, the image data C is stored in the VRAM 15C, and the image data D is stored in the VRAM 15D. The image data E is not stored in the VRAM 15 because there is no free VRAM.

Subsequently, the CPU 11 updates the management list stored in the flash memory 14 (step SB160).
FIG. 9C shows the updated management list l3. In the management list l3, the data ID of the stored image data is associated with the memory ID of each VRAM 15 in which the image data is stored in step SB150 described above. In this example, “Data B” that is the data ID of the image data B is associated with the memory ID “02” of the VRAM 15B, and “Data C” that is the data ID of the image data C is associated with the memory ID “03” of the VRAM 15C. The data ID “DataD” of the image data D is associated with the memory ID “04” of the VRAM 15D. Further, the flags “used” indicating that the image data is stored are associated with the memory IDs “02” to “04”, respectively.

(Parent-child node display process)
Next, after the image represented by the image data A is displayed on the memory display 17 as described above, the operation unit 18 is operated to instruct display of the image data D which is a child node of the display image. Assuming that In this case, in step SB10 described above, an instruction to display the image represented by the image data D is acquired. In subsequent step SB20, since the display image is an image of image data A and the instruction image is an image of image data D of its child node, the node of the instruction image is a parent or child node of the node of the display image. Determination is made (step SB20: YES), and a parent-child node display process is performed in the subsequent step SB40.

  FIG. 12 is a flowchart showing parent-child node display processing. First, the CPU 11 determines whether or not the node of the instruction image is a child node of the display image (step SB210). If the node of the instruction image is a parent node of the display image, it is determined that the node of the instruction image is not a child node of the display image (step SB210: NO). In this case, the CPU 11 supplies the display controller 16 with the memory ID of the VRAM 15 in which image data representing the instruction image is stored (step SB220). When the memory ID is supplied by the CPU 11, the display control unit 16 specifies the VRAM 15 to which the memory ID is assigned in the same manner as described above, and stores an image corresponding to the image data stored in the specified VRAM 15. It is displayed on the display body 17 (step SB230). As a result, an image instructed to be displayed by the operator is displayed on the memory display 17.

  On the other hand, as in this example, when the display image is an image of image data A and the instruction image is an image of image data D of its child node, it is determined that the node of the instruction image is a child node of the display image. (Step SB210: YES). In this case, the CPU 11 supplies the memory ID of the VRAM 15 in which image data representing the instruction image is stored to the display control unit 16 (step SB240). More specifically, the CPU 11 supplies the display control unit 16 with a memory ID associated with the data ID of the image data of the instruction image in the management list l3 of the flash memory 14. In this example, since the image data of the instruction image is the image data D, the memory ID “04” associated with the data ID “DataD” of the image data D in the management list l3 illustrated in FIG. It is supplied to the display control unit 16.

  When the memory ID is supplied by the CPU 11, the display control unit 16 specifies the VRAM 15 to which the memory ID is assigned in the same manner as described above, and stores an image corresponding to the image data stored in the specified VRAM 15. It is displayed on the display body 17 (step SB250). The image displayed at this time corresponds to the related image described above. Therefore, when the display control unit 16 is instructed to display the related image, the display control unit 16 drives the display element of the memory-type display body 17 in the normal mode which is the power supply state, and stores the display element in the above-described second storage unit. The related image corresponding to the image data thus displayed is displayed on the memory display 17. In this example, since the memory ID “04” is supplied by the CPU 11, the VRAM 15D to which the memory ID “04” is assigned is specified, and an image corresponding to the image data stored in the VRAM 15D is displayed on the memory-type display body 17. Is done. As described above, the image data D is stored in the VRAM 15D. Therefore, an image of the image data D instructed to be displayed by the operator is displayed on the memory display 17.

  In parallel with this, the CPU 11 specifies the VRAM 15 other than the VRAM 15 storing the image data of the instruction image and the VRAM 15 storing the image data of the parent node of the instruction image, and is stored in the specified VRAM 15. The image data is deleted (step SB260). More specifically, the CPU 11 first associates a data ID representing the image data of the instruction image with a data ID other than the data ID representing the image data of the parent node of the instruction image in the management list l3 of the flash memory 14. The specified memory ID is specified. In this example, the image data of the instruction image is the image data D, and as shown in FIG. 8, the image data of the parent node of the image data D is the image data A. Therefore, the management list shown in FIG. In l3, memory IDs “02” and “03” associated with data IDs other than “Data A” and “Data D” are specified. Subsequently, the CPU 11 deletes the image data stored in the VRAM 15 to which the specified memory ID is assigned. In this example, the image data B stored in the VRAM 15B assigned the memory ID “02” and the image data C stored in the VRAM 15C assigned the memory ID “03” are deleted. As shown in FIG. 8, since the image data B and C are sibling nodes of the image data D that is the image data of the instruction image, the image data D and the image data B and C are directly transitioned. This is because there is nothing to do. Subsequently, the CPU 11 updates the management list stored in the flash memory 14 (step SB270).

  FIG. 9D shows the updated management list 14. In this management list 14, the data IDs associated with the memory IDs “02” and “03” of the VRAMs 15 B and 15 C are deleted, and image data are respectively stored in the memory IDs “02” and “03”. Is associated with a flag “free” indicating that is not stored. Further, the memory ID “04” supplied to the display control unit 16 in step SB240 described above stores the image data of the image displayed on the memory display 17 in the VRAM 15 to which the memory ID is assigned. A pointer “current” indicating this is associated.

  Subsequently, the CPU 11 stores the image data of the child node of the instruction image in the VRAM 15 from which the image data has been deleted in step SB260 described above (step SB280). As described above, the image of the child node of the instruction image is a relation image connected to the instruction image. In other words, when the CPU 11 is instructed to display any one of the plurality of images, the image data representing the image instructed to be displayed is displayed in any one of the plurality of VRAMs 15 in the normal mode in which the power is supplied. The image data representing the relationship image having a predetermined relationship with the image is stored in the second storage unit which is the VRAM 15 other than the first storage unit. The processing in steps SB260 to SB280 is performed until the instruction image is displayed on the memory display 17 in step SB250 described above. In this example, the image data of the instruction image is the image data D, and the child nodes of the image data D are the image data G and the image data H as shown in FIG. 8, so the image data G is stored in the VRAM 15B. Image data H is stored in the VRAM 15C. Subsequently, the CPU 11 updates the management list stored in the flash memory 14 (step SB290).

  FIG. 9E shows the updated management list l5. In the management list 15, the data ID of the image data stored in the VRAM 15 is associated with the memory ID of the VRAM 15 in which the image data is stored in step SB 280 described above. In this example, “DataG” that is the data ID of the image data G is associated with the memory ID “02” of the VRAM 15B, and “DataH” that is the data ID of the image data H is associated with the memory ID “03” of the VRAM 15C. It is done. Further, a flag “used” indicating that image data is stored is associated with each of the memory IDs “02” and “03”.

  According to the embodiment described above, the image data of the child of the display image or the image of the parent node is stored in the VRAM 15 in advance, so that the image is displayed after the display of the image of the child of the display image or the parent node is instructed. The time until it is done can be shortened. Further, as described above, since the VRAM 15 is a non-volatile storage unit, compared to the case where the VRAM 15 is a volatile storage unit, after returning from the standby mode to the normal mode, the child or parent node of the display image is displayed. Images can be displayed promptly.

[Modification]
The above is the description of the embodiment, but the contents of this embodiment can be modified as follows. Further, the following modifications may be combined as appropriate.

(Modification 1)
In the first embodiment described above, only the image data of the pages before and after the instruction image is stored in the VRAM 15, but the operation unit 18 of the display device 1 includes an operation button for receiving an operation for instructing display of a specific image. If so, the image data representing the specific image may be stored in the VRAM 15. Here, the display device 1 includes VRAMs 15D to 15F in addition to the above-described VRAMs 15A to 15C, and the operation unit 18 includes operation buttons B1 to B4 that respectively receive instructions for displaying specific images. Is assumed. The operation button B1 is an operation unit that receives an operation for instructing the display of the image of the first page, and the operation button B2 is an operation unit that receives an operation of instructing the display of the image of the 10th page, and the operation button B3 Is an operation means for accepting an operation for instructing the display of the image of the 20th page, and the operation button B4 is an operation means for accepting an operation for instructing the display of the image of the last page.

  FIG. 13 is a diagram illustrating an example of image data storage processing for storing image data corresponding to an operation button. First, the CPU 11 counts the number of times each operation button is operated, creates a histogram representing the operation frequency for each operation button, and stores it in the flash memory 14 or the like. This histogram is preferably in a management format standardized between 0-1. Here, it is assumed that the histogram H1 shown in FIG. In the histogram H1, the operation frequency decreases in the order of the operation button B3 → the operation button B4 → the operation button B2 → the operation button B1. In this case, the priority order of the image data of the 20th page corresponding to the operation button B3 is first, the priority order of the image data of the last page corresponding to the operation button B4 is second, and the priority order is 10 corresponding to the operation button B2. The priority order of the image data of the page is No. 3, and the priority order of the image data of the first page corresponding to the operation button B1 is No. 4. The CPU 11 stores the image data of the pages before and after the display image in the VRAMs 15A to 15C in the same manner as in the first embodiment described above, and first, the image of the 20th page having the first priority order. The data is stored in the VRAM 15D, the image data of the last page having the second priority is stored in the VRAM 15E, and the image data of the tenth page having the third priority is stored in the VRAM 15F. Note that the image data of the first page having the fourth priority is not stored in the VRAM 15 because there is no VRAM 15 in which no image data is stored.

  That is, the CPU 11 selects a specific image whose display is instructed by an operation received by an operation button having an operation frequency higher than that of other operation buttons, among image data representing a specific image that is displayed by an operation received by the operation button. Is stored in the VRAM 15 in which no image data is stored. As described above, the fact that the image data stored in the VRAM 15 is determined based on the operation transfer frequency of the operation buttons means that the display device 1 prepares the display order based on the operation history of the operator. That is, it can be said that each image data has a predetermined relationship regarding the display order.

Further, when the operation frequency of the operation button is changed, the operation is as follows.
FIG. 14 is a diagram for explaining the image data storage process when the histogram H2 is created. In this histogram H2, the operation frequency decreases in the order of the operation button B3 → the operation button B1 → the operation button B4 → the operation button B2. In this case, the priority order of the image data of the 20th page corresponding to the operation button B3 is first, the priority order of the image data of the first page corresponding to the operation button B1 is second, and the last priority corresponding to the operation button B4. The priority of the image data of the page No. 3 is 3, and the priority of the image data of the 10th page corresponding to the operation button B2 is No. 4. In the same manner as described above, the CPU 11 first stores the image data of the 20th page having the first priority in the VRAM 15D, and then stores the image data of the first page having the second priority in the VRAM 15E. Then, the image data of the last page having the third priority is stored in the VRAM 15F. It should be noted that the image data of the 10th page with priority 4 is not stored in the VRAM 15 because there is no VRAM 15 in which no image data is stored.

Further, image data of a page corresponding to an operation button whose operation frequency by the operator is higher than a predetermined threshold may be preferentially stored in the VRAM 15.
FIG. 15 is a diagram for explaining image data storage processing when image data of a page corresponding to an operation button whose operation frequency is higher than a predetermined threshold is stored preferentially. In this histogram H3, the operation buttons whose operation frequency is higher than the threshold value L are the operation button B1 and the operation button B3, and the operation frequency decreases in the order of the operation button B3 → the operation button B1. In this case, the priority order of the image data of the 20th page corresponding to the operation button B3 is first, and the priority order of the image data of the first page corresponding to the operation button B1 is second. In the same manner as described above, the CPU 11 first stores the image data of the 20th page having the first priority in the VRAM 15D, and then stores the image data of the first page having the second priority in the VRAM 15E. Let Note that image data of pages corresponding to the operation buttons B2 and B4 whose operation frequency is equal to or less than the threshold value L is not stored in the VRAM 15. Further, the VRAM 15F in which no image data is stored at this time may be used for storing other image data.

In addition, the operation unit 18 may include a plurality of operation buttons that respectively accept operations for transitioning to a specific folder. In this case, in the same manner as described above, the CPU 11 prioritizes image data representing a list of files stored in the folder corresponding to each operation button based on the operation frequency of each operation button. Image data representing a list of files is stored in the VRAM 15 according to the order.
Further, this modification may be applied to the second embodiment. In this case, the display device 2 includes three VRAMs 15 in addition to the above-described VRAMs 15A to 15D, and the operation unit 18 of the display device 2 includes operation buttons B1 to B4 that respectively receive instructions for displaying specific images. It will be.
According to this modification, it is possible to quickly display an image that is instructed to be displayed by an operation that is frequently operated by the operator.

(Modification 2)
In the second embodiment described above, when the image data of the child node of the instruction image is stored in the VRAM 15, the image data is read and stored in a predetermined order. Among them, image data of an image having a high frequency (hereinafter referred to as “transition frequency”) displayed after the instruction image is displayed may be preferentially stored in the VRAM 15. As described above, the fact that the image data stored in the VRAM 15 is determined based on the frequency of transition from the display image means that the display device 2 prepares the display order based on the browsing history of the operator. Become. That is, it can be said that each image data has a predetermined relationship regarding the display order.

  FIG. 16 is a diagram illustrating an example of image data storage processing for preferentially storing image data of an image with a high transition frequency from the instruction image. First, the CPU 11 counts the number of times the pointer “current” described above is associated with each data ID stored in the management list of the flash memory 14, and creates a histogram representing the transition frequency for each image data. It is stored in the flash memory 14. This histogram is desirably a management format standardized between 0 and 1 as in the first modification described above.

  Here, it is assumed that the histogram H4 is created as a histogram representing the transition frequency from the image of the image data A, and the histogram H5 is created as a histogram representing the transition frequency from the image of the image data D. First, in the histogram H4, the image data of the image data A having the highest transition frequency from the image is the image data B, and the transition frequency is low in the order of image data B → image data E → image data D → image data C. It will become. In this case, the priority order of the image data B is No. 1, the priority order of the image data E is No. 2, the priority order of the image data D is No. 3, and the priority order of the image data C is No. 4. When the CPU 11 stores the image data of the child node of the image data A in the VRAM 15, the image data is read in the order of image data B → image data E → image data D → image data C having a high priority, and the image data is stored. It is stored in the VRAM 15 that is not. That is, the CPU 11 stores, in the VRAM 15 in which no image data is stored, image data representing a related image that is displayed after the display image and is higher in frequency than other related images among the plurality of related images.

  The same applies when image data of child nodes of the image data D is stored in the VRAM 15. In the histogram H5, the image data having the highest transition frequency from the image of the image data D is the image data H, and the image data having the next highest transition frequency is the image data G. In this case, the priority order of the image data H is first, and the priority order of the image data G is second. When the CPU 11 stores the image data of the child nodes of the image data D in the VRAM 15 in the same manner as described above, the image data is read in the order of image data H → image data G having the highest priority, and no image data is stored. The data is stored in the VRAM 15.

Further, only the image data of an image whose transition frequency is higher than a predetermined threshold may be stored in the VRAM 15 in the same manner as in the first modification described above.
Further, this modification may be applied to the first embodiment described above. In this case, the CPU 11 creates a histogram representing the transition frequency from the image of each page. Then, the CPU 11 determines the priority order of each image data in descending order of the transition frequency from the display image, and stores the image data in the VRAM 15 according to the priority order.
According to this modification, it is possible to preferentially store the image data of an image that is frequently viewed by the operator next to the instruction image in the VRAM 15.

(Modification 3)
In the above-described embodiment, the queue list or the management list is sequentially stored in the flash memory 14, but the present invention is not limited to this. For example, while operating in the normal mode, it may be stored in the RAM 13, and the queue list or management list stored in the RAM 13 may be stored in the flash memory 14 when shifting from the normal mode to the standby mode. .

(Modification 4)
In the above-described embodiment, the example in which the display device 1 includes a plurality of VRAMs 15 has been described. However, only one VRAM 15 that is logically divided into a plurality of VRAMs 15 may be included. In this case, one VRAM 15 corresponds to a plurality of storage means.
In the second embodiment described above, the display device 1 includes the four VRAMs 15, but more VRAMs 15 may be included. As described above, when a large number of VRAMs 15 are provided, it is possible that the process of storing the image data of the child nodes of the instruction image is not completed before the instruction image is displayed. In this case, it is desirable to end the image data storage process when the instruction image is displayed.

(Modification 5)
In the second embodiment described above, the storage contents of the VRAM 15 are managed by the management list, but the present invention is not limited to this. For example, the image data having the hierarchical structure shown in FIG. 8 may be managed in association with the memory ID of the VRAM 15 storing the image data.

(Modification 6)
The processing performed by the display control unit 16 described above may be executed by the CPU 11 according to a program. Each program executed by the CPU 11 is stored in a recording medium readable by a computer device such as a magnetic recording medium such as a magnetic tape or a magnetic disk, an optical recording medium such as an optical disk, a magneto-optical recording medium, or a semiconductor memory. It can be provided in the state. It is also possible to download this program via a network such as the Internet.

It is a figure which shows the external appearance of the display apparatus which concerns on 1st Embodiment. It is a block diagram which shows the structure of the said display apparatus. It is a flowchart which shows the display process which concerns on 1st Embodiment. It is a flowchart which shows the non-front-and-back page display process in the said display process. It is a figure which shows the cue list produced in the said non-back-and-front page display process. It is a flowchart which shows the front and back page display process in the said display process. It is a block diagram which shows the structure of the display apparatus which concerns on 2nd Embodiment. It is a figure which shows typically the hierarchical structure of the image data memorize | stored in the said display apparatus. It is a figure which shows the management list memorize | stored in the said display apparatus. It is a flowchart which shows the display process which concerns on 2nd Embodiment. It is a flowchart which shows the non-parent-child node display process in the said display process. It is a flowchart which shows the parent-child node display process in the said display process. It is a figure explaining an example of the image data storage process concerning the modification 1. It is a figure explaining another example of the image data storage process which concerns on the modification 1. FIG. It is a figure explaining another example of the image data storage process which concerns on the modification 1. FIG. It is a figure explaining an example of the image data storage process concerning the modification 2.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 2 ... Display apparatus, 10 ... Power supply part, 11 ... CPU, 12 ... ROM, 13 ... RAM, 14 ... Flash memory, 15 ... VRAM, 16 ... Display control part, 17 ... Memory | storage display body, 18 ... Operation part

Claims (8)

A plurality of storage means for maintaining a state of storing data without receiving power supply;
It has a plurality of display elements, and power is supplied during a period from when the display elements are driven until an image is displayed. After the image is displayed, the image is displayed even if power is not supplied. Display means to continue,
After the image is displayed on the display means, the storage means and the display means are shifted to a power non-supply state in which power is not supplied, and when a new image is displayed on the display means, the storage means And state transition means for shifting to a power supply state in which power is supplied to the display means,
When instructed to display any one of the plurality of images, in the power supply state, the image data representing the image instructed to be displayed is one of the plurality of storage units. Storage control for storing image data representing a relational image having a predetermined relationship with respect to the display order of the image in a second storage means other than the first storage means. Means,
When instructed to display one of a plurality of images and image data representing the image is stored in the first storage unit by the storage control unit, the display element of the display unit is driven. Then, an image corresponding to the image data is displayed on the display means, and when the display of the related image is instructed, the display element of the display means is driven and stored in the second storage means And a display control means for displaying the related image according to image data on the display means. The storage control means represents the related image after the image data representing the image that is instructed to be displayed is stored in the first storage means until the image is displayed on the display means. The display device according to claim 1, wherein image data is stored in the second storage unit. The display order is determined for the plurality of images,
The display device according to claim 1, wherein the related image is an image in a display order immediately before or after the image instructed to be displayed. The plurality of images are images in which an image corresponding to a parent node and an image corresponding to a child node are hierarchically connected,
The display device according to claim 1, wherein the related image is an image corresponding to a parent node or an image corresponding to a child node of the image instructed to be displayed. There are a plurality of related images,
The storage control means stores, in the second storage means, image data representing a relation image whose frequency displayed on the display means is higher than a predetermined threshold among the plurality of relation images. The display device according to claim 1, wherein the display device is a display device. A plurality of operation means each for receiving an operation for instructing display of a specific image among the plurality of images;
The storage control unit is configured to store image data representing the specific image whose display is instructed by an operation received by the operation unit, other than the first storage unit and the second storage unit among the plurality of storage units. The display device according to claim 1, wherein the display device is stored in the storage unit. The storage control unit is configured to store image data representing the specific image instructed to be displayed by another operation unit or an operation received by the operation unit having an operation frequency higher than a predetermined threshold among the plurality of storage units. The display device according to claim 6, wherein the display device is stored in a storage unit other than the first storage unit and the second storage unit. It has a plurality of storage means for maintaining the state of storing data without receiving power supply, and a plurality of display elements, and power is supplied in a period until the display elements are driven to display an image, After the image is displayed, a computer of a display device including display means that continues to display the image even when power is not supplied,
After the image is displayed on the display means, the storage means and the display means are shifted to a power non-supply state in which power is not supplied, and when a new image is displayed on the display means, the storage means And state transition means for shifting to a power supply state in which power is supplied to the display means,
When instructed to display any one of the plurality of images, in the power supply state, the image data representing the image instructed to be displayed is one of the plurality of storage units. Storage control for storing image data representing a related image having a predetermined relationship with the image with respect to the display order in a second storage means other than the first storage means. Means,
When one of the plurality of images is instructed to be displayed and image data representing the image instructed to be displayed is stored in the first storage means by the storage control means, the display means When the display device is driven to display an image corresponding to the image data on the display means and when the instruction to display the related image is given, the display device of the display means is driven and the second storage means A program for functioning as display control means for causing the display means to display the related image corresponding to the image data stored in the display.

Images