JP2017134843A - Information processor and display controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce power consumption and processing time required for pre-processing for electronic paper.SOLUTION: An information processor comprises a first memory being a nonvolatile memory, and switches electric power supplied to the first memory to any of first electric power capable executing first processing and second electric power lower than the first electric power while executing the first processing with respect to first data stored in the first memory. The information processor includes a plurality of candidates of the first processing, executes the first processing in a state of the electric power supplied to the first memory being the first electric power when the number of the plurality of candidates of the first processing is less than a predetermined threshold value, switches the electric power supplied to the first memory from the first electric power to the second electric power after completion of the first processing, and switches the electric power supplied to the first memory from the first electric power to the second electric power, subsequently restores the electric power to the first electric power again and executes the first processing when the number of the candidates of the first processing is equal to the threshold value or more.SELECTED DRAWING: Figure 1

Description

  Embodiments described herein relate generally to an information processing apparatus and a display control apparatus.

  In portable information processing devices such as slate terminals and tablet terminals, and information processing devices such as electronic POPs (Point Of Purchase advertising), electronic posters, and electronic medical records, efficient use of power is an important technical issue. . By using a low power consumption display such as electronic paper that consumes very little power other than during display rewriting as the display device of these information processing devices, power consumption during standby such as while the user is browsing the display can be reduced. Can be suppressed.

  In general, in the rewriting process of electronic paper, a two-stage process is required, that is, a preprocess for data to be displayed (hereinafter referred to as rewrite data) and a drawing process for rewriting the display of the electronic paper with the data obtained by the preprocess. become. The pre-processing for electronic paper is composed of two processes, a processing process and a selection process. In the processing, preprocessed rewritten data is generated by processing the rewritten data itself such as an image. In the selection process, information such as drive voltage (hereinafter referred to as rewrite control information) used when rewriting the electronic paper display with preprocessed rewrite data is selected, and information (hereinafter referred to as rewrite control information) is selected. Rewrite control information selection information) is generated. These processes are processes that require a large amount of power consumption and processing time due to a large processing amount.

JP2011-193387A JP 2002-230970 A

Freescale Semiconductor, Inc., “i.MX50 Multimedia Applications Processor Reference Manual”, Rev.1, Chapter 24 Electrophoretic Display Controller (EPDC), 10/2011

  An object of the following embodiments is to provide an information processing apparatus and a display control apparatus capable of reducing power consumption and processing time required for preprocessing for electronic paper.

  An information processing apparatus according to an embodiment includes a first memory that is a non-volatile memory, performs a first process on first data stored in the first memory, and supplies power supplied to the first memory to the first memory. In the information processing apparatus that switches between the first power that can execute the first process and the second power that is lower than the first power, the information processing apparatus includes a plurality of candidates for the first process, When the number of candidates for one process is smaller than a predetermined threshold, the first process is executed with the power supplied to the first memory as the first power, and the first process is completed after the first process is completed. The power supplied to one memory is switched from the first power to the second power, and when the number of candidates for the first processing is equal to or greater than the threshold, the power supplied to the first memory is changed to the first power. 1 power? It is returned again to the first power after switching to the second power to execute the first processing.

  The display control apparatus according to the embodiment includes a preprocessing unit that generates the first image data for display from data that is the basis of the first image data stored in the first memory, and the preprocessing unit. A management unit that transfers processed rewritten data including the first image data generated by the second memory to the second memory, and when the display device is rewritten using the first image data, the processed rewritten data is stored in the second memory. A determination unit for determining whether or not the processed rewritten data is stored in the second memory, and the rendering processing of the display device using the processed rewritten data stored in the second memory A rewrite processing unit for instructing the display device, a control unit for executing drawing processing of the display device using the processed rewrite data held in the second memory in accordance with an instruction from the rewrite processing unit, and the process A power controller that switches power supplied to the first memory to second power lower than the first power that enables access to the first memory after rewrite data is transferred to the second memory; Is provided.

FIG. 1 is a block diagram illustrating a schematic configuration of an information processing apparatus according to a first embodiment. FIG. 2 is a block diagram illustrating a schematic configuration of an EPD rewrite control unit according to the first embodiment. FIG. 3 is a block diagram illustrating a schematic configuration of a preprocessing unit according to the first embodiment. FIG. 4 is a diagram illustrating a configuration example of a preprocessing cache according to the first embodiment. FIG. 5 is a flowchart illustrating an example of a rewriting process according to the first embodiment. FIG. 6 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the second embodiment. FIG. 7 is a block diagram illustrating an example of an EPD rewrite control unit according to the second embodiment. FIG. 8 is a flowchart illustrating an example of a rewrite process according to the second embodiment. FIG. 9 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the third embodiment. FIG. 10 is a flowchart illustrating an example of a rewrite process according to the third embodiment. FIG. 11 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the fourth embodiment. FIG. 12 is a flowchart illustrating an example of a rewriting process according to the fourth embodiment. FIG. 13 is a diagram for explaining an outline of preloading according to the fifth embodiment. FIG. 14 is a flowchart illustrating an example of a processing flow according to the fifth embodiment. FIG. 15 is a timing chart of preprocessing and drawing processing according to the fifth embodiment. FIG. 16 is a timing chart of an operation example during hibernation according to the sixth embodiment. FIG. 17 is a flowchart of a processing flow during hibernation according to the sixth embodiment. FIG. 18 is a diagram illustrating a case where rewriting processing is performed by adding hint information according to the seventh embodiment. FIG. 19 is a diagram illustrating a case where the rewriting process according to the seventh embodiment is performed. FIG. 20 is a diagram showing a cache entry of a preprocessing cache according to the seventh embodiment. FIG. 21 is a flowchart illustrating an example of a processing flow according to the seventh embodiment. FIG. 22 is a flowchart illustrating an example of a rewrite process according to the seventh embodiment. FIG. 23 is a diagram showing an image viewer application according to the eighth embodiment. FIG. 24 is a timing chart showing two rewrite processes according to the eighth embodiment. FIG. 25 is a block diagram illustrating a schematic configuration example of a cloud system according to the tenth embodiment. FIG. 26 is a flowchart of the processing flow of the cloud system according to the tenth embodiment. FIG. 27 is a diagram for explaining the outline of the rewriting process according to the eleventh embodiment. FIG. 28 is a diagram showing an outline of rewriting processing when the moving direction of the knob is changed in FIG. FIG. 29 is a block diagram illustrating a schematic configuration of an information processing apparatus according to a twelfth embodiment. FIG. 30 is a diagram showing a configuration of a preprocessing cache according to the twelfth embodiment. FIG. 31 is a flowchart illustrating an example of a rewrite process according to the twelfth embodiment. FIG. 32 is a block diagram illustrating a schematic configuration of an information processing apparatus according to a thirteenth embodiment. FIG. 33 is a diagram illustrating a configuration example of a preprocessing cache according to the fourteenth embodiment.

  Hereinafter, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to exemplary embodiments will be described in detail with reference to the accompanying drawings.

  For example, in rewrite data processing (for example, data conversion processing, which is executed by the data conversion processing unit 113a of the preprocessing unit 113), image data is displayed so that color image data can be displayed on grayscale electronic paper. Processing to convert data to grayscale or black and white (binary) image data, processing to invert black and white image data to black and white, display size of electronic paper, and size of rewriting area when electronic paper is partially rewritten A process of enlarging or reducing the image data is performed in accordance with the above.

  In addition, in the rewrite control information selection process (for example, the selection process, which is executed by the selection processing unit 113b of the preprocessing unit 113), it is possible to perform the intended rewriting process without consuming unnecessary power and time. In order to select appropriate rewrite control information, it is necessary to perform data analysis of rewrite data. This selection process is a very important process because if the appropriate rewrite control information cannot be selected, the load on the information processing apparatus increases.

  Rewrite control information refers to how to apply voltage to rewrite each pixel or set of electronic paper to a desired grayscale value, or to rewrite each pixel to a desired color in the case of electronic paper capable of color display. Is described information, and is called Waveform or the like. The rewrite control information may include information such as the voltage value, the time for applying the voltage, and the order in which the pair is applied while being changed.

  A plurality of rewrite control information is prepared on the information processing apparatus, and it is necessary to appropriately use them according to the rewriting method of the electronic paper. For example, the number of gradation levels of the image data to be rewritten, the characteristics of the image obtained by analyzing the histogram, and the difference in the rewriting method (for example, an afterimage in which the rewriting speed is slow but the characters before rewriting remain before rewriting). Rewriting method with few rewriting methods or rewriting speed is fast, but afterimages are likely to remain, or rewriting method is slow but rewriting process makes it difficult to see a color different from the desired color. It is necessary to select and use one that matches the purpose from a plurality of rewrite control information according to the difference in ambient temperature, etc. For this reason, rewriting processing is often performed by using different rewriting control information for the same rewriting data depending on the situation.

  Drawing processing on electronic paper can be performed by performing the preprocessing as described above to generate a pair of preprocessed rewritten data and rewrite control information selection information. As described above, this pre-processing requires relatively large power consumption and processing time. Also, in color electronic paper, etc., the rewrite control information becomes complicated, such as a complicated sequence for applying voltage while changing the voltage value, or a complicated rewrite sequence due to the color arrangement of the rewrite data. There is. In this case, the selection process in the pre-processing may further complicate the process required for image analysis and feature extraction, and as a result, power consumption and processing time may be further increased.

  Therefore, in the following embodiments, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof that can reduce power consumption and processing time required for preprocessing for electronic paper are provided. Illustrate.

(Embodiment 1)
First, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to the first embodiment will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the first embodiment. As shown in FIG. 1, the information processing apparatus 1 includes a SoC (System On a Chip) 100, a main memory 120, an EPD 140 as a display device having a memory property, power supply control devices 150A and 150B, and an input device 130. Is done.

  The display device 140 having the memory property is, for example, an electronic paper display (EPD). The electronic paper method may be various methods such as an electrophoresis method, an electronic powder fluid method, and a cholesteric liquid crystal method.

  The input device 130 includes a touch panel that functions as a pointing device provided on the surface of the EPD 140. Note that the information processing apparatus 1 may include other input devices such as a keyboard and a mouse.

  The main memory 120 is a non-volatile memory such as an MRAM (Magnetorogenic Random Access Memory). On the main memory 120, rewrite data to be displayed on the EPD 140 and one or more rewrite control information that are candidates for selection in the pre-processing are stored. In the first embodiment, the preprocessed rewrite data obtained by the processing in the preprocess and the rewrite control information selection ID (rewrite control information selection ID generated by the selection process in the preprocess) are, for example, rewrite control. A pre-processing cache composed of a pair with an information identifier (the same applies to the following embodiments) is also stored on the main memory 120.

  The power control device 150A supplies power to the main memory 120 and the SoC 100, and the power control device 150B supplies power to the EPD 140. The power supply control devices 150A and 150B are each PMIC (Power Management Integrated Circuit) or the like.

  The information processing apparatus 1 may include a solar cell and a power storage unit such as a capacitor, and may operate using electric power generated by the solar cell. In that case, the power storage unit stores the surplus power generated by the solar cell during idling or the like. The power supply control devices 150A and 150B supply power to each unit of the information processing device 1 so that peak power consumption during active time and the like is covered by both the power stored in the power storage unit and the power generated by the solar cell. Perform power control. As described above, the embodiment exemplified below is one of the objects to enable the information processing apparatus to operate with very little power. The basic policy for this purpose is to reduce power consumption by actively transitioning each module of the information processing apparatus to a standby state or a low power consumption mode with low power consumption. Therefore, only the power reduction required for the preprocessing itself is not important. If the pre-processing time is long, the power consumption will be reduced by actively transitioning to a low power consumption standby state when the information processing device is idle (when waiting for a response from the user or when the information processing device is not used). In this case, the time when active (when the information processing apparatus performs some processing) becomes long, and it is difficult to obtain the effect. In addition, if the processing time for the preprocessing is long, the responsiveness of the information processing apparatus is also affected, so that the usability of the information processing apparatus user is greatly impaired. Therefore, it is very important to reduce the processing time of the preprocessing. The same applies to the following embodiments.

  The SoC 100 includes a communication interface such as a CPU (Central Processing Unit) 101, a memory controller 103, an EPD controller 105, a pre-processing accelerator 102 used for pre-processing, an internal memory 104, and a wireless LAN controller 106. They are connected by a bus 107.

  The SoC 100 may provide a plurality of types of standby states in which the power consumption in the standby state and the cost required for transition to and return from the standby state are different so that the power consumption is low.

  The EPD controller 105 uses the main memory 120 as a working memory, reads the preprocessed rewrite data and the rewrite control information corresponding to the rewrite control information selection ID from the main memory 120, and executes the drawing process for the EPD 140. To do. The EPD controller 105 can update a plurality of partial areas of the EPD 140 in parallel.

  FIG. 2 is a block diagram illustrating a schematic configuration of the EPD rewrite control unit according to the first embodiment. As shown in FIG. 2, the EPD rewrite control unit 110 is a device driver of an EPD controller 105 of an operating system (hereinafter referred to as OS) operating on the CPU 101. The EPD rewrite control unit 110 includes a power management unit 115, a preprocessing unit 113, a cache determination unit 112, a rewrite processing unit 114, and a cache management unit 111 (also referred to as a management unit). As shown in FIG. 4, the pre-processing unit 113 includes a data conversion processing unit 113a and a selection processing unit 113b.

  When the EPD rewrite control unit 110 is instructed to rewrite a partial area or the whole of the EPD 140 by an application, middleware, OS, or the like operating on the information processing apparatus 1, the power management unit 115, the preprocessing unit 113, By operating the cache determination unit 112, the rewrite processing unit 114, and the cache management unit 111 in cooperation, the result of the preprocessing of the rewrite processing using the same rewrite control information with the same rewrite data is stored in the preprocess cache on the main memory 120. Whether or not a cache hit occurs is checked. If there is a cache hit, the drawing processing of the EPD 140 is performed by reusing data in the preprocessing cache. Thereby, it is possible to reduce power consumption and processing time required for preprocessing. Further, by reducing the time required for preprocessing (hereinafter referred to as preprocessing time), it is possible to lengthen the time during which the main memory 120 composed of MRAM can be turned off, thereby further reducing power consumption. Can be reduced.

  Furthermore, generally, when the SoC 100 is shifted to a standby state with lower power consumption, more power consumption and processing time are required to recover from the standby state. Therefore, in order to reduce the total power consumption, an idle time corresponding to the power consumption required for returning from the standby state is required. Therefore, in the first embodiment, as described above, it is possible to reduce the preprocessing time, so that it is possible to increase the opportunity to use the standby state in which the idle time is longer and the power consumption is low, and as a result. Further power saving can be achieved.

  FIG. 4 is a diagram showing a configuration example of a preprocessing cache held on the main memory of FIG. This preprocessing cache is managed by the cache management unit 111 of the EPD rewrite control unit 110 shown in FIG.

  As shown in FIG. 4, the preprocessing cache includes a plurality of cache entries. In the example of FIG. 4, six cache entries are registered as the preprocessing cache. Each cache entry is composed of a pair of a tag part and a preprocess cache data part.

  The tag part is composed of a pair of a rewrite data ID and a rewrite method tag, and a VALID bit. An EPD rewrite request issued by an application, middleware, or the like is issued with a pair of a rewrite data ID for distinguishing rewrite data and a rewrite method tag indicating what rewrite is performed. The cache determination unit 112 that has received such a rewrite request determines a cache hit. In the cache hit determination, by searching the tag portion, the pair of the rewrite data ID and the rewrite method tag matches, and the VALID bit indicating whether the data of the cache entry is valid (VALID) or invalid (INVALID) is valid. It is determined whether there is an entry with (VALID).

  The rewrite data ID is information for uniquely identifying the rewrite data. For example, the application or middleware manages the rewrite data and the rewrite data ID in association with each other, and when rewriting using the same rewrite data, the same rewrite data ID is added to the rewrite request and notified to the EPD rewrite control unit 110. In the example shown in FIG. 4, there are four types of rewrite data “1” to “4”.

  The rewrite method tag is information added to the rewrite request in order to specify the rewrite method. In the rewrite method tag, for example, the data is binarized and rewritten, the binarized data is further reversed and rewritten, the rewriting that the afterimage is difficult to remain in gray scale, the rewriting speed is Rewriting that is fast but an afterimage remains, and a combination of two or more of them is designated. In the example shown in FIG. 4, for rewrite data with rewrite data IDs “1” and “2”, two rewrite methods “B” and “W” are designated in the past and entered in the preprocessing cache. For rewrite data with rewrite data IDs “3” and “4”, one rewrite method of “G” is designated in the past and entered in the preprocessing cache.

  The rewriting method “B” is, for example, rewriting the rewritten data by binarizing. The rewriting method “W” is, for example, binarizing the rewritten data and further reversing the black and white. The rewriting method “G” is, for example, The rewriting data is converted to gray scale. In the rewriting method 'G' for converting to gray scale, when rewriting data is analyzed as having 8 gradations, rewriting control information to be rewritten with 8 gradations is selected. In that case, it is not necessary to use rewrite control information in 16 gradations, and an image quality equivalent to 16 gradations can be obtained with a short rewriting time and low power consumption.

  Note that an EPD 140 rewrite request issued by an application, middleware, or the like includes an ID for uniquely identifying a rewrite data ID / rewrite method tag pair instead of a rewrite data ID / rewrite method tag pair. May be added. For example, in the case of FIG. 4, the ID of <1, B> is '1', the ID of <1, W> is '2', the ID of <2, B> is '3', and the ID of <2, W> is The ID of “4”, <3, G> may be “5”, and the ID of <4, G> may be “6”. In this case, <rewrite data ID, rewrite method tag> in the tag portion stores an ID for identifying a pair instead. The same applies to all the following embodiments.

  The preprocess cache data part is composed of a pair of a rewrite control information selection ID and preprocessed rewrite data.

  The rewrite control information selection ID is information for specifying any one of a plurality of rewrite control information held by the information processing apparatus 1. When the rewrite processing unit 114 instructs the EPD controller 105 to execute the rewrite process of the EPD 140 using the entry whose rewrite control information selection ID is “34” in FIG. 4, the EPD controller 105 stores the main memory 120. The 34th rewrite control information arranged above is read, and rewrite processing is executed using this rewrite control information.

  The preprocessed rewrite data stores the data size in addition to the content data (contents) of the preprocessed rewrite data.

  FIG. 5 is a flowchart illustrating an example of the rewriting process according to the first embodiment. In the example illustrated in FIG. 5, an example is shown in which the EPD rewrite control unit 110 reuses data on the preprocessing cache to save power and speed up the rewrite process. In the processing shown in FIG. 5, a rewrite request is issued from the application, middleware, OS, or the like to the EPD rewrite control unit 110 so that the EPD 140 is rewritten using rewrite data arranged in a frame buffer or the like on the main memory 120. And started.

  As shown in FIG. 5, in the rewrite process, when the EPD rewrite control unit 110 receives a rewrite request, the power management unit 115 of the EPD rewrite control unit 110 turns on the power of the main memory 120 for active power saving. It is confirmed whether or not it is turned off (step S101). If it is turned off (step S101; YES), the main memory 120 is turned on using the power control device 150A (step S102). Proceed to step S103. As a result, the main memory 120 can be accessed. Since the main memory 120 is a non-volatile memory such as an MRAM, the contents of the preprocessing cache configured on the main memory 120 are retained. On the other hand, if the main memory 120 is powered on (step S101; NO), the EPD rewrite control unit 110 proceeds to step S103 as it is.

  In step S103, the cache determination unit 112 of the EPD rewrite control unit 110 checks whether or not a prematch cache exists that matches the rewrite data ID and rewrite method tag pair added to the rewrite request ( If the cache is hit (step S103; YES), the process proceeds to step S107. On the other hand, when no cache hit occurs (step S103; NO), the cache management unit 111 of the EPD rewrite control unit 110 determines a cache entry for storing the preprocessing result (step S104). At this time, if the cache entry is full, the cache entry is determined using an algorithm for determining a cache entry to be replaced, such as LRU (Least Recently Used). Subsequently, the preprocessing unit 113 of the EPD rewrite control unit 110 instructs the preprocessing accelerator 102 to perform preprocessing (step S105).

  In response to an instruction from the preprocessing unit 113, the preprocessing accelerator 102 performs preprocessing including the above-described processing and selection processing based on the rewrite data on the main memory 120. Thereafter, the preprocessing accelerator 102 writes the processed rewrite data as the result of the preprocessing back to the determined cache entry (step S106). Further, the cache management unit 111 stores the rewrite control information selection ID, which is another result of the preprocessing, in the cache entry (step S106). At this time, the cache management unit 111 also stores the information of the rewrite data ID, the rewrite method tag, and the VALID bit (VALID) of the tag unit in the cache entry (step S106). Thereafter, the EPD rewrite control unit 110 proceeds to step S107.

  In step S107, the rewrite processing unit 114 of the EPD rewrite control unit 110 requests the EPD controller 105 to perform drawing processing on the EPD 140 using data stored in the preprocessing cache (step S107). On the other hand, the EPD controller 105 reads the rewrite control information corresponding to the rewrite control information selection ID stored in the preprocess cache from the main memory 120, and reads the preprocessed rewrite data stored in the cache. Read and execute drawing processing on the EPD 140 (step S108). Thereafter, the EPD rewrite control unit 110 waits until the rewrite process is completed (step S109; NO). When the end of the rewriting process is notified by an interrupt or the like (step S109; YES), the power management unit 115 of the EPD rewriting control unit 110 turns off the main memory 120 using the power control device 150A (step S109; YES). Step S110). Thereby, power consumption is reduced. Thereafter, the EPD rewrite control unit 110 ends this operation.

  As described above, memory access to the main memory 120 can be significantly reduced by holding the preprocessing result as a preprocessing cache. As a result, power consumption and processing time can be greatly reduced.

  In the first embodiment, the rewrite control information selection ID which is one of the preprocessing results is stored in the preprocessing cache. However, the rewrite control information itself is stored in the preprocessing cache instead of the rewrite control information selection ID. May be. In that case, the process of reading the rewrite control information from the rewrite control information selection ID enters before the process of storing the preprocessing result in the cache entry (step S106). The same applies to the following embodiments.

  In the first embodiment, the main memory 120 is a non-volatile memory. However, the present invention is not limited to this, and the main memory 120 may be a memory such as a volatile DRAM. In that case, during idle time when drawing processing to the EPD 140 is not performed, consumption is performed while holding data such as a DRAM self-refresh mode so that data on the preprocessing cache can be held while reducing power consumption. The DRAM controller may be set to use a power saving mode that can reduce power. The same applies to the following embodiments.

  At the time of idling after completion of the drawing process on the EPD 140, the power supply control device 150B may be instructed to stop power supply to the EPD 140, and the power supply control device 150B itself may be set to be in the low power consumption mode. Further, power gating of the SoC 100 module such as the EPD controller 105 may be performed, or the clock supply may be stopped. The same applies to the following embodiments. Note that this configuration can be applied even to a configuration that does not include the preprocessing accelerator 102.

  In the first embodiment, the preprocessing accelerator 102 performs the preprocessing. However, the present invention is not limited to this, and the CPU 101 or the EPD controller 105 may perform the processing, or the processing may be divided and executed. The same applies to the following embodiments.

  The processing for storing the pre-processing cache entry is not limited to the above method, and the pre-processing accelerator 102 may perform all of the processing, or the CPU 101 and the pre-processing accelerator 102 may share the processing. Good. The same applies to the following embodiments.

  In the first embodiment, the EPD controller 105 is built in the SoC 100. However, the invention is not limited to this, and an EPD controller external to the SoC 100 may be used.

  FIG. 4 shows an example of the configuration of the cache entry of the preprocessing cache, and is not limited to this configuration. Since the display area of the EPD 140 can be partially rewritten, there is a case where the size of the preprocessed rewritten data cached in the preprocessed cache data section differs for each entry.

  Specifically, the rewrite data includes, for example, data indicating the page number of the currently displayed page from the one having a large data size such as data for one page of the electronic book application, or the application of the information processing apparatus 1. There are even small data sizes such as software buttons displayed on the EPD 140 for the user to point on the touch panel, and image data of each selection item in the user interface such as a menu or list. Therefore, in the area for storing the preprocessed rewritten data in each entry of FIG. 4, a pointer such as C language or address information to another area may be stored instead of the preprocessed rewritten data. In this case, the area where the preprocessed rewritten data is actually stored is another area indicated by the pointer or address information. By utilizing the characteristics of the EPD 140 that is partially rewritten, the preprocessing cache does not need to hold the preprocessed rewritten data of the entire screen, and can hold the partial preprocessed rewritten data to be rewritten. You can rewrite the screen with just that. This is one of the important features of the EPD preprocessing cache. The same applies to the following embodiments.

  In the first embodiment, rewriting of an image with a small data size such as a button displayed on the EPD 140 as a user interface is also cached by preprocessing. According to this configuration, due to the characteristics of the EPD 140 and the EPD controller 105, the EPD controller 105 performs processing after the rewriting time (the EPD controller 105 starts the actual rewriting process) according to the data size of rewriting data (hereinafter referred to as the rewriting size). When the information processing apparatus 1 is shifted to a standby state with low power consumption after the rewriting is completed to reduce power consumption, the rewrite size is small and the effect at first glance is not effective. Even if it is small, the same power saving effect as when the rewrite size is large can be obtained. For this reason, it is extremely important that rewriting with a small data size is cached in the preprocessing cache. Further, the button or each key of the software keyboard has a great influence on the user of responsiveness, and the convenience given to the user can be improved.

  In the first embodiment, with respect to the rewritten data that has been preprocessed once, the preprocess result is held in the preprocess cache. However, the present invention is not limited to this. For example, a home screen, menu or list when the information processing apparatus 1 is activated, images of key buttons of the software keyboard, software components that can be shared by one or more applications, etc. are used relatively frequently in advance. For known rewrite data, preprocessing may be performed in advance, and the result of the preprocessing may be stored in the information processing apparatus 1 in advance. Note that the advance may be at the time of shipment, installation, software update, or the like. The pre-processing result stored in advance is stored in the pre-processing cache when the information processing apparatus 1 is started, when cold booting, when starting an application, or the like. As a result, regarding specific rewrite data, it is possible to reduce power consumption when performing rewrite processing first. The same applies to the following embodiments.

  In the first embodiment, the power control device 150A supplies power to the main memory 120 and the SoC 100, and the power control device 150B supplies power to the EPD 140. However, the present invention is not limited to this. For example, the power supply control device 150A may supply power to the main memory 120, the SoC 100, and the EPD 140. The same applies to the following embodiments.

  In the first embodiment, the processing in the preprocessing may include processing for creating rewrite data itself using an accelerator such as a GPU or the CPU 101, such as PDF data or rendering processing in a web browser. The same applies to the following embodiments.

(Embodiment 2)
Next, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to the second embodiment will be described in detail with reference to the drawings. In the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  FIG. 6 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the second embodiment. As illustrated in FIG. 6, the information processing apparatus 2 includes a SoC 200, a main memory 120, an EPD 140, an EPD controller 210, an EPD dedicated memory 220, a power supply control device 150 </ b> A, a power supply control device 150 </ b> B, and an input device 130. As described above, the information processing apparatus 2 has the same configuration as the information processing apparatus 1 according to the first embodiment. The EPD controller 210 is externally attached to the SoC 200, and the EPD stores rewrite processing data in the EPD controller 210. It has a configuration in which a dedicated memory 220 is provided.

  The power supply control device 150B supplies power to the EPD controller 210 and the EPD dedicated memory 220 in addition to the EPD 140. The power supply to the EPD controller 210 or the like may be performed by the power supply control device 150A that supplies power to the main memory 120, the SoC 200, or the like.

  The main memory 120 is a non-volatile memory such as an MRAM as in the first embodiment. On the main memory 120, rewrite data to be displayed on the EPD 140 is stored. The rewritten data is transferred to the EPD dedicated memory 220 before executing the rewriting process.

  The EPD dedicated memory 220 may be a nonvolatile memory such as an MRAM. The EPD dedicated memory 220 can be used as a working memory by the EPD controller 210.

  The SoC 200 includes a bus 107, a CPU 101, a memory controller 103, a wireless LAN controller 106, and the like. Further, the SoC 200 may include the preprocessing accelerator 102 as in the first embodiment.

  In the second embodiment, unlike the first embodiment, the EPD controller 210 executes preprocessing and drawing processing. That is, in the second embodiment, the EPD controller 210 realizes an EPD rewrite control unit. The EPD controller 210 includes an internal memory 211 such as a nonvolatile MRAM. The internal memory 211 stores a preprocessing cache configured by a pair of preprocessed rewrite data and a rewrite control information selection ID. The rewrite control information may be placed on the internal memory 211.

  The basic configuration of the EPD rewrite control unit according to the second embodiment is the same as that of the EPD rewrite control unit 110 (see FIG. 2) according to the first embodiment. FIG. 7 shows an example of the EPD rewrite control unit 110 in the EPD controller 210. When the EPD rewrite control unit 110 receives a rewrite request for rewriting a partial area or the whole of the EPD 140 from an application, middleware, OS, or the like operating on the information processing apparatus 2, the EPD rewrite control unit 110 uses the same rewrite control information with the same rewrite data It is checked whether or not the result of the preprocessing of the rewriting process causes a cache hit in the preprocessing cache configured on the internal memory 211 of the EPD controller 210. If there is a cache hit, the data in the preprocessing cache is reused. Thus, the EPD drawing unit 213 is instructed to rewrite the EPD 140. As a result, it is possible to reduce power consumption and processing time required for preprocessing. Further, by omitting the preprocessing, the power of the EPD dedicated memory 220 can be kept off, so that the power saving effect can be obtained. The configuration of the preprocessing cache held on the internal memory 211 of the EPD controller 210 is the same as that of the preprocessing cache (see FIG. 4) exemplified in the first embodiment.

  FIG. 8 is a flowchart illustrating an example of the rewriting process according to the second embodiment. The operation shown in FIG. 8 is performed when a rewrite request is issued from the application, middleware, OS, or the like to the device driver of the EPD controller 210 so that the EPD 140 is rewritten with the rewrite data on the main memory 120. When power supply to the EPD controller 210, the EPD dedicated memory 220, and the main memory 120 is stopped for the purpose of the conversion, the EPD controller 210 and the EPD are connected to the power control devices 150B and 150A by the device driver of the EPD controller 210 or the like. An instruction to resume power supply to the dedicated memory 220 and the main memory 120 is given, and after rewriting data is transferred from the main memory 120 to the EPD dedicated memory 220, the process is started by an instruction from the device driver of the EPD controller 210. If the data already exists in the EPD dedicated memory 220, data transfer is not necessary, no power supply to the main memory 120 is necessary, and no power supply to the EPD dedicated memory 220 is necessary at this time. The power supply control device 150A may be instructed to stop power supply to the main memory 120 after being transferred to the EPD dedicated memory 220. Note that the internal memory 211 on the EPD controller 210 is a non-volatile memory such as an MRAM, so that the contents of the preprocessing cache configured on the internal memory 211 are retained.

  As shown in FIG. 8, in the rewriting process, when the rewriting request is received and the power supply to the EPD controller 210 is resumed, the cache determination unit 112 of the EPD rewriting control unit 110 adds the rewriting data added to the rewriting request. It is checked (cache determination) whether or not a matching ID / rewrite method tag pair exists in the preprocessing cache (step S201). If a cache hit occurs (step S201; YES), the process proceeds to step S210. On the other hand, when there is no cache hit (step S201; NO), the power management unit 115 of the EPD rewrite control unit 110 checks whether the power of the EPD dedicated memory 220 is turned off for active power saving. If it is off (step S202; YES), the power of the EPD dedicated memory 220 is turned on using the power supply control device 150B (step S203), and the process proceeds to step S206. As a result, the EPD dedicated memory 220 can be accessed. On the other hand, if the EPD dedicated memory 220 is powered on (step S202; NO), the EPD rewrite control unit 110 proceeds directly to step S206.

  In step S206, the cache management unit 111 of the EPD rewrite control unit 110 determines a cache entry for storing the preprocessing result (step S206). At this time, if the cache entry is full, the cache entry is determined using an algorithm for determining a cache entry to be replaced, such as LRU. Subsequently, the data conversion processing unit 113a and the selection processing unit 113b of the preprocessing unit 113 of the EPD rewrite control unit 110 perform preprocessing (step S207), and preprocessed rewritten data as a result of this preprocessing is obtained. The determined cache entry is written (step S208). Further, the cache management unit 111 stores the rewrite control information selection ID, which is another result of the preprocessing, in the cache entry (step S208). At this time, the cache management unit 111 also stores information on the rewrite data ID, the rewrite method tag, and the VALID bit (VALID) of the tag unit in the cache entry (step S208). When the preprocessing accelerator 102 is provided, the preprocessing unit 113 may issue a preprocessing instruction to the preprocessing accelerator 102 and the preprocessing accelerator 102 may execute the preprocessing.

  Next, the power management unit 115 of the EPD rewrite control unit 110 turns off the power of the EPD dedicated memory 220 that has been used (step S209), and the process proceeds to step S210.

  In step S210, the rewrite processing unit 114 of the EPD rewrite control unit 110 performs drawing processing on the EPD 140 using data stored in the preprocessing cache (step S210). Thereafter, the EPD rewrite control unit 110 waits until the rewrite process is completed (step S211; NO). When the end of the rewriting process is notified by interruption or the like (step S211; YES), the power management unit 115 of the EPD rewriting control unit 110 turns off the power of the EPD 140 and the EPD controller 210 using the power control device 150B. (Step S212). Thereby, power consumption is reduced. Since the internal memory 211 is a non-volatile memory, the data cached in the internal memory 211 is retained even when the EPD controller 210 is turned off. Further, since the EPD 140 is a non-volatile display, the image drawn on the EPD 140 is continuously held. Thereafter, the EPD rewrite control unit 110 ends this operation.

  As described above, the memory access to the EPD dedicated memory 220 can be greatly reduced by holding the preprocess result as the preprocess cache. As a result, power consumption and processing time can be greatly reduced.

  In the second embodiment, the preprocessing cache is held in the internal memory 211 of the EPD controller 210. However, the preprocessing cache may be held in the EPD dedicated memory 220 or in both the internal memory 211 and the EPD dedicated memory 220. It may be held. At that time, the pre-processing cache that is frequently used may be stored in the internal memory 211. In the second embodiment, the entire rewrite control information is held in the internal memory 211, but all or a part of the rewrite control information may be held in the EPD dedicated memory 220. At this time, the internal memory 211 may store frequently used rewrite control information. The same applies to the following embodiments.

  In the second embodiment, in addition to the main memory 120, the EPD dedicated memory 220 and the internal memory 211 of the EPD controller 210 are non-volatile memories. However, the present invention is not limited thereto, and the EPD dedicated memory 220 and the internal memory of the EPD controller 210 are not limited thereto. 211 may be a volatile memory. In that case, while the data such as the drawing process to the EPD 140 is not performed, the data in the self-refresh mode of the DRAM is held so that the data on the preprocessing cache can be held while reducing the power consumption. A power saving mode that can reduce power consumption may be used, or power may be supplied only to the internal memory 211 of the EPD controller 210. The same applies to the following embodiments.

  Further, as described above, not only the configuration in which the EPD controller 210 is externally attached to the SoC 200, but also the EPD controller 105 of the SoC 100 of the first embodiment may operate in the same manner as the EPD controller 210 of the second embodiment. Can be configured. In that case, the EPD controller 105 may include the internal memory 211, or the internal memory 104 may be used instead of the internal memory 211.

  In addition, as shown in the example, the size of the cached data of the preprocessed rewritten data in the preprocessed cache data portion is often different for each entry because of the property that the EPD 140 can partially update the display. Therefore, the area for storing the preprocessed rewritten data of each cache entry in FIG. 4 may be configured to include address information for another area for actually storing data. The same applies to the following embodiments.

(Embodiment 3)
Next, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to the third embodiment will be described in detail with reference to the drawings. In the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  The information processing apparatus according to the third embodiment may have the same configuration as the information processing apparatus 1 according to the first embodiment (see FIG. 1), for example. However, in the third embodiment, the preprocessing cache is configured in the nonvolatile internal memory 104 provided in the SoC 100. By disposing the preprocessing cache in the internal memory 104 of the SoC 100, it is not necessary to access the main memory 120 using the nonvolatile memory in the case of a cache hit. Therefore, the EPD 140 can be rewritten while the main memory 120 is turned off. Is possible. As a result, the power-off time of the main memory 120 can be lengthened and further power saving can be achieved. Further, since the internal memory 104 of the SoC 100 is on-chip, it can be accessed faster than the main memory 120. Thereby, the processing time of the rewriting process can be shortened, and as a result, the power consumption and the processing time can be further reduced.

  The SoC 100 according to the third embodiment receives an interrupt from the input device 130 such as a button or key specialized for a specific process attached to the touch panel, the keyboard, or the information processing apparatus 2 in a standby state with low power consumption. Can do.

  The internal memory 104 is a non-volatile memory such as an MRAM. In the third embodiment, the internal memory 104 stores a preprocessing cache configured by a pair of preprocessed rewritten data and a rewrite control information selection ID. The basic configuration of the preprocessing cache may be the same as that of the preprocessing cache shown in FIG. Rewrite control information is also placed on the internal memory 104. Furthermore, an interrupt vector table and an EPD rewrite interrupt handler for requesting rewrite to the device driver of the EPD controller 210 for rewrite processing stored in the interrupt vector table are also arranged on the internal memory 104. Similar to the first embodiment, rewrite data to be displayed on the EPD 140 is stored on the main memory 120.

  The basic configuration of the EPD rewrite control unit according to the third embodiment is the same as that of the EPD rewrite control unit 110 according to the first embodiment shown in FIG. The cache determination unit 112 is arranged on the internal memory 104 by the processing of the EPD rewrite interrupt handler. The pre-processing unit 113, the rewrite processing unit 114, the cache management unit 111, and the power management unit 115 are part of the device driver processing of the EPD controller 210 and are arranged on the internal memory 104. Some of these configurations may be arranged on the main memory 120.

  FIG. 9 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the third embodiment. As shown in FIG. 9, the information processing apparatus 3 is provided with, for example, a BACK key 301, a SELECT key 302, and a NEXT key 303. The EPD 140 of the information processing apparatus 3 displays a menu 340 having three selection items by software. In the third embodiment, the rewrite processing is performed by interrupting the SoC 100 when the user of the information processing device 3 inputs a keyboard key or a key specialized for a specific processing, thereby interrupting the EPD in the internal memory 104 Triggered when a handler starts. As a premise, the EPD rewrite interrupt handler is associated with a specific key, for example. For example, the EPD rewrite interrupt handler moves the focus of the selection items before and after the menu 340 displayed on the EPD 140 by the application, and displays the previous and next pages of the electronic book application. Assigned to each. The NEXT key 303 is associated with a specific rewrite data ID = 1000 reserved by an application, middleware, OS, or the like. Since there are three menu selection items, it is assumed that the EPD rewrite interrupt handler assigned to the NEXT key 303 has a state variable that can take a value from “0” to “2”. In this case, rewrite data IDs from 1000 to 1002 are reserved.

  FIG. 10 is a flowchart illustrating an example of the rewriting process according to the third embodiment. The operation shown in FIG. 10 makes it possible to save the power and speed up the rewriting process by reusing the data on the preprocessing cache, and is executed by the following procedure. That is, when an interrupt is generated for the SoC 100 when a keyboard key is input, a corresponding EPD rewrite interrupt handler is activated. In the EPD rewrite interrupt handler, the cache determination unit 112 uses a specific rewrite data ID (for example, number 1000) and a rewrite method tag set in advance for each key as they are, or the rewrite data ID. And the state variable is used as a base, and the result is used. The state variable indicates, for example, which selection item in the menu is focused (for example, if the third item is 2, 1000 + 2 = 1002). The calculation is a process for shifting the focus to the previous selection item by decrementing a specific rewrite data ID, for example, when a BACK key is interrupted (for example, 1002-1 = 1001). It is.

  In the operation illustrated in FIG. 10, whether or not the cache determination unit 112 of the EPD rewrite control unit 110 matches the pair of the obtained rewrite data ID (= 1001) and the rewrite method tag exists in the preprocessing cache. Is checked (cache determination) (step S301). If a cache hit occurs (step S301; YES), the process proceeds to step S310. On the other hand, when there is no cache hit (step S301; NO), the cache determination unit 112 notifies a key input event to an application or the like (step S302). Thereafter, the EPD rewrite control unit 110 waits until processing corresponding to the key input event is performed by the application and a rewrite request is received from the application (step S303; NO).

  A reserved rewrite data ID (1000 to 1002) is added to the rewrite request received from the application. Therefore, the cache determination unit 112 can determine that there is a cache miss without making a cache determination. Therefore, when a rewrite request is received from the application (step S303; YES), the cache management unit 111 of the EPD rewrite control unit 110 determines a cache entry for storing the preprocessing result (step S304). At this time, if the cache entry is full, the cache entry is determined using an algorithm for determining a cache entry to be replaced, such as LRU.

  Next, the power management unit 115 of the EPD rewrite control unit 110 checks whether or not the main memory 120 is turned off for active power saving (step S305), and is turned off. In the case (step S305; YES), the main memory 120 is turned on using the power supply control device 150A (step S306), and the process proceeds to step S307. As a result, the main memory 120 can be accessed. Since the main memory 120 is a non-volatile memory such as an MRAM, the contents of the preprocessing cache configured on the main memory 120 are retained. On the other hand, if the main memory 120 is powered on (step S305; NO), the EPD rewrite control unit 110 proceeds to step S307 as it is.

  In step S307, the cache determination result indicates that no cache hit was found in the preprocessing cache, so the preprocessing unit 113 of the EPD rewrite control unit 110 instructs the preprocessing accelerator 102 to perform preprocessing (step S307).

  In response to an instruction from the preprocessing unit 113, the preprocessing accelerator 102 performs preprocessing including the above-described processing and selection processing based on the rewrite data on the main memory 120. Thereafter, the preprocessing accelerator 102 writes the processed rewrite data, which is the result of the preprocessing, back to the determined cache entry (step S308). In addition, the cache management unit 111 also includes information on the rewrite control information selection ID, the rewrite data ID of the tag unit, the rewrite method tag, and the VALID bit (VALID), which is another result of the preprocessing. Store in the entry (step S308). Subsequently, the power management unit 115 of the EPD rewrite control unit 110 uses the power control device 150A to turn off the main memory 120 (step S309), and the process proceeds to step S310.

  In step S310, the rewrite processing unit 114 of the EPD rewrite control unit 110 requests the EPD controller 105 to perform drawing processing on the EPD 140 using data stored in the preprocessing cache (step S310). On the other hand, the EPD controller 105 reads the rewrite control information corresponding to the rewrite control information selection ID stored in the preprocess cache from the internal memory 104, and reads the preprocessed rewrite data stored in the cache. Reading is performed, and drawing processing on the EPD 140 is executed (step S311). Thereafter, the EPD rewrite control unit 110 ends this operation.

  In the third embodiment, since there is a premise that the cache determination unit 112 of the EPD rewrite interrupt handler determines a specific interrupt, the rewrite request with the reserved rewrite data ID issued in step S304. The determination result is fixed as a cache miss and the determination process is omitted, but the cache determination is also performed by another cache determination unit installed in the driver of the EPD controller 210 after the rewrite request is notified. Similarly to the first embodiment, preprocessing can be omitted for interrupts other than the above interrupts. As a result, further power saving and higher speed can be achieved.

  In addition, for example, a control device such as a microcontroller whose power is lower than that of the SoC 100 is between the input device 130 and the SoC 100, and the control device is supplied with power from a place different from the power supply control device 150A. If the SoC 100 and the power supply control device 150A can be controlled, the control device stops the power supply to the SoC 100 and performs hibernation to turn off the power supply control device 150A itself when idle after the rewrite processing in step S311. By doing so, it is possible to actively save power. In this case, since the internal memory 104 of the SoC 100 is a non-volatile memory, the contents of the preprocessing cache are retained even after the return process led by the control device. Therefore, the EPD 140 can be rewritten at high speed even after the return. When the internal memory 104 of the SoC 100 is a volatile memory such as SRAM, the preprocessing cache on the internal memory 104 may be saved in the nonvolatile main memory 120 to execute hibernation. Alternatively, only the internal memory 104 such as an SRAM may be energized and the power supply to the SoC 100 may be stopped. The same applies to the following embodiments.

  In the third embodiment, a specific EPD rewrite interrupt handler, rewrite data ID, and rewrite method tag are set in advance for the interrupt. However, the correspondence between these is dynamically changed when the application is started. Is possible.

  In the third embodiment, all the preprocessing caches are provided in the internal memory 104 of the SoC 100. However, it is not necessary to provide the whole in the internal memory 104, and a part thereof may be arranged in the main memory 120. In such a case, the power consumption and the processing speed are optimized by preferentially arranging cache entries that are frequently used on the internal memory 104 and suppressing the number of times the main memory 120 is turned on. be able to.

  In the third embodiment, the entire rewrite control information is stored in the internal memory 104, but a part of the rewrite control information may be stored in the main memory 120. At this time, the internal memory 104 may be used as a cache for frequently used rewrite control information.

  In the third embodiment, the EPD controller 210 is built in the SoC 100, but may be an external EPD controller 210.

  In addition, when the displayed contents are determined and used very frequently, such as a menu screen, the rewrite control information selection ID and the preprocessed rewrite data, which are the results of preprocessing, are stored in the internal memory 104. It may be stored in advance in the preprocessing cache. In this case, the processing in steps S302 to S309 in FIG. 10 can be skipped, so that a high power saving effect can be obtained. Note that “preliminary” may be when the application is started, when the information processing apparatus 3 is cold booted, when shipped, or the like.

(Embodiment 4)
Next, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to the fourth embodiment will be described in detail with reference to the drawings. In the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  In the same configuration as the information processing apparatus 2 (see FIG. 6) of the second embodiment in which the tag portion of the preprocessing cache is configured in the internal memory 104 of the EPD controller 210, the fourth embodiment is a control device that consumes less power than the SoC 200. , A configuration in which the SoC 200 is disposed between one or more input devices 130 such as a keyboard and a touch panel. The control device is supplied with power from a place different from the power supply control device 150A and the SoC 200, and can control the SoC 200 and the power supply control device 150A from the control device.

  When receiving a request for interrupt processing from a keyboard or the like, the control device determines whether or not a preprocessing cache for rewriting processing corresponding to the interrupt exists, and if a cache hit occurs, sends a rewriting request to the EPD controller 210. If it is directly transmitted and a cache miss occurs, an interrupt is transmitted to the SoC 200, and a rewrite request is issued from the SoC 200 as necessary. Therefore, when a cache hit occurs in the pre-processing cache, it is possible to perform a rewriting process with the minimum necessary configuration with the SoC 200 and the main memory 120 turned off, thereby significantly reducing power consumption. can do. For example, in the case of an electronic book application, when a new electronic book is opened, it operates with a configuration including the SoC 200 and the main memory 120. It is possible to operate with a minimum configuration that does not use the main memory 120.

  FIG. 11 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the fourth embodiment. As shown in FIG. 11, the information processing device 4 includes the SoC 200, the main memory 120, the EPD 140, the EPD dedicated memory 220, the power control device 150A, the power control device 150B, the power control device 450, the microcontroller 400, and one or more. Input device 130.

  The input device 130 is a keyboard, a touch panel, a network, or the like. The interrupt processing by these input devices 130 is not transmitted directly to the SoC 200, but is transmitted to the microcontroller 400 disposed between the SoC 200 and the SoC 200.

  The microcontroller 400 has lower power consumption than the SoC 200 and is always energized. The microcontroller 400 has an internal memory 401, and the tag portion of the preprocessing cache is held in the internal memory 401.

  In the fourth embodiment, as in the second embodiment, the EPD controller 210 performs preprocessing. The EPD controller 210 has an internal memory 211 such as a nonvolatile MRAM. The internal memory 211 also stores a preprocessing cache configured by a pair of preprocessed rewrite data and a rewrite control information selection ID. The tag portion of the preprocessing cache is also stored in the internal memory 211 of the EPD controller 210. Consistency is maintained between the tag part of the preprocessing cache held in the internal memory 211 of the EPD controller 210 and the tag part of the preprocessing cache held in the internal memory 401 of the microcontroller 400. Rewrite control information is also placed on the internal memory 211 of the EPD controller 210.

  The basic configuration of the EPD rewrite control unit is the same as that of the second embodiment. Also in the fourth embodiment, the EPD rewrite control unit 110 is a process in the EPD controller 210. However, a cache determination unit similar to the cache determination unit 112 is also mounted on the microcontroller 400. A power management unit that turns on / off the power of the SoC 200 may be mounted on the microcontroller 400. The configuration of the preprocessing cache held on the internal memory 211 of the EPD controller 210 is the same as the preprocessing cache (see FIG. 4) illustrated in the first embodiment.

  FIG. 12 is a flowchart illustrating an example of the rewriting process according to the fourth embodiment. The process shown in FIG. 12 is started when an interrupt is generated in the microcontroller 400 by the user of the information processing apparatus 4 performing keyboard key input or the like. As in the third embodiment, a specific rewrite data ID and rewrite method tag pair is assigned to a specific key of the keyboard in advance.

  As shown in FIG. 12, in the rewriting process, the cache determination unit 112 on the microcontroller 400 uses the tag part of the preprocessing cache on the internal memory 401 of the microcontroller 400, and the rewritten data ID notified at the time of interruption. Is checked (cache determination) whether there is a match with the pair of the rewrite method tag in the preprocessing cache (step S401), and if a cache hit occurs (step S401; YES), the power supply to the EPD controller 210 is turned on. The controller 150B is instructed to turn on the EPD controller 210 (step S414), and a rewrite request is transmitted to the EPD controller 210 (step S415), and the process proceeds to step S411. On the other hand, when there is no cache hit (step S401; NO), the cache determination unit 112 on the microcontroller 400 notifies the SoC 200 of an interrupt. Thereby, the key input event is notified to the application or the like (step S402), and processing corresponding to the key input event is executed by the application or the like as necessary. Thereafter, as a result, a rewrite request in which a pair of a rewrite data ID and a rewrite method tag is added is issued to the EPD controller 210. When notifying the interrupt to the SoC 200, if the power of the SoC 200 is off, the power management unit 115 of the microcontroller 400 turns on the power of the SoC 200 using the power control device 150A, and then notifies the interrupt. . Further, after a rewrite request is issued to the EPD controller 210 as a result of the process corresponding to the key input event, the SoC 200 may be shifted to a standby state with low power consumption, or the power management unit 115 on the microcontroller 400 May instruct the power supply to the SoC 200 to stop.

  Next, the power management unit 115, which is a process of the EPD controller 210, confirms whether the power of the EPD dedicated memory 220 is turned off for active power saving (step S404), and is turned off. If yes (step S404; YES), the power supply control device 150B is used to turn on the EPD dedicated memory 220 (step S405), and the process proceeds to step S406. As a result, the EPD dedicated memory 220 can be accessed. On the other hand, if the EPD dedicated memory 220 is powered on (step S404; NO), the EPD controller 210 proceeds directly to step S406.

  Next, the cache management unit 111, which is the process of the EPD controller 210, determines a cache entry using an algorithm for determining a cache entry to be replaced, such as LRU (step S406). Subsequently, the preprocessing unit 113, which is the process of the EPD controller 210, executes the preprocessing using the EPD dedicated memory 220 as a working memory (step S407), and writes the result of this preprocessing in the determined cache entry. (Step S408).

  Next, the power management unit 115, which is the process of the EPD controller 210, turns off the power of the EPD dedicated memory 220 using the power control device 150B (step S409). Next, the cache management unit 111 of the EPD controller 210 transmits information on the tag part of the preprocessing cache to the microcontroller 400, and executes a process of updating the tag part for synchronization on the microcontroller 400 side. Then, the tag portion held in the internal memory 401 of the microcontroller 400 is matched with the tag portion in the internal memory 211 of the EPD controller 210 (step S410), and the process proceeds to step S411. Thereby, consistency is maintained between the tag portion held in the internal memory 401 of the microcontroller 400 and the tag portion in the internal memory 211 of the EPD controller 210. Note that the process shown in step S410 may be executed via the SoC 200. Further, when the rewrite process to be cached is limited to a pair of a specific plurality of rewrite process rewrite data IDs and a rewrite method tag, and is previously set in the information processing apparatus 4, the process of step S410 is omitted. Is possible.

  In step S411, the rewrite processing unit 114, which is a process of the EPD controller 210, reads the rewrite control information corresponding to the rewrite control information selection ID stored in the preprocessing cache from the internal memory 211 and stores the rewrite control information stored in the cache. The processed rewrite data is read and a drawing process on the EPD 140 is performed (step S411). Thereafter, the EPD controller 210 waits until the rewriting process is completed (step S412; NO). When the end of the rewriting process is notified by interruption or the like (step S412; YES), the power management unit 115 on the microcontroller 400 turns off the power of the EPD controller 210 using the power control device 150B (step S412). S413). This process may be executed by the power management unit of the EPD controller 210. Thereby, the power consumption of the EPD controller 210 is also reduced. Since the internal memory 211 is a non-volatile memory, the data cached in the internal memory 211 is retained even when the EPD controller 210 is turned off. Thereafter, the EPD controller 210 ends this operation.

(Embodiment 5)
As a method for more efficiently implementing the above-described first to fourth embodiments, there is a method for performing preload on the preprocessing cache. Here, preloading means that preprocessing for rewriting data of rewriting processing that is likely to be executed in the future is executed first, and the result is registered in the preprocessing cache. In this way, when rewriting processing that is highly likely to be executed in the future is known, pre-processing is executed in advance on the target rewriting data before the actual rewriting request is issued, and the result is sent to the preprocessing cache. By performing preloading, data stored in the preprocessing cache can be used for the first rewrite request. As a result, the rewriting time can be shortened, so that the responsiveness of the information processing apparatus can be improved. In addition, by shortening the rewriting time, the time during which the power source of the SoC 200 and the memory can be turned off is increased, so that further power saving can be achieved.

  The preload of the preprocessing cache can be applied to any configuration of the first to fourth embodiments. Here, a description will be given on the assumption of Embodiment 3 in which the internal memory 104 of the SoC 200 is used as a cache.

  In addition, preloading of the preprocessing cache can be applied to various uses, for example, when the next selection item or the next page is rewritten in the above menu, list, or electronic book application, respectively. Here, an example of a Kana-Kanji conversion application is shown as an example.

  FIG. 13 is a diagram for explaining an outline of preloading in the Kana-Kanji conversion application. The Kana-Kanji conversion application, for example, when a user inputs a reading of a word to be input (for example, “Sho”) and presses a conversion key, a candidate called multiple dictionaries using a correspondence table called a dictionary and a kanji. (For example, “small”, “saving”, “small”) are displayed. Thereafter, when the conversion key is pressed by the user, the focus is sequentially switched to the next candidate. First, it is assumed that, for example, color original data exists as shown in FIG. When the user presses the conversion key once, three kanji candidates “small”, “saving” and “small” are displayed on the EPD 140 in black and white as shown in FIG. 13B. Specifically, in order from the left, “small” that is in focus is white (background is black and characters are white), and “no” and “small” that are not in focus are displayed in black. Next, when the user presses the conversion key once, as shown in FIG. 13C, the focus shifts to “saving”, “saving” is displayed in white, and “small” and “small” are black. It will be displayed without being displayed. Further, when the conversion key is pressed once, as shown in FIG. 13D, the focus shifts to “low” and is displayed in white, and “small” and “saving” are displayed in black. become.

  In order to display the state shown in FIG. 13B, the pre-processing for white “<small”, “W”> for “small”, and the black pre-processing for “saving” and “low” < A total of three preprocessings of “saving”, “B”> and <“low”, “B”> are executed. Further, in order to display the state of FIG. 13C from the state of FIG. 13B, the focus is shifted to <“small”, “B”> for further changing “small” to black. For this reason, a total of two pre-processing with <"saving" and "W"> is executed. Similarly, in order to display the state of FIG. 13 (d) from the state of FIG. 13 (c), it is necessary to rewrite the display of “saving” and “low”. ”,“ B ”> pre-processing cache can be reused, so the necessary pre-processing is one time << small>,“ B ”>.

  The user expects the focus to move at high speed each time the conversion key is pressed, but if preprocessing is performed each time the key is pressed, it takes time to move the focus, which may impair usability. . Furthermore, since the main memory 120 in which the original data is arranged is accessed each time, the main memory 120 cannot be repeatedly switched on and off, and the power cannot be turned off. There is a possibility that the advantage of being a non-volatile memory cannot be fully utilized.

  For this reason, <"small", "W">, <"saving", "W">, <"small", "W">, <"small", "B">, <"saving" ”,“ B ”> and <“ Less ”,“ B ”>, a total of six pre-processing is executed in advance and stored in the pre-processing cache configured in the internal memory 104 of the SoC 200, The focus can be moved at high speed. Further, since the main memory 120 needs to be turned on only once, power consumption can be reduced. However, if the processing time for performing the six preprocessings collectively affects the usability, the characteristic that the processing time of the drawing process of one EPD 140 is relatively long is used well, The entire processing time may be hidden in the drawing process.

  FIG. 14 is a flowchart illustrating an example of a processing flow of the application when pre-loading to the preprocessing cache with the Kana-Kanji conversion application. In the method shown in FIG. 14, the above six pre-processes are not executed at once. First, when a conversion key such as a keyboard is pressed by the user, <"small", "W">, <"saving", "B"> and the minimum necessary to display the state of FIG. Three rewrite requests of “<small” and “B”> are issued to the EPD rewrite control unit 110 (steps S501 to S503). On the other hand, the EPD controller 210 executes three preprocessing and drawing processing for these three rewrite requests in parallel. At this time, the EPD rewrite control unit 110 executes a process of caching in the preprocessing cache of the internal memory 104 of the SoC 200. While the drawing process of the EPD 140 is being executed, the Kana-Kanji conversion application performs the remaining three pre-processes necessary for displaying the state of FIG. 13C and the state of FIG. The EPD rewrite control unit 110 is instructed (step S504). As a result, the results of all six preprocessing are stored in the preprocessing cache. However, in step S504, drawing processing based on the three preprocessing results is not performed. After that, when the conversion key is pressed again by the user, the rewriting process necessary to display the state of FIG. 13C and the state of FIG. 13D is performed using the data in the preprocessing cache. . At that time, since access to the main memory 120 and pre-processing do not occur, power consumption can be suppressed, and focus can be switched at high speed.

  FIG. 15 shows an example of a timing chart of preprocessing and drawing processing when the processing flow shown in FIG. 14 is executed. FIG. 15A shows <"small", "W">, <"saving", "W">, <"small", "W">, <"small", "B">, <"saving" ”,“ B ”> and <“ Small ”,“ B ”>, a total of six pre-processing timing charts. FIG. 15B is a timing chart for displaying the state of FIG. , “W”>, <“saving”, “W”> and <“low”, “W”>.

  As can be seen from FIG. 15, after the three preprocessing (S1) for displaying the state of FIG. 13B is executed, three drawing processes (S11) using the results of these preprocessing (S1) are executed. ) Are executed in parallel, pre-processing (S2 and S3) necessary for the state of FIG. 13C and the state of FIG. 13D is executed. As a result, the processing time of the preprocessing (S2 and S3) related to <"small", "B">, <"saving", "B"> and <"small", "B"> is the drawing process (S11). Since it is hidden, the preload preprocessing (S2 and S3) can be executed without affecting the time for displaying the state of FIG. 13B.

  However, when the preloaded data is not used, the power required for the pre-processing for bleeding is wasted, so the Kana-Kanji conversion application holds the history information about the use of candidates, and at what timing based on this history information You may decide how far to preload. In addition, it is possible to calculate how many candidate preloads are concealed in the drawing time in consideration of the drawing processing time and the preprocessing preloading time.

  Moreover, you may control the aggressiveness of a preload according to the surplus electric power generated with the solar cell with which an information processing apparatus is provided, or the residual amount of an electrical storage part. For example, when there is a lot of surplus power generated by a solar cell or when the remaining amount of a power storage unit is large, the preload is positively increased to improve the responsiveness of the information processing device. When the amount is small or when the remaining amount of the power storage unit is small, the number of preloads can be suppressed.

(Embodiment 6)
The EPD rewrite control unit 110 using the preprocessing cache according to the first to fourth embodiments may be combined with the preloading of the preprocessing cache according to the fifth embodiment. In that case, saving the state of the SoC 200 to the nonvolatile memory speeds up the recovery process from the standby state with low power consumption when executing hibernation to turn off the power of the SoC 200, the memory, and the display. Can do.

  FIG. 16 is a timing chart showing an operation example at the time of hibernation when the preprocessing cache is not performed and when it is performed. FIG. 16A shows a timing chart when the preprocessing cache is not performed in the information processing apparatus that uses the EPD as a display, and FIG. 16B shows that the preprocessing cache is performed in the information processing apparatus that uses the EPD as a display. The timing chart in the case is shown.

  In an information processing apparatus using an LCD or the like as a display, the LCD is turned off in a standby state in which hibernation suspend processing has been performed, and nothing is displayed on the display. Therefore, the process for returning from the standby state for the user is started by inputting a specific key on the keyboard or inputting a power button, and is completed by displaying a screen immediately before entering the suspend process on the display (FIG. 16 ( In a), S92 to S93). The responsiveness for the user can be said to be the time until the screen immediately before entering the suspend process is displayed.

  On the other hand, the case of an information processing apparatus including the EPD 140 as a display is different. Even in the suspended standby state, the EPD 140 that is a non-volatile display always displays the screen immediately before the suspension. Therefore, the user does not return from the standby state suspended by a specific key input or the like, but the recovery is started by touch panel or keyboard input for the contents of the currently displayed screen in the standby state and is displayed in the standby state. After the processing for the contents of the screen is executed, the time until the result is displayed on the EPD 140 (S92 to S95) (the time until the display of the EPD 140 changes) is the response time for the user. Therefore, in an information processing apparatus using the EPD 140 as a display, it cannot be said that the responsiveness is improved unless the time until the processing result for the contents of the screen displayed in the standby state is displayed on the EPD 140 is shortened.

  In addition, the time from when the user finishes operating the information processing apparatus to when the suspend process is started has little effect on the responsiveness for the user. Therefore, as shown in S11, before starting the suspend process, a pre-process of the rewrite process predicted after the return may be performed, and the result may be preloaded into the pre-process cache. In that case, since the preprocessing cache can be used at the time of return, the responsiveness can be improved. However, if there are many rewrite processing options for the user to complete the return processing, preloading all of them will increase the cost required for preloading. Therefore, for example, it may be determined whether or not preloading should be executed based on the number of options. Alternatively, specific image data indicating that restoration processing is in progress is determined, the preprocessing result of the image data is always stored in the preprocessing cache, and when the restoration processing is started, this is first specified in the EPD 140 It is also possible to promptly inform the user that the return process has started.

  FIG. 17 is a flowchart illustrating an example of a processing flow at the time of hibernation executed by an electronic book application terminal, an interactive electronic POP, an electronic medical record, or the like. In the example shown in FIG. 17, it is assumed that power consumption is reduced by actively using hibernation on the application side during browsing. Further, it is assumed that the return process is started by using the BACK key or the NEXT key of the keyboard as a trigger in the standby state after the suspend process. When the BACK key is pressed, the page before the currently displayed page is rewritten. When the NEXT key is pressed, the next page is rewritten.

  As shown in FIG. 17, in the processing flow at the time of hibernation, first, the OS of the information processing apparatus selects a rewrite processing option (preload item) that completes the return processing before instructing the application to execute hibernation. It is checked whether or not the number is larger than the threshold (step S601). For example, when the threshold is 1, there are two options for the NEXT key and the BACK key. However, since the BACK key causes a cache hit in the preprocessing cache, it may be determined that preloading is unnecessary and that one option is determined.

  When the preload item is larger than the threshold (step S601; YES), the OS proceeds to step S603. On the other hand, if the preload item is smaller than the threshold value (step S601; NO), the OS instructs the EPD rewrite control unit 110 to execute the preprocessing for the next page to be rewritten when the NEXT key is pressed (step S602). The process proceeds to step S603. This preloads the next page into the preprocessing cache.

  In step S603, after the preload is completed, the OS executes hibernation (step S603). Thereafter, when the return processing from the standby state is started when the NEXT key is pressed, a request to rewrite the next page is sent to the EPD rewrite control unit 110. On the other hand, the EPD rewrite control unit 110 executes the rewrite process using the preprocess cache because the preprocess cache has a cache hit. This makes it possible to return from the suspended standby state at high speed.

  Note that the threshold for the preload item may be changed according to the surplus power generated by the solar battery of the information processing apparatus or the remaining amount of the power storage unit. For example, the threshold value may be increased when the surplus power generated by the solar battery is large or when the remaining amount of the power storage unit is large.

  Here, an example of the return processing from the standby state when hibernation is executed has been described, but it goes without saying that the present invention is also applicable to a standby state in which the information processing apparatus has low power consumption.

(Embodiment 7)
In the preprocessing cache method according to the first to fourth embodiments, by providing the EPD rewrite control unit 110 with information or knowledge regarding rewrite processing possessed by an application or the like in the form of hint information, the cache hit rate of the preprocess cache is further increased. Can be increased. In addition, by guaranteeing a cache hit situation in the preprocessing cache, data generation processing such as rendering for preparing rewritten data in the frame buffer and the processing for writing the generated rewritten data to the frame buffer are eliminated. As a result, more active power saving and higher speed can be achieved.

  The EPD 140 has a rewrite process with a high probability and a low probability of executing the same rewrite process again. When a rewrite process with a high probability that an application or middleware will be executed again can be identified, hint information indicating whether the rewrite process with a high probability of being executed again is included in the rewrite process passed to the EPD rewrite control unit 110. By adding, it becomes possible for the cache management unit 111 of the EPD rewrite control unit 110 to use when determining whether or not to cache the preprocess result. As a result, it is possible to reduce the average power consumption and processing time required for the rewriting process to increase the cache hit rate. Further, as in the third embodiment, when there are memories with different access speeds where caches can be arranged, it becomes possible to use which rewrite processing pre-processing result should be arranged in a fast-access memory. . As hint information, for example, the pre-processing result of the rewriting process should not be cached, the pre-processing result of the rewriting process should be cached as much as possible, and the frequently used data such as menus must be used. For example, it can be cached so that it is not replaced from the cache.

  In FIG. 18 and FIG. 19, hint information that always instructs the preprocessing cache not to be replaced and cached is added to the rewriting request to guarantee the situation in which the cache hits the preprocessing cache. An outline of an example in which data generation processing such as rendering for preparing in a buffer or the like and processing for writing the generated rewritten data to the frame buffer can be eliminated.

  FIG. 20 shows an example of the cache entry of the preprocessing cache. The example shown in FIG. 20 has a configuration in which a LOCK bit is added to the preprocessing cache shown in FIG. As shown in FIG. 20, when hint information that instructs to be cached and not replaced is added, the cache management unit 111 sets the LOCK bit of the preprocessing cache to ‘1’. When the LOCK bit is “1”, the preprocessing cache is not replaced with other data. However, if the LOCK bit of all cache entries is “1” and no more cache entries can be added, the next time this hint information is received, the rewrite process is performed without caching, and the application For example, it may be configured to notify that the cache cannot be cached any more and release the unnecessary LOCK bit.

  The example shown in FIG. 18 is an example in which rewriting processing is performed by adding hint information that guarantees a cache hit at the time of the first rewriting. As shown in FIG. 18, first, rewrite data 731 is generated from data 701 that is the basis of the rewrite data by performing rendering processing for generating rewrite data using an accelerator such as CPU 101 or GPU. To do. The generated rewrite data 731 is copied onto a memory accessed by the preprocessing accelerator 102 such as the frame buffer 703 using a GPU or the like. The preprocessing unit 113 instructs the preprocessing accelerator 102 to perform preprocessing. The preprocessing accelerator 102 executes preprocessing according to the instruction. At this time, if the cache determination unit 112 determines a cache miss, the cache management unit 111 caches the preprocessing cache with the LOCK bit of the preprocessing cache set to “1”, and the rewrite processing unit 114 performs the preprocessing cache. The EPD controller 105 is instructed to rewrite using the above data. Note that the hint information may be added when instructing the EPD rewrite control unit 110 to preload the preprocessing cache without performing the drawing process.

  The example shown in FIG. 19 is an example in the case where the subsequent rewriting process is performed in a state in which it is guaranteed that a cache hit is sure. In the example shown in FIG. 19, since all information necessary for the rewriting process is on the preprocessing cache, there is no need for rewriting data on the frame buffer. Processing such as generation of the rewrite data 731 and writing of the rewrite data 731 into the frame buffer 703 can be omitted. For this reason, it is possible to greatly shorten a series of processing time until the rewrite processing unit 114 including the part for generating the rewrite data 731 instructs rewrite. As a result, the responsiveness of the information processing apparatus can be greatly improved, and the time during which the information processing apparatus is in a standby state with low power consumption can be lengthened, so that power can be reduced accordingly. In addition, since it is possible to reduce power required for processing for generating rewritten data 731, writing to the frame buffer 703, and preprocessing, it is possible to significantly reduce power consumption.

  FIG. 21 is a flowchart illustrating an example of a processing flow on the application or middleware side according to the seventh embodiment. FIG. 21 exemplifies a case where rewriting processing is performed by adding hint information that guarantees a cache hit at the time of the first rewriting. First, an accelerator such as the CPU 101 or a GPU performs a rendering process for generating rewrite data (step S701). Next, the accelerator 101 such as the CPU 101 or the GPU copies the generated rewrite data 731 onto the memory accessed by the preprocessing accelerator 102 such as the frame buffer 703 (step S702). Thereafter, a rewrite request including hint information is issued to the EPD rewrite control unit 110 such as a driver of the EPD controller 210 (step S703), and the process ends.

  FIG. 22 is a flowchart showing an example of the subsequent rewriting process in a state where it is guaranteed that a cache hit will always occur. In the case shown in FIG. 22, since all information necessary for rewriting is in the preprocessing cache, the application or middleware performs a process of issuing a rewriting request to the EPD rewriting control unit 110 (step S711). In this way, processing such as processing for writing to the frame buffer 703 becomes unnecessary on the application side.

  A reusable processing result for generating the rewrite data 731 may be configured to realize a two-level cache that is cached at the application or middleware level.

  Further, the seventh embodiment can be combined with the preload to the preprocessing cache of the fifth embodiment. For example, if it is decided to rewrite all pages in turn in an application or a questionnaire that conducts a test for learning use in an educational setting, the N + 1th page is preprocessed when the Nth page is requested to be rewritten. By adding hint information to be preloaded into the cache, it is possible to overlap the Nth page rewrite process and the N + 1th preprocess. As a result, the processing time with the shorter processing time can be concealed.

  In addition to the method of adding hint information to the rewrite request each time, the knowledge and information possessed by the application are stored in the EPD rewrite control unit 110, for example, at the time of starting the application or immediately before starting a series of fixed processes. You may comprise so that it may pass as hint information. In this way, for example, when browsing a relatively small number of pages such as academic paper data or electronic medical records with a relatively small number of pages, the hint information indicates the browsing method and the total number of pages. , It is possible to determine that it is more efficient to cache all pages.

(Embodiment 8)
By reducing the preprocessing time using the preprocessing cache according to the first to fourth embodiments, the start timing of the subsequent rewriting process can be advanced. As a result, the processing time of the entire rewriting process can be shortened, so that the SoC 100 and the memory can be turned into a standby state with low power consumption or turned off in a short time, and further power saving can be achieved. it can.

  In the following description, for the sake of clarity, the description will be made on the assumption that the configuration of the information processing apparatus 1 (see FIG. 1) according to the first embodiment is applicable, but the present invention is applicable to any configuration of the first to fourth embodiments. . However, as a premise, it is assumed that the EPD controller 210 is designed to be able to start rewrite processing periodically. According to this configuration, for example, the timing at which rewriting can be started every N milliseconds is neglected, and the actual drawing process to the EPD 140 is performed in response to the rewriting request that can be drawn after the preprocessing is completed by that time. .

  An image viewer application used for explanation will be described with reference to FIG. As shown in FIG. 23, in the image viewer application, an area 810 for displaying image data, and a BACK key 801 and a NEXT key 803 for switching the image data are displayed on the EPD 140 by software. When the BACK key 801 is selected on the touch panel, the previous image data is displayed in the area 810, and when the NEXT key 803 is selected, the next image data is displayed in the area 810. In this image viewer application, when the BACK key 801 and the NEXT key 803 are selected, the key is rewritten to feed back the selection to the user. Since these keys are frequently rewritten in the image viewer application, there is a high possibility of a cache hit in the preprocessing cache. On the other hand, since the image data is switched one after another, rewriting of uncached image data occurs when the NEXT key 803 is selected. In other words, in this application, when the NEXT key 803 is selected, two rewrite processes are performed: a rewrite process of the NEXT key 803 itself that causes a cache hit in the preprocess cache, and an image rewrite process that does not hit the cache in the preprocess cache. Is called.

  FIG. 24 is a timing chart showing an example of two rewrite processes processed in parallel by the EPD controller. FIG. 24A is a time chart when there is no preprocessing cache for two rewriting processes processed in parallel by the EPD controller 105. First, preprocessing of the NEXT key 803 is started at time T0, and the processing is in time for rewriting start timing T1, so that the drawing processing of the NEXT key 803 is started at time T1. In the configuration of FIG. 1, since there is only one preprocessing accelerator 102 that performs preprocessing, the preprocessing of image data starts from time T1 when the preprocessing of the NEXT key 803 ends. Since this pre-processing ends a little before time T2, which is the rewrite start possible timing, a rewrite start wait occurs until time T2. At time T2, image data drawing processing is started. The drawing process is completed at time T4, and the main memory 120 and the SoC 100 can be turned off for the first time, or can be shifted to a standby state with low power consumption.

  On the other hand, FIG. 24B is a timing chart when the preprocessing cache is used. First, since the NEXT key 803 has a cache hit in the preprocessing cache, the NEXT key 803 does not need to be preprocessed. Therefore, the preprocessing accelerator 102 can immediately execute preprocessing of image data. The drawing process of the NEXT key 803 is not started until the time T1 at which the rewriting can be started, and waits for the start of rewriting. Since the preprocessing of the image data ends by time T1, the drawing processing of the image data and the NEXT key 803 is started simultaneously and executed in parallel, and the drawing processing is completed earlier than time T4. Therefore, the main memory 120 and the SoC 100 can be turned off or can be shifted to a standby state with low power consumption from the end time to time T4. As a result, it is possible to reduce power consumption compared to the case where the preprocessing cache is not used.

  In this way, by using the preprocessing cache, a power saving effect can be obtained even when a series of rewriting processes in which the preprocessing cache does not work is included.

(Embodiment 9)
In the above-described embodiment, the rewrite data ID for distinguishing the rewrite data is stored in the tag portion of the preprocessing cache. However, the configuration is not limited to this, and a configuration in which, for example, the rewrite data ID is not used is also possible. In that case, the rewritten data itself may be used instead of the rewritten data ID in the configuration of the preprocessing cache shown in FIG. In this case, the rewritten data ID field may be a pointer to data. With this configuration, even when a rewrite request without a rewrite data ID is issued, the rewrite data is compared with the rewrite data stored in the preprocessing cache as described above. A determination similar to the determination of whether or not the rewrite data IDs matched in the embodiment can be made. In this case, since the rewritten data is compared, the processing amount is small if the data size of the rewritten data is small. Therefore, the configuration may be such that cache or determination processing is performed. Further, the size of the rewrite data and the display position on the EPD 140 may be used instead of the rewrite data ID.

  Such a configuration can be used in all of the above-described embodiments. Note that the comparison between the rewritten data and the rewritten data stored in the preprocessing cache can be performed by software or hardware.

(Embodiment 10)
In the above-described embodiment, the information processing apparatus alone is configured to save power by using the preprocessing cache. However, the present invention is not limited to this. For example, a plurality of information processing apparatuses perform common preprocessing. In this case, it is possible to prevent the preprocessing in each information processing apparatus from being performed by offloading the preprocessing to a cloud, a server, a multi-function peripheral, a smartphone, a tablet PC, a digital television, or the like.

  FIG. 25 is a block diagram illustrating a schematic configuration example of a cloud system according to the tenth embodiment. As illustrated in FIG. 25, the cloud system 10 includes a configuration in which a plurality of information processing apparatuses 1A to 1N and a cloud server 1001 are connected via a network 1000 such as the Internet. Each of the information processing apparatuses 1A to 1N may be any information processing apparatus according to the above-described embodiment. In the following, it is assumed that the information processing apparatus 1 according to the first embodiment is used for simplification of description. The cloud server 1001 is a computing system that can communicate using the wireless LAN controller 106 or the like inside the SoC 100. The cloud server 1001 executes preprocessing for rewritten data and holds the obtained preprocessing results as preprocessing caches 1001A to 1001N. doing. The cloud server 1001 may be, for example, a server, a cloud, a multifunction peripheral, a smartphone, a tablet PC, or a digital TV. The preprocessing caches 1001A to 1001N are managed on a non-volatile memory on a computer constituting the cloud.

  The EPD rewrite control unit provided on the cloud server 1001 side may be the same as the EPD rewrite control unit 110 (see FIG. 2) according to the first embodiment. However, the rewrite processing unit 114 is arranged on the information processing apparatuses 1A to 1N side.

  For example, when browsing the same electronic book with these information processing apparatuses 1 </ b> A to 1 </ b> N, performing the same preprocessing in each information processing apparatus is wasteful of power consumption. Therefore, common preprocessing is performed in the cloud server 1001 for preprocessing, and the resulting pair of preprocessed rewritten data and rewrite control information selection ID is cached on the cloud server 1001 side as preprocessed caches 1001A to 1001N. Keep it.

  FIG. 26 shows an example of the processing flow of the cloud system according to the tenth embodiment. As shown in FIG. 26, first, when displaying an arbitrary page of a specific electronic book on each of the information processing apparatuses 1A to 1N, a request for rewriting the corresponding rewrite data is sent from the information processing apparatuses 1A to 1N to the cloud server 1001. The cache determination unit 112 in the EPD rewrite control unit 110 of the cloud server 1001 is called by being transmitted to the above EPD rewrite control unit 110 via the wireless LAN controller 106 of each of the information processing apparatuses 1A to 1N (step S1001). The cache determination unit 112 checks the preprocessing caches 1001A to 1001N on the cloud server 1001, and determines whether or not a cache hit occurs in the preprocessing caches 1001A to 1001N (step S1002). When a cache hit occurs in any of the preprocessing caches 1001A to 1001N (step S1002; YES), the EPD rewrite control unit 110 of the cloud server 1001 proceeds to step S1006. On the other hand, if no cache hit occurs in any of the preprocessing caches 1001A to 1001N (step S1002; NO), the cache management unit 111 in the EPD rewrite control unit 110 of the cloud server 1001 determines a cache entry for storing the preprocessing result. (Step S1003). Next, the preprocessing unit 113 in the EPD rewrite control unit 110 of the cloud server 1001 performs preprocessing of the page on the cloud server 1001 (step S1004), and the rewrite control information that is the preprocessing result in the determined preprocessing cache. The selection ID and preprocessed rewritten data are stored (step S1005), and the process proceeds to step S1006.

  In step S1006, the cloud server 1001 transmits the rewrite control information selection ID on the preprocess cache and the pair of preprocessed rewrite data to the rewrite processing unit 114 on the information processing apparatuses 1A to 1N side (step S1006). On the other hand, the rewrite processing unit 114 on the information processing apparatuses 1A to 1N side reads the rewrite control information corresponding to the received rewrite control information selection ID from the main memory 120 of the information processing apparatuses 1A to 1N and the like. Using the processed rewrite data, the EPD controller 105 is instructed to perform drawing processing on the EPD 140 (step S1007), and the processing is terminated.

  Note that the pre-processing caches 1001A to 1001N created by the cloud server 1001 are created differently depending on the display type, size, resolution, version of rewrite control information, temperature, etc. of the information processing apparatuses 1A to 1N. Also good.

  Further, on the information processing apparatuses 1A to 1N side, the drawing process of the EPD 140, the reception process of the next page, and the transmission process of the next rewrite request (may be a pre-processing preload request that requests only the pre-processing). By overlapping, it is possible to reduce the time during which the information processing apparatuses 1A to 1N are active, and thus it is possible to reduce power consumption. In addition, when a plurality of partial rewriting processes are required in each of the information processing apparatuses 1A to 1N to display one page of an electronic book or one screen of a web browser, the page is not transmitted / received for each rewriting process. By transmitting and receiving in a unit such as, it is possible to reduce power consumption and time required for data transmission and reception. Further, in the information processing apparatuses 1A to 1N, the transmission / reception of a unit of data is overlapped with the drawing process, so that the active time can be shortened in the information processing apparatuses 1A to 1N, and the standby time with low power consumption is achieved. The power consumption can be reduced.

  In addition, instead of executing pre-processing on the cloud server 1001 side every time a rewrite request is received from the information processing apparatuses 1A to 1N, an electronic book is created when an e-book application executed on the information processing apparatuses 1A to 1N is started. Information to be identified may be transmitted, and preprocessing of all pages of the electronic book may be executed in parallel on the cloud server 1001.

  Further, the rewrite control information may be transmitted from the cloud server 1001 side instead of the rewrite control information selection ID. In this case, the information processing devices 1A to 1N may not hold the rewrite control information.

  The rewrite control information may be arranged on the information processing apparatuses 1A to 1N side without the need to arrange the rewrite data. When the preprocessing is always offloaded onto the cloud server 1001, the information processing apparatuses 1A to 1N do not need the preprocessing accelerator 102, so the information processing apparatuses 1A to 1N can be reduced in power consumption and are compact and lightweight. can do. On the other hand, assuming that wireless LAN access is not possible, the rewrite data may be on the information processing apparatuses 1A to 1N side. When the time and power consumption required for wireless LAN transmission / reception change dynamically and may increase compared to preprocessing on the information processing apparatuses 1A to 1N side, for example, application startup Try both the case where preprocessing is performed on the cloud server 1001 side and the case where preprocessing is performed on the information processing apparatuses 1A to 1N side, and switch to the one with the smaller processing time or power consumption at certain times or at regular time intervals. You may do it.

  When the preprocessing caches 1001A to 1001N are configured on a non-volatile memory such as the MRAM of the computer forming the cloud server 1001, the power management unit 115 reduces power consumption by turning off the power of the MRAM at idle. Can do.

  Moreover, you may control transmission / reception according to the surplus electric power generated with the solar cell of information processing apparatus 1A-1N, and the residual amount of an electrical storage part. For example, when there is a lot of surplus power generated by a solar battery or when the remaining amount of the power storage unit is large, in preparation for a case where these become small, preloading the preprocessing of the previous page of the e-book and the result of the preprocessing Reception may be performed.

  Alternatively, the cloud server 1001 may execute preprocessing, and the preprocessing caches 1001A to 1001N may be managed on the information processing apparatus side as in the above-described embodiment. In this case, once the information processing apparatus has cached, the drawing process can be performed without preprocessing, and the rewriting process can be saved.

(Embodiment 11)
In the above-described embodiment, the electronic paper rewriting process is continuously performed using the same rewriting control information with the same rewriting data, such as a scroll bar which is a user interface attached to a web browser or a list, and the rewriting area thereof If there is an overlap, it is also possible to preload only the difference on the preprocessing cache and repeat the drawing process using the difference on the preprocessing cache. Alternatively, it is also possible to preload the rewrite data cache, calculate the difference therefrom, and repeatedly perform drawing processing using the difference. In these cases, the amount of data processing is reduced, and when the user of the information processing device operates the scroll bar or the like, the drawing process is executed immediately (the scroll bar moves), thereby improving the responsiveness. And power consumption can be reduced. At that time, the amount of data processing is reduced by thinning out the continuous rewriting process, so that the power consumption can be reduced.

  Here, an example will be described in which a rewrite mode optimized for a scroll bar is prepared in the EPD rewrite control unit, and a rewrite process is executed using the rewrite mode. FIG. 27 is a diagram for explaining the outline of the rewriting process using the rewriting mode optimized for the scroll bar. In FIG. 27, the illustrated scroll bar has a white rail-shaped background and a black knob (knob) indicating the area currently displayed on the EPD 140. Such a scroll bar can be drawn with binary image data. The application or middleware uses a scroll bar rewriting area 1101 that is an area surrounded by a dotted line that is a combination of a black part 1103 (knob) surrounded by a dotted line in FIG. 27 and a white part 1102 that is a rectangular area above it. In the rewriting process, rewriting requests are issued to the EPD rewriting control unit 110 in the order of rewriting A → rewriting B → rewriting C → rewriting D → rewriting E. As a result, since the black portion 1103 (knob) of the scroll bar is displayed while being shifted downward, it is expressed as if the knob was slid downward.

  In the scroll bar rewriting process, first, before the scroll process by the user starts, such as when the application is started, the scroll bar rewriting mode is used in the application, and the scroll bar rewriting area 1101 is used as scroll bar information at that time. The EPD rewrite control unit 110 is notified in advance of the rewrite data ID (for example, No. 100) used when issuing the rewrite request. At this time, the size of the scroll bar rewriting area 1101 and the sizes of the white portion 1102 and the black portion 1103 are also notified to the EPD rewriting control unit 110. The EPD rewrite control unit 110 performs preprocessing so as to select rewrite control information in which an afterimage of the end portion (white portion 1102) is difficult to remain, and preloads the preprocess cache with rewrite data ID = 100. For the black portion 1103, the black portion 1103 (knob) is divided into an overlapping portion 1103a of the black portion 1103 before and after moving one unit (for example, rewriting A → rewriting B) and the remaining head portion 1103b. Even if the afterimage of the head portion 1103b remains, it can be erased at the time of rewriting the tail portion (white portion 1102), so that the rewrite control information is selected so that the black portion 1103 can be seen by the user as soon as possible. The result is preloaded to the preprocessing cache with the next rewrite data ID = 101, for example.

  When rewriting with rewrite control information so that no afterimage remains, if black appears to be the fastest in the middle of the rewriting process so that no afterimage remains, take advantage of its characteristics. The rewrite control information may be used. Further, the preprocessing of the overlapping portion 1103a is not necessary.

  When the actual user scroll process is started and the rewrite data ID = 100 and the position of the scroll bar rewrite area 1101 (rewrite start position) are notified to the EPD rewrite control unit 110 one after another, the preprocess cache is rewritten. Since it is already known that the data ID = 100 is the rewrite data ID for the scroll bar when the application is started, the preprocessing cache with the rewrite data ID = 101 is also searched and calculated based on the scroll bar information. A rewrite process using cached data is performed at a predetermined rewrite position. Specifically, first, the rewrite processing unit 114 instructs to rewrite the head portion 1103b, and then instructs to rewrite the tail portion (white portion 1102). Note that the rewriting of the head portion 1103b uses rewrite control information that can be quickly shown to the user, so that the movement of the knob can be made to follow the user's scrolling process. The user experience can be improved. Since the afterimage is erased by rewriting the tail portion (white portion 1102), the afterimage does not remain in the scroll process.

  Depending on the unit of the movement distance of the knob, there are cases where rewriting occurs frequently. In that case, it is preferable to reduce the number of rewrites by thinning out intermediate rewrites. Thereby, power saving can be achieved. The thinning rate may be, for example, once every several times. For example, every other rewriting B and rewriting D among the rewriting A to rewriting E of FIG. Furthermore, if the number of rewrites is large, the EPD controller 105 exceeds the number of rewrite processes that can be processed in parallel, and there may be a case where the overwritten rewrite process waits until the end of the preceding rewrite process. In that case, it is preferable to adjust the rewrite time interval so that the number of rewrites does not exceed the number that can be processed in parallel. For example, if the rewriting time interval is T, R is the time required for rectangular rewriting processing, and P is the upper limit of parallelism, the number of rewriting times is reduced by thinning out the intermediate rewriting processing so that T is larger than R / P. It is possible to avoid exceeding the number that can be processed in parallel, so that the overwritten rewriting process can be prevented from waiting until the end of the preceding rewriting process.

  FIG. 28 shows an outline of the rewriting process when the user who has moved the knob downward in FIG. 27 suddenly changes the movement direction of the knob upward. In the example shown in FIG. 28, after the rewriting process is performed in the order of rewriting A to rewriting E, a rewriting request is issued to the EPD rewriting control unit 110 in the order of rewriting e to rewriting a. In this case, if it takes time to rewrite the end portion (white portion 1102) of the rewrite E to white, the rewrite e head portion 1103b is rewritten to black and the rewrite d start portion until the rewrite is completed. Rewriting processing of the area having the same height as the top portion of the rewriting e is awaited under the portion 1103b. Therefore, when the entire rewriting process of the scroll bar rewriting area is performed without division, the entire rewriting process of the rewriting e and the rewriting d waits for completion of the preceding rewriting process, and the movement of the knob may not follow the user's scrolling process. . Therefore, the rewriting process is performed by dividing the head part 1103b and the tail part (white part 1102), so that the rewriting process of the head part 1103b of rewriting d and the rewriting process of rewriting white in rewriting e and rewriting d. Rewritten first without being affected by the preceding rewriting process. Thereby, it can be shown that the knob is moving following the user, and usability can be improved. Note that the rewriting of the head portion 1103b of the rewriting e is executed after the rewriting of the end portion (white portion 1102) of the rewriting E.

Embodiment 12
Next, an information processing device, a display control device, a semiconductor chip, a display device control method, and a program thereof according to a twelfth embodiment will be described in detail with reference to the drawings. In the following description, the same components as those in the above-described embodiment are denoted by the same reference numerals, and redundant description thereof is omitted.

  The form in which the minimum part necessary for the rewriting process is operated using the microcontroller 400 according to the fourth embodiment is not limited to the information processing apparatus 4 equipped with the EPD 140, and a general display device such as an LCD is installed. It can also be applied to smartphones, tablet PCs, mobile phones and the like. The preprocessing in this case includes a rewriting data generation process such as a rendering process and a screen to be displayed. The value stored in the preprocessing cache is the contents of the frame buffer used by the display device as a result.

  FIG. 29 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the twelfth embodiment. As illustrated in FIG. 29, the information processing apparatus 12 according to the twelfth embodiment includes an EPD 140 of the information processing apparatus 4 (see FIG. 11) according to the fourth embodiment as a display device 1240 such as an LCD, and an EPD controller 210 as an LCD controller. The display device controller 1210 includes a configuration in which the EPD dedicated memory 220 is replaced with the display device dedicated memory 1220, and the SoC 100 is replaced with the SoC 1200 including the preprocessing accelerator 102.

  When receiving a request for interrupt processing using a keyboard or the like, the microcontroller 400 determines whether or not a pre-processing cache for rewriting processing to the display device 1240 corresponding to the interrupt exists, and in the case of a cache hit, the display device. A rewrite request is directly transmitted to the controller 1210. When a cache miss occurs, an interrupt is transmitted to the SoC 1200, and a rewrite request is issued from the SoC 1200 to the display device 1240 as necessary. For this reason, when a cache hit occurs in the preprocessing cache, the power supplied to the main memory 120 is shifted to a lower power than when normal reading and writing is possible, which can hold the memory contents, with the SoC 1200 powered off. Therefore, it is possible to perform the rewriting process with the minimum necessary configuration for rewriting the page, thereby greatly reducing the power consumption. For example, in the case of an electronic book application, when opening a new electronic book or its new chapter, etc., it operates with a configuration including the SoC 1200 and the main memory 120, and repeats simple page feed when browsing the electronic book thereafter. It is possible to operate the most part of the time with the minimum necessary configuration that does not use the SoC 1200 or the main memory 120.

  The information processing device 12 includes a SoC 1200, a main memory 120, a display device 1240, a display device controller 1210, a display device dedicated memory 1220, power supply control devices 150A and 150B, a power supply control device 450, and a microcontroller 400. And one or more input devices 130.

  The microcontroller 400 consumes less power than the SoC 1200 and is always energized. The microcontroller 400 has an internal memory 401, and the tag portion of the preprocessing cache is held in the internal memory 401.

  The display device controller 1210 has an internal memory 211. The internal memory 211 stores a preprocessing cache composed of a plurality of rewrite data. The tag portion of the preprocessing cache is also stored in the internal memory 211 of the display device controller 1210. Consistency is maintained between the tag portion of the preprocessing cache held in the internal memory 211 of the display device controller 1210 and the tag portion of the preprocessing cache held in the internal memory 401 of the microcontroller 400.

  In the twelfth embodiment, the display device rewrite control unit is a process in the display device controller 1210. The configuration may be the same as that of the EPD rewrite control unit 110 shown in FIG. 2, for example. However, the cache determination unit 112 is also mounted on the microcontroller 400. A power management unit that turns on / off the power of the SoC 1200 may be mounted on the microcontroller 400. The preprocessing unit 113 is a process of an OS, middleware, or application that runs on the CPU 101, and may use the preprocessing accelerator 102 or the like.

  FIG. 30 shows a configuration example of a preprocessing cache held on the display device controller 1210. The preprocessing cache is composed of a plurality of cache entries. In the example of FIG. 30, there are four entries. Each cache entry is composed of a pair of a tag part and a preprocess cache data part.

  The tag part is composed of a preprocessed rewritten data ID and a VALID bit. The rewrite request of the display device 1240 issued by an application or the like is issued with a preprocessed rewrite data ID that distinguishes the preprocessed rewrite data. The cache determination unit 112 that has received such a rewrite request determines whether or not a cache hit occurs. In the cache determination, by searching the tag part, the preprocessed rewritten data ID matches, and the VALID bit indicating whether the data of the cache entry is valid (VALID) or invalid (INVALID) becomes valid (VALID). It is determined whether there is an entry.

  The preprocessed rewrite data ID is information for uniquely identifying the preprocessed rewrite data. For example, the application or middleware manages the preprocessed rewrite data and the preprocessed rewrite data ID in association with each other, and when rewriting using the same preprocessed rewrite data, the same preprocessed rewrite data ID is used as a rewrite request. In addition, the display device rewrite control unit is notified.

  The preprocessed cache data portion stores preprocessed rewritten data. The preprocessed rewrite data is the size of a frame buffer for storing data for rewriting the screen, and the data size is the same in this example.

  FIG. 31 is a flowchart illustrating an example of a rewrite process according to the twelfth embodiment. In the example shown in FIG. 31, the display device rewrite control unit caches preprocessed rewritten data. This process is started when the user of the information processing apparatus 12 generates an interrupt to the microcontroller 400 by a key input on the keyboard or the like. Similar to the third embodiment, a specific preprocessed rewrite data ID is assigned in advance to a specific key of the keyboard.

  As shown in FIG. 31, in the rewriting process, the cache determination unit 112 on the microcontroller 400 uses the tag part of the preprocessing cache on the internal memory 104 of the microcontroller 400, and the preprocessed data notified at the time of interruption It is checked (cache determination) whether there is a match with the rewrite data ID in the preprocessing cache (step S1201). If a cache hit occurs (step S1201; YES), the power supply control device 150B supplies power to the display device controller 1210. The display device controller 1210 is powered on (step S1212), a rewrite request is transmitted to the display device controller 1210 (step S1213), and the process proceeds to step S1211. On the other hand, when there is no cache hit (step S1201; NO), the cache determination unit 112 on the microcontroller 400 notifies the SoC 1200 of an interrupt. Thereby, the key input event is notified to the application or the like (step S1202), and processing corresponding to the key input event is executed by the application or the like as necessary. As a result, the pre-processing unit 113 executes pre-processing such as rendering using the pre-processing accelerator 102 such as GPU (step S1203), and uses the obtained pre-processing result to transmit the information to the display device controller 1210. A rewrite request with the processed rewrite data ID added is issued (step S1204). When notifying the interrupt to the SoC 1200, if the power of the SoC 1200 is off, the power management unit 115 of the microcontroller 400 turns on the power of the SoC 1200 using the power control device 150A, and then notifies the interrupt. . Further, after a rewrite request is issued to the display device controller 1210 as a result of processing corresponding to the key input event, the SoC 1200 may be shifted to a standby state with low power consumption, or a power management unit on the microcontroller 400 115 may instruct the power supply to the SoC 1200 to stop.

  Next, the power management unit 115, which is a process of the display device controller 1210, confirms whether the power of the display device dedicated memory 1220 is turned off or in a power saving state with relatively low power consumption (step S1205). ) When the power is off or in the power saving state (step S1205; YES), the power of the display device dedicated memory 1220 is turned on using the power control device 150B, or the read / write state is saved. After returning from the power state (step S1206), the process proceeds to step S1207. On the other hand, if the power of the display device dedicated memory 1220 is on (step S1205; NO), the display device controller 1210 proceeds directly to step S1207.

  In step S1207, the cache management unit 111, which is the process of the display device controller 1210, determines a cache entry using an algorithm for determining a cache entry to be replaced, such as LRU (step S1207). Subsequently, the preprocessing unit 113, which is the process of the display device controller 1210, writes the result of the preprocessing executed in step S1203 in the determined cache entry (step S1208).

  Next, the power management unit 115, which is a process of the display device controller 1210, turns off the power of the display device dedicated memory 1220 using the power supply control device 150B or makes a transition to the power saving state (step S1209). Next, the cache management unit 111 of the display device controller 1210 transmits information on the tag part of the preprocessing cache to the microcontroller 400, and executes processing for updating the tag part for synchronization on the microcontroller 400 side. Thus, the tag portion held in the internal memory 401 of the microcontroller 400 is matched with the tag portion in the internal memory 211 of the display device controller 1210 (step S1210), and the process proceeds to step S1211. As a result, consistency is maintained between the tag portion held in the internal memory 401 of the microcontroller 400 and the tag portion in the internal memory 211 of the display device controller 1210. Note that the processing shown in step S1210 may be executed via the SoC 1200.

  In step S1211, the rewrite processing unit 114, which is the process of the display device controller 1210, reads the preprocessed rewrite data stored in the preprocess cache and performs the rewrite process of the display device 1240 (step S1211). End the operation.

  When the display on the display device 1240 is turned off and put into a standby state after the rewriting process is completed, the power management unit 115 turns off the power to the display device 1240 and the display device controller 1210 using the power control device 150B. . When the internal memory 211 of the display device controller 1210 uses a non-volatile memory, the cached data is retained even when the power is turned off. When a volatile memory is used, data in the internal memory 211 may be written to the display device dedicated memory 1220 so that the display device dedicated memory 1220 can be set to a power saving mode in which the contents of the memory can be retained. The internal memory 211 of the device controller 1210 may be set to a power saving mode that can hold the contents of the memory, or only the internal memory 211 may be energized.

  In the twelfth embodiment, in step S1210, the tag portion of the microcontroller 400 and the tag portion of the display device controller 1210 are made consistent. However, the rewrite process to be cached is limited to a plurality of specific preprocessed rewrite data IDs. In this case, step S1210 can be omitted by setting the information processing apparatus 12 in advance.

(Embodiment 13)
Similar to the twelfth embodiment, the form in which the internal memory 104 of the SoC 100 of the third embodiment is used as a preprocessing cache is not limited to the information processing apparatus 4 equipped with the EPD 140, and is equipped with a general display device such as an LCD. It can also be applied to smart phones, tablet PCs, mobile phones and the like. The preprocessing in this case includes a rewriting data generation process such as a rendering process and a screen to be displayed. The value stored in the preprocessing cache is the result of the frame buffer.

  FIG. 32 is a block diagram illustrating a schematic configuration of the information processing apparatus according to the thirteenth embodiment. As shown in FIG. 32, the information processing apparatus 13 according to the thirteenth embodiment includes an EPD 140 of the information processing apparatus 1 (see FIG. 1) according to the first embodiment as a display device 1240 such as an LCD, and an EPD controller 105 as an LCD controller. Each of the display device controllers 1305 has a replaced configuration.

(Embodiment 14)
Further, in the configuration of the thirteenth embodiment, as in the sixth embodiment, it is possible to speed up the return from the state where the hibernation suspend process has been performed. In this case, the preprocessed rewritten data to be displayed after returning may be stored in the preprocess cache of the internal memory 104 before entering the standby state with low power consumption.

(Embodiment 15)
In the above-described embodiment, as shown in FIG. 33, a temperature range parameter may be added to the tag portion of the preprocessing cache. That is, in the fifteenth embodiment, the information processing apparatus includes a temperature sensor, and different rewrite control information is used according to the temperature of a space in which the information sensor is disposed.

  The above-described embodiment and its modifications are merely examples for carrying out the present invention, and the present invention is not limited thereto, and various modifications according to specifications and the like are within the scope of the present invention. Furthermore, it is obvious from the above description that various other embodiments are possible within the scope of the present invention. For example, it is needless to say that the modification examples illustrated as appropriate for the embodiments can be combined with other embodiments.

  DESCRIPTION OF SYMBOLS 1,1A-1N, 2,3,4,12,13 ... Information processing apparatus, 10 ... Cloud system, 100, 200, 1200, 1300 ... SoC, 101 ... CPU, 102 ... Pre-processing accelerator, 103 ... Memory controller 104 ... Internal memory, 105 ... EPD controller, 106 ... Wireless LAN controller, 107 ... Bus, 110 ... EPD rewrite control unit, 111 ... Cache management unit, 112 ... Cache determination unit, 113 ... Pre-processing unit, 113a ... Data conversion Processing unit 113b ... Selection processing unit 114 ... Rewrite processing unit 115 ... Power management unit 120 ... Main memory 130 ... Input device 140 ... EPD 150A, 150B, 450 ... Power control device 210 ... EPD controller 213... EPD drawing unit, 220... EPD dedicated memory, 301 and 8 DESCRIPTION OF SYMBOLS 1 ... BACK key, 302 ... SELECT key, 303, 803 ... NEXT key, 340 ... Menu, 400 ... Microcontroller, 401 ... Internal memory, 701 ... Original data, 703 ... Frame buffer, 705, 1001A-1001N ... Pre-processing cache, 731 ... rewrite data, 810 ... area, 1000 ... network, 1001 ... cloud server, 1101 ... scroll bar rewrite area, 1102 ... white part, 1103 ... black part, 1103a ... overlapping part, 1103b ... top part, 1210 , 1305... Display device controller, 1220... Display device dedicated memory, 1240.

Claims (5)

A first memory that is a non-volatile memory, executes a first process on the first data stored in the first memory, and is capable of executing the first process with power supplied to the first memory; In the information processing apparatus that switches between power and second power lower than the first power,
The information processing apparatus includes a plurality of candidates for the first process,
When the number of candidates for the first process is smaller than a predetermined threshold, the first process is executed with the power supplied to the first memory as the first power, and after the first process is completed Switching the power supplied to the first memory from the first power to the second power;
If the number of candidates for the first process is greater than or equal to the threshold, the power supplied to the first memory is switched from the first power to the second power and then returned to the first power again. Performing the first process;
Information processing device. A pre-processing unit that generates the first image data for display from data that is the basis of the first image data stored in the first memory;
A management unit that transfers processed rewrite data including the first image data generated by the preprocessing unit to a second memory;
A determination unit that determines whether the processed rewritten data is held in the second memory when the display device is rewritten using the first image data;
When the processed rewrite data is held in the second memory, a rewrite processing unit that instructs drawing processing of the display device using the held processed rewrite data;
A control unit that executes drawing processing of the display device using the processed rewritten data held in the second memory in accordance with an instruction from the rewrite processing unit;
After the processed rewrite data is transferred to the second memory, the power control for switching the power supplied to the first memory to a second power lower than the first power that enables access to the first memory And
A display control device. A power control unit that controls power supplied to each of the first semiconductor chip in which the preprocessing unit is incorporated and the second semiconductor chip in which the determination unit is incorporated;
When the processed rewritten data generated for the data that is the source of the first image data is stored in the second memory, the rewritten processing unit stores the processed rewritten data that is stored. Instructing the drawing process of the display device using
The second semiconductor chip operates with lower power than the first semiconductor chip;
The power supply control unit supplies power supplied to the first semiconductor chip when the processed rewritten data generated for the data that is the source of the first image data is not held in the second memory. The display control apparatus according to claim 2, wherein the fifth power is switched to a sixth power that is higher than the fifth power.   The display control device according to claim 2, wherein the second memory is an internal memory built in the SoC. The pre-processing unit has not yet issued a rewrite request for rewriting the display device immediately before the power supplied to the display control device is switched from the third power to the fourth power lower than the third power. Performing the pre-processing on the original data of the other first image data that is not,
The management unit includes the other first image generated by the preprocessing unit with respect to the data that is the source of the other first image data for which a rewrite request for rewriting the display device has not yet been issued. The display control apparatus according to claim 2, wherein data is written to the second memory.

Images