JP2009246617A - Output buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of suppressing generation of an erroneous operation signal in start-up of a power source. <P>SOLUTION: The output buffer circuit 1 includes a timing adjusting circuit TA for generating a fourth signal G to be outputted to an output circuit 30 by delaying a phase of fall timing in start-up of a power source for a second signal D outputted from a second level converter 10b. The timing adjusting circuit TA includes a third level converter 10c for generating a third signal E that falls later than a first signal B of a first level converter 10a, and an OR circuit 42 for outputting to the output circuit 30 the fourth signal G having a result of logical OR operation of the third signal E and the second signal D. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an output buffer circuit of a semiconductor device, and more particularly to a three-state type output buffer circuit.

An output buffer circuit 100 of a conventional semiconductor device that operates with two types of power supply voltages will be described with reference to FIG.
The output buffer circuit 100 receives a data input signal A and a control input signal C from an internal circuit (not shown) of the semiconductor device. Based on the input signals A and C, the output buffer circuit 100 has an H level, an L level, and a high impedance. This is a three-state circuit that outputs three values.

  The output buffer circuit 100 is roughly divided into a level converter unit 110 that converts and outputs the signal levels of the input signals A and C, and an output signal OUT based on a signal input from the level converter unit 110. And an output circuit 130 for outputting to EX.

  The level converter unit 110 includes a first level converter 110a and a second level converter 110b. The first level converter 110a receives the data input signal A and its inverted signal A bar from the core circuit operating at the power supply potential VDL on the semiconductor chip core side. The first level converter 110a converts the level of the signals A and A having an amplitude from the ground level to the power supply potential VDL on the semiconductor chip core side into an amplitude from the ground level to the external output interface power supply potential VDH, thereby converting the first signal B. To the output circuit 130.

  The second level converter 110b receives a control input signal C and its inverted signal C bar from an internal circuit. The second level converter 110b converts the level of the signals C and C having an amplitude from the ground level to the power supply potential VDL on the semiconductor chip core side into an amplitude from the ground level to the external output interface power supply potential VDH, thereby converting the second signal D. To the output circuit 130.

  The output circuit 130 includes a logic control circuit 140 and a final stage buffer 150. Based on the signals B and D from the level converter unit 110, the logic control circuit 140 outputs the external output interface power supply potential VDH level or ground level signals J and K to the transistors TP60 and TN60 of the final stage buffer 150, respectively. . The final stage buffer 150 uses the three values of the external output interface power supply potential VDH level (H level), the ground power supply potential level (L level), and the high impedance as the output signal OUT based on the input signals J and K. Output.

  More specifically, when the second signal D is at the L level, the H level output signal OUT is output if the first signal B is at the H level, and conversely, if the first signal B is at the L level, the L level is output. A level output signal OUT is output. On the other hand, when the second signal D is at H level, the node N60 between the transistors TP60 and TN60 is set to high impedance regardless of whether the first signal B is at H level or L level.

For example, Patent Document 1 is known as such a three-state type output buffer circuit.
Japanese Patent Laid-Open No. 10-285013

  However, in such an output buffer circuit 100, if the parasitic capacitances in the level converters 110a and 110b are different, the first signal B and the second signal D output from each level converter are turned on when the power is turned on. A signal delay Skew (see FIG. 10B) occurs. In particular, when the parasitic capacitance of the first level converter 110a becomes larger than that of the second level converter 110b, the first signal B is delayed with respect to the second signal D as shown in FIG. Here, the magnitude of such parasitic capacitance varies depending on the wiring length that changes depending on the arrangement position of elements such as transistors constituting the level converters 110a and 110b, and the type of power supply wiring in the upper layer. Then, it has been clarified by the present inventors that a malfunction signal SH as shown in FIG. 10D is generated as the output signal OUT by the signal delay Skew.

  Hereinafter, a malfunction signal SH generated at the time of power-up when the L-level data input signal A and the L-level control input signal C are input (hereinafter simply referred to as “power-up”) will be described.

  As shown in FIG. 10A, when the power is turned on, the power supply potential VDL on the semiconductor chip core side and the external output interface power supply potential VDH rise with a predetermined slope. Further, the inverted signals A and C which become H level rise following the rising level of the power supply potential VDL on the semiconductor chip core side. The inverted signals A and C are input to the N channel MOS transistor TN11 of the first level converter 110a and the N channel MOS transistor TN21 of the second level converter 110b. At this time, until the signal levels of the inverted signals A and C exceed the threshold values of the transistors TN11 and TN21, the signal levels of the signals B and D are maintained at the external output interface power supply as shown in FIG. It rises following the rise of the potential VDH. That is, when L level input signals A and C are input, the L level signals B and D are supposed to be output, but the signal levels of the inverted signals A and C are set to the transistors TN11 and TN21. Until the threshold value is exceeded, the L level signals B and D are not output.

  When the inverted signals A and C bar exceed the thresholds of the transistors TN11 and TN21, the transistors TN11 and TN21 are turned on and the signals B and D fall to the ground level (L level). However, as described above, when the parasitic capacitance of the first level converter 110a becomes larger than that of the second level converter 110b, the transmission time of the first signal B becomes longer than that of the second signal D, and therefore FIG. ), The first signal B falls later than the second signal D. The signal delay Skew generated by the signals B and D is input to the transistors TP60 and TN60 of the final stage buffer 150 while maintaining the delay by intra-buffer racing. Then, as shown in FIG. 10 (c), the timing at which both the signals J and K input to the transistors TP60 and TN60 become L level occurs. By these L level signals J and K, P channel MOS transistor TP60 is turned on and N channel MOS transistor TN60 is turned off. For this reason, as shown in FIG. 10D, an H-level malfunction signal SH that follows the rising level of the external output interface power supply potential VDH is generated as an output signal OUT for a moment, and in the initial operation state when the power is turned on. There is a risk of malfunction.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide an output buffer circuit capable of suppressing the occurrence of a malfunction signal when the power is turned on.

  In order to achieve the above object, an output buffer circuit according to claim 1 includes a first level converter that generates a first signal based on a data input signal, and a second level that generates a second signal based on a control input signal. And a third level converter that generates a third signal, and generates a fourth signal that delays the fall of the second signal when the power is turned on based on the third signal And a timing adjustment circuit that outputs the fourth signal to the output circuit, and the third level converter receives an input for outputting a third signal of a reference potential when the power is turned on. A transistor connected to the source of the second power supply potential in the third level converter is a transistor connected to the source of the second power supply potential in the first level converter. It was larger than the register.

  As described above, the first signal and the second signal are the second power supply when the power is turned on even when the signal level of the reference potential is output based on the data input signal and the control input signal. The signal level rises following the rising level of the potential. Then, the first signal and the second signal fall to the reference potential after a predetermined time has elapsed. Here, the predetermined time is a time until the first and second level converters operate stably.

  According to the above configuration, the third signal output from the third level converter is set to output the signal level of the reference potential when the power is turned on. However, like the first signal and the second signal, the signal level of the third signal rises following the rising level of the second power supply potential until the third level converter operates stably. Then, the third signal falls to the reference potential after a predetermined time has elapsed. At this time, the timing at which the first to third signals fall to the reference potential varies depending on the parasitic capacitance of each level converter. Here, since the predetermined transistor in the third level converter is formed larger than the predetermined transistor in the first level converter, the parasitic capacitance of the third level converter is larger than that of the first level converter. Therefore, since the transmission time of the third signal is longer than that of the first signal, the third signal falls later than the first signal. Since the fourth signal in which the falling timing of the second signal is delayed is generated based on the third signal that falls later than the first signal, the falling timing of the generated fourth signal is generated. Can be the same as or slower than the first signal. Thereby, even if the transmission time of the first signal is longer than that of the second signal, it is possible to suppress the occurrence of the delay of the first signal with respect to the fourth signal output from the second level converter side to the output circuit. . Therefore, the first signal of the second power supply potential and the fourth signal of the reference potential are output although the first and second signals (fourth signal) of the reference potential should be output to the output circuit. Can be suppressed. Therefore, generation | occurrence | production of the malfunction signal which may generate | occur | produce by the delay of the 1st signal with respect to a 4th signal can be suppressed suitably.

The output buffer circuit according to claim 2, wherein the timing adjustment circuit includes an OR circuit that generates the fourth signal having a result of an OR operation between the second signal and the third signal.
According to the above configuration, in the OR circuit, the fourth signal having the logical sum operation result of the third signal that falls later than the first signal and the second signal is generated. Therefore, when the power supply is turned on, a signal that falls late to the reference potential is generated as the fourth signal among the second signal and the third signal. Therefore, the fourth signal generated by the OR circuit is a signal that falls later than the first signal when the power is turned on. For example, when the transmission time of the first signal is longer than that of the second signal, the third signal having a transmission time longer than that of the first signal is output to the output circuit as the fourth signal. Thereby, even if the transmission time of the first signal is longer than that of the second signal, it is possible to suppress the occurrence of the delay of the first signal with respect to the fourth signal output from the second level converter side to the output circuit. .

  The output buffer circuit according to claim 3, wherein the timing adjustment circuit includes a delay circuit that generates a delay signal obtained by delaying the third signal by a predetermined time and outputs the delay signal to the OR circuit. The circuit generates the fourth signal having a result of an OR operation between the delayed signal and the second signal.

  According to the above configuration, the third signal output from the third level converter is further delayed in the delay circuit. As a result, the delayed signal input to the OR circuit is a signal that surely falls later than the first signal. Therefore, the fourth signal generated by the OR circuit is a signal that surely falls later than the first signal.

  The output buffer circuit according to claim 4, wherein the timing adjustment circuit is generated by an AND circuit that generates a signal having a result of a logical product operation of the first signal and the third signal, and the AND circuit. OR circuit for generating the fourth signal having a result of a logical OR operation between the received signal and the second signal.

  According to the above configuration, the AND circuit generates a signal having a logical product operation result of the first signal and the third signal. Therefore, at the time of power-on, the signal that falls first before the reference potential is output to the OR circuit among the first signal and the third signal. At this time, since the third signal is set to fall later than the first signal, the first signal is always output from the AND circuit when the power is turned on.

  In the OR circuit, a fourth signal having a logical OR operation result between the second signal and the first signal input through the AND circuit is generated. Therefore, when the power is turned on, a signal that falls late to the reference potential is generated as the fourth signal among the first signal and the second signal. Therefore, the fourth signal generated by the OR circuit is the same signal as the first signal or falls later than the first signal when the power is turned on. For example, when the transmission time of the first signal is longer than the second signal, the first signal is output to the output circuit as the fourth signal. Thereby, even if the transmission time of the first signal is longer than that of the second signal, it is possible to suppress the occurrence of the delay of the first signal with respect to the fourth signal output from the second level converter side to the output circuit. .

  The output buffer circuit according to claim 5 includes a first level converter that generates a first signal based on a data input signal, and a second level converter that generates a second signal based on a control input signal, The transistor connected to the source of the second power supply potential in the second level converter is formed larger than the transistor connected to the source of the second power supply potential in the first level converter.

  As described above, the first signal and the second signal are the second power supply when the power is turned on even when the signal level of the reference potential is output based on the data input signal and the control input signal. The signal level rises following the rising level of the potential. Then, the first signal and the second signal fall to the reference potential after a predetermined time has elapsed. At this time, the timing at which the first and second signals fall to the reference potential varies depending on the parasitic capacitance of each level converter. Here, in the above configuration, since the predetermined transistor in the second level converter is formed larger than the predetermined transistor in the first level converter, the parasitic capacitance of the second level converter is larger than that of the first level converter. Also grows. Accordingly, the transmission time of the second signal is longer than that of the first signal. Thereby, generation | occurrence | production of the delay of the 1st signal with respect to a 2nd signal can be suppressed.

  As described above, according to the present invention, it is possible to provide an output buffer circuit capable of suppressing the generation of a malfunction signal when the power is turned on.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. In the present embodiment, the same components as those shown in FIG. 9 will be described with the same reference numerals.

  As shown in FIG. 1, the output buffer circuit 1 is roughly divided into a level converter unit 10 that converts and outputs a signal level of an input signal input from an internal circuit (not shown) of the semiconductor device, and a level converter unit. 10 includes an output circuit 30 that outputs an output signal OUT to an external output terminal EX based on a signal input from 10, and a timing adjustment circuit TA.

  The level converter 10 includes a first level converter 10a that generates a first signal B obtained by level-converting a data input signal A input from an internal circuit, and a second level that converts a level of a control input signal C input from the internal circuit. The second level converter 10b for generating the signal D and the third level converter 10c for generating the third signal E for delaying the falling of the second signal D when the power is turned on are provided.

  The first level converter 10 a includes a first input circuit 11 and a first level converter circuit 21. The first input circuit 11 includes first and second inverter circuits 11a and 11b. The power supply terminals of the inverter circuits 11a and 11b are connected to the power supply potential VDL (first power supply potential) and the ground power supply potential (reference potential) on the semiconductor chip core side, respectively.

  The first inverter circuit 11a logically inverts the input data input signal A, and generates a power supply potential VDL level (HL level) or ground level (L level) signal AI on the semiconductor chip core side. The second inverter circuit 11b logically inverts the inverted signal AI input from the first inverter circuit 11a and generates a signal AT having a signal level (L level or HL level) equivalent to the data input signal A. In this way, the first input circuit 11 generates complementary signals AT and AI having amplitudes from L level to HL level. The first input circuit 11 supplies the complementary signals AT and AI to the first level converter circuit 21.

  The signal AI output from the first inverter circuit 11a is supplied to the gate of the N-channel MOS transistor TN11 of the first level converter circuit 21. The signal AT output from the second inverter circuit 11b is supplied to the gate of the N-channel MOS transistor TN12. The sources of these transistors TN11 and TN12 are connected to the ground power supply potential.

  The drain of the transistor TN11 is connected to the drain of the P-channel MOS transistor TP11, and the drain of the transistor TN12 is connected to the drain of the P-channel MOS transistor TP12. The sources of these transistors TP11 and TP12 are connected to the external output interface power supply potential VDH (second power supply potential).

  A node N11 between the transistors TN11 and TP11 is connected to the gate of the transistor TP12, and a node N12 between the transistors TN12 and TP12 is connected to the gate of the transistor TP11. The node N11 is connected to the output circuit 30, and the first signal B at the external output interface power supply potential VDH level (H level) or the ground level (L level) is output from the node N11 to the output circuit 30. That is, the first level converter circuit 21 converts the level of the complementary signals AT and AI having the amplitude from the L level to the HL level into the amplitude from the L level to the H level, and outputs the first signal B as the output circuit 30. Output to.

  The second level converter 10 b includes a second input circuit 12 and a second level converter circuit 22. The second input circuit 12 is composed of first and second inverter circuits 12a and 12b. Similar to the first input circuit 11, the second input circuit 12 generates complementary signals CT and CI having amplitudes from L level to HL level based on the input control input signal C. The second input circuit 12 supplies the complementary signals CT and CI to the second level converter circuit 22.

  The signal CI output from the first inverter circuit 12a is supplied to the gate of the N-channel MOS transistor TN21 of the second level converter circuit 22. A signal CT output from the second inverter circuit 12b is supplied to the gate of the N-channel MOS transistor TN22. The sources of these transistors TN21 and TN22 are connected to the ground power supply potential.

  The drain of the transistor TN21 is connected to the drain of the P-channel MOS transistor TP21, and the drain of the transistor TN22 is connected to the drain of the P-channel MOS transistor TP22. The sources of these transistors TP21 and TP22 are connected to the external output interface power supply potential VDH.

  A node N21 between the transistors TN21 and TP21 is connected to the gate of the transistor TP22, and a node N22 between the transistors TN22 and TP22 is connected to the gate of the transistor TP21. The node N21 is connected to the slow phase circuit 40, and the second signal D of H level or L level is output from the node N21 to the slow phase circuit 40. That is, the second level converter circuit 22 converts the level of the complementary signals CT and CI having the amplitude from the L level to the HL level into the amplitude from the L level to the H level, and outputs the second signal D as a delay circuit. Output to 40.

  The third level converter 10 c includes a third level converter circuit 23. The power supply potential VDL on the semiconductor chip core side is supplied as a signal V to the gate of the N-channel MOS transistor TN31 of the third level converter circuit 23. The power supply potential VDL on the semiconductor chip core side is supplied to the gate of the N-channel MOS transistor TN32 through the inverter circuit 13 as a ground level signal VI. The sources of these transistors TN31 and TN32 are connected to the ground power supply potential.

  The drain of the transistor TN31 is connected to the drain of the P-channel MOS transistor TP31, and the drain of the transistor TN32 is connected to the drain of the P-channel MOS transistor TP32. The sources of these transistors TP31 and TP32 are connected to the external output interface power supply potential VDH. Here, the transistors TP31 and TP32 are transistors having a larger element size than the transistors TP11 and TP12 in the first level converter circuit 21. Specifically, the transistors TP31 and TP32 are R times the size of the transistors TP11 and TP12 in the first level converter circuit 21 (R is a real number larger than 1 and twice in this embodiment) (for example, Gate area). Thereby, the parasitic capacitance of the third level converter 10c becomes larger than the parasitic capacitance of the first level converter 10a.

  A node N31 between the transistors TN31 and TP31 is connected to the gate of the transistor TP32, and a node N32 between the transistors TN32 and TP32 is connected to the gate of the transistor TP31. The node N31 is connected to the slow phase circuit 40, and the third signal E is output from the node N31 to the slow phase circuit 40. The third signal E will be described in detail. When the voltage levels of the power supplies VDH and VDL are stable, the L level third signal E is always output from the node N31. However, when the power supply is turned on, the third rise that follows the rising level of the external output interface power supply potential VDH until the power supply potential VDL (signal V) on the semiconductor chip core side exceeds the threshold voltage of the transistor TN31. Signal E is output. On the other hand, if the power supply potential VDL (signal V) on the semiconductor chip core side exceeds the threshold voltage of the transistor TN31 at the time of power supply startup, the third signal E that follows the rising level of the external output interface power supply potential VDH is generated. Fall to L level. At this time, as described above, since the parasitic capacitance of the third level converter 10c is larger than that of the first level converter 10a, the transmission time of the third signal E is longer than that of the first signal B of the first level converter 10a. become longer.

  The delay phase circuit 40 includes a delay circuit 41 and an OR circuit 42. The delay circuit 41 is composed of an even number (two stages in FIG. 1) of inverter circuits connected in series. The delay circuit 41 delays the third signal E input from the third level converter 10 c for a predetermined time according to the number of stages of the inverter circuit, and outputs the delayed signal Ed to the OR circuit 42.

  The OR circuit 42 receives the second signal D from the second level converter 10b together with the delay signal Ed. The OR circuit 42 outputs to the output circuit 30 a fourth signal G having a result obtained by performing an OR operation on the delay signal Ed from the delay circuit 41 and the second signal D from the second level converter 10 b.

  More specifically, when the L level third signal E is output from the third level converter 10c as in the case where the voltage levels of the power supplies VDH and VDL are stable, the L level delay signal Ed is ORed. Input to the circuit 42. For this reason, the OR circuit 42 outputs the second signal D from the second level converter 10b to the output circuit 30 as the fourth signal G.

  On the other hand, the power supply potential from the third level converter 10c to the external output interface is the same as when the power is input to which the L level data input signal A and the control input signal C are input (hereinafter simply referred to as “power supply startup”). When the third signal E at the rising level (H level) of VDH is output, the delay signal Ed at the H level is input to the OR circuit 42. Therefore, when the H level delay signal Ed is input in this way, the OR circuit 42 outputs the H level delay signal Ed as the fourth signal G regardless of the signal level of the second signal D. Output to 30. Here, the delay signal Ed is a signal whose timing of falling from the rising level of the power supply potential VDH to the L level is later than that of the first signal B. Therefore, the OR circuit 42 does not output the second signal D to the output circuit 30 when the power is turned on when the first signal falls later than the second signal D, but instead of the first signal B The delayed signal Ed that falls late is output to the output circuit 30 as the fourth signal G. This suppresses the occurrence of the signal delay Skew of the first signal B with respect to the fourth signal G output from the second level converter 10b side to the output circuit 30 when the power is turned on.

  As described above, in the present embodiment, the delay phase circuit 40 and the third level converter 10c delay the fall of the second signal D when the power is turned on, thereby generating the signal delay Skew shown in FIG. It functions as a timing adjustment circuit TA that suppresses.

Next, the internal configuration of the output circuit 30 will be described with reference to FIG.
As shown in FIG. 2, the output circuit 30 includes a logic control circuit 50 and a final stage buffer 60. The logic control circuit 50 includes five inverter circuits 51, 52, 53, 54, and 55, and a NOR circuit 56 and a NAND circuit 57 that are connected to the inverter circuits 51 to 55, respectively. Although not shown, the power supply terminals of the inverter circuits 51 to 55 are connected to the external output interface power supply potential VDH and the ground reference potential, respectively.

  The inverter circuit 51 logically inverts the first signal B input from the first level converter 10 a and outputs the logically inverted signal BI to the input terminals of the NOR circuit 56 and the NAND circuit 57, respectively.

  The inverter circuit 52 logically inverts the fourth signal G input from the OR circuit 42 and outputs the logically inverted signal GI to the input terminals of the inverter circuit 53 and the NAND circuit 57, respectively. The inverter circuit 53 logically inverts the signal GI input from the inverter circuit 52 and outputs a signal GT having a signal level equivalent to that of the fourth signal G to the input terminal of the NOR circuit 56.

  The NOR circuit 56 outputs to the inverter circuit 54 a signal J having a result obtained by performing a NOR operation on the input signal BI and the signal GT. The inverter circuit 54 logically inverts the signal J input from the NOR circuit 56 and outputs the inverted signal JI to the final stage buffer 60.

  The NAND circuit 57 outputs a signal K having a result obtained by performing a NAND operation on the input signal BI and the signal GI to the inverter circuit 55. The inverter circuit 55 logically inverts the signal K input from the NAND circuit 57 and outputs the inverted signal KI to the final stage buffer 60.

  The final stage buffer 60 includes a P-channel MOS transistor TP60 and an N-channel MOS transistor TN60. The inverted signal JI is supplied from the inverter circuit 54 to the gate of the transistor TP60, and the inverted signal KI is supplied from the inverter circuit 55 to the gate of the transistor TN60. The source of the transistor TP60 is connected to the external output interface power supply potential VDH, and the drain is connected to the drain of the transistor TN60. The source of the transistor TN60 is connected to the ground.

These transistors TP60. A node N60 between the TN60 is connected to the external output terminal EX, and an output signal OUT is output from the node N60.
Next, the operation of the output buffer circuit 1 configured as described above in a state where the voltage levels of the power supplies VDL and VDH are stable will be described with reference to FIG.

First, a case where an L level data input signal A is input when an L level control input signal C is input will be described.
As shown in FIG. 3, when the L-level data input signal A is input, the signal AI becomes the HL level and the signal AT becomes the L level, the transistor TN11 is turned on, and the transistor TN12 is turned off. When the transistor TN11 is turned on, the transistor TP12 is turned on because its gate is connected to the ground. When transistor TP12 is turned on, transistor TP11 is turned off because its gate is connected to external output interface power supply potential VDH. At this time, the potential of the node N11 between the transistors TN11 and TP11 becomes the ground level (L level), and the L-level first signal B is output from the node N11 to the output circuit 30.

  On the other hand, when the L level control input signal C is input, the signal CI becomes HL level and the signal CT becomes L level, the transistor TN21 is turned on and the transistor TN22 is turned off. At this time, the potential of the node N21 between the transistors TN21 and TP21 becomes the ground level, and the second signal D of L level is output from the node N21 to the OR circuit 42.

  In the third level converter 10c, when the voltage levels of the power supplies VDL and VDH are stable, the TN signal V is always supplied to the transistor TN31 and the L signal VI is supplied to the transistor TN32. Therefore, the transistor TN31 is turned on and the transistor TN32 is turned on. At this time, since the potential of the node N31 between the transistors TN31 and TP31 becomes the ground level, the L-level third signal E is always output to the delay circuit 41 from the node N31 (third level converter 10c). For this reason, the L level delay signal Ed is always output from the delay circuit 41 to the OR circuit 42. Thus, when the voltage level of each power supply is stable, the second signal D output from the second level converter 10 b is output to the output circuit 30 as the fourth signal G in the OR circuit 42. Therefore, here, the L-level second signal D is output to the output circuit 30 as the fourth signal G.

  Next, when the L level first signal B is input to the inverter circuit 51 of the output circuit 30 and the L level fourth signal G is input to the inverter circuit 52, the NOR circuit 56 receives the H level signal BI and the L level. The signal GT is input. The NAND circuit 57 receives an H level signal BI and an H level signal GI. Then, the H level signal JI is supplied from the NOR circuit 56 through the inverter circuit 54 to the transistor TP60. The H level signal KI is supplied from the NAND circuit 57 to the transistor TN60 via the inverter circuit 55.

  The transistor TP60 is turned off in response to the H level signal JI, and the transistor TN60 is turned on in response to the H level signal KI. As a result, the L level output signal OUT is output from the node N60 between the transistors TP60 and TN60 to the external output terminal EX.

  Next, when the data input signal A rises from L level to H level from time t1, the signal AI becomes L level and the signal AT becomes H level, the transistor TN11 is turned off, and the transistor TN12 is turned on. Then, the transistor TP11 is turned on and the transistor TP12 is turned off. At this time, the potential of the node N11 becomes the external output interface power supply potential VDH level (H level), and the first signal B of H level is output from the node N11 to the output circuit 30.

  When the H-level first signal B and the L-level fourth signal G are input to the output circuit 30, the L-level signal JI is supplied to the transistor TP60, and the L-level signal KI is supplied to the transistor TN60. The Then, the transistor TP60 is turned on and the transistor TN60 is turned off. As a result, the H level output signal OUT is output from the node N60 to the external output terminal EX.

  Next, when the control input signal C rises from L level to H level from time t2, the signal CI becomes L level and the signal CT becomes H level, the transistor TN21 is turned off, and the transistor TN22 is turned on. Then, the transistor TP21 is turned on and the transistor TP22 is turned off. At this time, the potential of the node N21 becomes the external output interface power supply potential VDH level (H level), and the fourth signal G of H level is output from the node N21 via the OR circuit 42 to the output circuit 30.

  When the H level fourth signal G is input to the output circuit 30 in this way, the first signal B (data input signal A) is H level (time t2 to t3), L level (time t3). In the subsequent period), an H level signal JI is supplied to the transistor TP60, and an L level signal KI is supplied to the transistor TN60. Thereby, both the transistor TP60 and the transistor TN60 are turned off, and the node N60 is set to high impedance.

  Next, the operation of the output buffer circuit 1 when the power is turned on will be described with reference to FIG. Here, when the L level data input signal A and the L level control input signal C are input, the parasitic capacitance of the first level converter 10a is larger than the parasitic capacitance of the second level converter 10b. Will be described.

  When the power supply is turned on as shown in FIG. 4A, the voltage levels of the power supply potential VDL on the semiconductor chip core side and the external output interface power supply potential VDH rise with a predetermined slope.

  At this time, when the L-level data input signal A is input to the first input circuit 11, the signal AI at the power supply potential VDL level on the semiconductor chip core side is input to the transistor TN 11 of the first level converter circuit 21. The TN 12 receives an L level signal AT. When the L level control input signal C is input to the second input circuit 12, the transistor TN21 of the second level converter circuit 22 receives the signal CI of the power supply potential VDL level on the semiconductor chip core side, and the transistor TN22. Is supplied with an L level signal CT. Further, the power supply potential VDL on the semiconductor chip core side is always input as the signal V to the transistor TN31 of the third level converter circuit 23, and the L level signal VI is always input to the transistor TN32.

  Here, the transistors TN12, TN22, and TN32 are turned off by the L level signals AT, CT, and VI. On the other hand, the transistors TN11, TN21, and TN31 are turned on when the HL level signals AI, CI, and V are input while the power supply potential VDL on the semiconductor chip core side is stable as described above. However, when the power supply is turned on, as shown in FIG. 4A, the voltage level of the power supply potential VDL on the semiconductor chip core side is not stable and rises with a predetermined slope. Therefore, the signals AI, CI, and V that are supposed to be at the HL level rise following the rising level of the power supply potential VDL on the semiconductor chip core side when the power is turned on. Accordingly, the transistors TN11, TN21, and TN31 are turned on until the voltage level of the power supply potential VDL on the semiconductor chip core side, that is, the signal levels of the signals AI, CI, and V exceed the threshold voltages of the transistors TN11, TN21, and TN32. Not. Therefore, until these transistors TN11, TN21, and TN31 are turned on, the first to third level converter circuits 21 to 23 operate unstablely in the inactive region. That is, the level converter circuits 21 to 23 that should output the L level signals B, D, and E are set to the rising level of the external output interface power supply potential VDH in the inactive region, as shown in FIG. Signals B, D, and E that follow and rise are output (time t11 to t12).

  When the signal levels of the signals AI, CI, V exceed the threshold voltages of the transistors TN11, TN21, TN31, the transistors TN11, TN21, TN31 are turned on. Then, the signals B, D, and E that have followed the rising level of the external output interface power supply potential VDH are lowered to the L level.

  At this time, since the parasitic capacitance of the first level converter 10a is larger than that of the second level converter 10b, the transmission time of the first signal B is longer than that of the second signal D, and the first signal B becomes the second signal. Fall later than D. That is, the second signal D falls at time t12, and then the first signal B falls at time t13. The first signal B is output to the output circuit 30 and the second signal D is output to the OR circuit 42.

  Further, since the transistors TP31 and TP32 in the third level converter 10c are formed to have a larger element size than the transistors TP11 and TP12 in the first level converter 10a, the parasitic capacitance of the third level converter 10c is reduced to the first level converter. It becomes larger than that of 10a. Accordingly, the transmission time of the third signal E is longer than that of the first signal B, and the third signal E falls later than the first signal B. That is, the first signal B falls at time t13, and then the third signal E falls at time t14. The third signal E falling later than the first signal B is delayed by a predetermined time in the delay circuit 41 and output to the OR circuit 42 as the delay signal Ed. That is, the delay signal Ed falls at time t15 that is delayed by a predetermined time from time t14.

  Here, the OR circuit 42 to which the second signal D and the delay signal Ed are input is in a period (time t11 to t15) in which the delay signal Ed at the rising level (H level) of the external output interface power supply potential VDH is input. Outputs the H-level delayed signal Ed to the output circuit 30 as the fourth signal G regardless of the signal level of the second signal D. That is, even if the second signal D falls earlier than the first signal (time t11), the fourth signal G output to the output circuit 30 is time t15 when the delay signal Ed falls due to the delay signal Ed. (See FIG. 4C). Then, when the delay signal Ed falls (time t15), the fourth signal G also falls. As a result, the fourth signal G output from the second level converter 10b side to the output circuit 30 is more time (t15-t13) than the first signal B output from the first level converter 10a side to the output circuit 30. Only late. Therefore, even if the transmission time of the first signal B becomes longer than the second signal D, the signal delay Skew of the first signal B with respect to the fourth signal G output from the second level converter 10b side to the output circuit 30 Occurrence can be suppressed. That is, even if the second signal D falls earlier than the first signal B, the occurrence of the signal delay Skew of the first signal B with respect to the fourth signal G can be suppressed.

  Thereby, when the power is turned on, as shown in FIG. 4C, the first signal B is at the H level, and the fourth signal G output from the second level converter 10b side to the output circuit 30 is at the L level. There will be no timing. Therefore, as shown in FIG. 4D, the signal JI output from the inverter circuit 54 does not fall to the L level. That is, unlike the conventional output buffer circuit 100, the timing when the signals JI and KI input to the final stage buffer 60 are both at the L level does not occur. Accordingly, as shown in FIG. 4E, in the output buffer circuit 1 including the timing adjustment circuit TA, the malfunction signal SH is not generated as the output signal OUT.

According to the embodiment described above in detail, the following effects can be obtained.
(1) The timing adjustment circuit TA including the third level converter 10c and the slow phase circuit 40 is provided. Based on the third signal E, the timing adjustment circuit TA generates a fourth signal obtained by delaying the fall of the second signal when the power is turned on. That is, the timing adjustment circuit TA does not output the second signal D that falls earlier than the first signal B to the output circuit 30 when the power is turned on, and instead falls third later than the first signal B. The signal E is output to the output circuit 30 as the fourth signal G. As a result, when the power is turned on, the fall of the fourth signal G output from the second level converter 10b to the output circuit 30 is detected, and the first signal B output from the first level converter 10a to the output circuit 30 is detected. You can fall later. Therefore, the generation of the signal delay Skew of the first signal B with respect to the fourth signal G can be suitably suppressed. This eliminates the timing at which both the signals JI and KI are at the L level when the power is turned on, so that the generation of the malfunction signal SH can be suitably suppressed.

  In addition, since the generation of the signal delay Skew of the first signal B with respect to the fourth signal G can be suppressed in this way, the degree of freedom in the startup sequence of the power supply potential VDL on the semiconductor chip core side and the external output interface power supply potential VDH Can be improved.

  (2) The transmission time of the first and second signals B and D output from the level converters 10a and 10b is strongly influenced by the magnitude of the parasitic capacitance with respect to the external output interface power supply potential VDH in the level converters 10a and 10b. It was made clear by the present inventors to receive. That is, as the parasitic capacitance with respect to the external output interface power supply potential VDH in each level converter 10a, 10b increases, the transmission time of the first and second signals B, D becomes longer.

  Therefore, in the present embodiment, the transistors TP31 and TP32 to which the external output interface power supply potential VDH in the third level converter 10c is connected to the source are connected to the transistors TP31 and TP32, and the external output interface power supply potential VDH in the first level converter 10a is connected to the source. The device size is larger than the transistors TP11 and TP12. Thereby, the parasitic capacitance with respect to the external output interface power supply potential VDH in the third level converter 10c becomes larger than that in the first level converter 10a. Therefore, since the transmission time of the third signal E is longer than that of the first signal B, the third signal E can be lowered later than the first signal B when the power is turned on.

  (3) A delay circuit 41 that delays the third signal E output from the third level converter 10c by a predetermined time is provided. The delay circuit 41 generates a delay signal Ed obtained by further delaying the third signal E that falls later than the first signal B. Based on this delay signal Ed, the fourth signal G is delayed more reliably than the first signal B by generating the brother 4 signal G in which the fall of the second signal D at the time of power-on is delayed. Can be lowered.

  (4) The power supply potential VDL on the semiconductor chip core side is always input as the signal V to the transistor TN31 of the third level converter 10c, and the L level signal VI is always input to the transistor TN32. Thereby, in a state where the voltage levels of the power supplies VDL and VDH are stable, the L-level third signal E is constantly output from the third level converter 10c. In addition, an OR circuit 42 that performs an OR operation between the L-level third signal E (delayed signal Ed) and the second signal D is provided. Therefore, the second signal D is output to the output circuit 30 as the fourth signal G from the OR circuit 42 to which the L-level third signal E is input in a state where the voltage levels of the power supplies VDL and VDH are stable. The Therefore, the newly added timing adjustment circuit TA (the third level converter 10c and the slow phase circuit 40) does not affect the operation of the output buffer circuit 1 in a state where the voltage levels of the power supplies VDL and VDH are stable.

(Second Embodiment)
Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. 5 and 6 focusing on differences from the first embodiment. The same members as those shown in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 5, in the output buffer circuit 2, instead of the delay phase circuit 40 of the output buffer circuit 1 of the first embodiment, a delay phase circuit 40a including a delay circuit 43, an AND circuit 44, and an OR circuit 42 is provided. Is provided.

  The delay circuit 43 is composed of an even number (two stages in FIG. 1) of inverter circuits connected in series. The delay circuit 43 delays the first signal B input from the first level converter 10 a for a predetermined time according to the number of stages of the inverter circuit, and outputs the delayed signal Bd to the AND circuit 44.

  The AND circuit 44 receives the third signal E from the third level converter 10c together with the delay signal Bd. The AND circuit 44 outputs to the OR circuit 42 a signal F having a result obtained by performing an AND operation on the delay signal Bd from the delay circuit 43 and the third signal E from the third level converter 10c.

  More specifically, when the L level third signal E is input as in the case where the voltage levels of the power supplies VDH and VDL are stable, the AND circuit 44 does not depend on the signal level of the delay signal Bd. The L level third signal E is output to the OR circuit 42 as the signal F. On the other hand, when the signals Bd and E of the rising level (H level) of the external output interface power supply potential VDH are input as when the power is turned on, the AND circuit 44 outputs the signal that has fallen to the L level first as the signal F. To the OR circuit 42. In the present embodiment, the element size ratio of the transistors TP31 and TP32 to the transistors TP11 and TP12 (twice here) and the delay circuit 43 so that the transmission time of the delay signal Bd is shorter than the third signal E. Delay time is set. Therefore, the AND circuit 44 outputs the delay signal Bd as the signal F to the OR circuit 42 when the power is turned on.

  The OR circuit 42 receives the second signal D from the second level converter 10b together with the signal F. The OR circuit 42 outputs a fourth signal G having a result obtained by performing an OR operation on the signal F from the AND circuit 44 and the second signal D from the second level converter 10 b to the output circuit 30.

  More specifically, when the L level third signal E is input from the AND circuit 44 as the signal F, as in the case where the voltage levels of the power supplies VDL and VDH are stable, the OR circuit 42 outputs the second signal. D is output to the output circuit 30 as the fourth signal G. Therefore, the newly added timing adjustment circuit TA (the third level converter 10c and the slow phase circuit 40a) does not affect the operation of the output buffer circuit 2 in a state where the voltage levels of the power supplies VDL and VDH are stable. On the other hand, when the signals D and F at the rising level (H level) of the external output interface power supply potential VDH are input as when the power is turned on, the OR circuit 42 outputs a signal that subsequently falls to the L level as the fourth signal. Output to the output circuit 30 as G.

  Next, the operation when the power supply of the output buffer circuit 2 configured as described above is turned on will be described with reference to FIG. Here, the case where the L level data input signal A and the control input signal C are input and the parasitic capacitance of the first level converter 10a is larger than the parasitic capacitance of the second level converter 10b will be described. .

  When the power is turned on, the signals AI, CI, and V that are supposed to be at the HL level rise following the rising level of the power supply potential VDL on the semiconductor chip core side. Until these signals AI, CI, and V exceed the threshold voltages of the transistors TN11, TN21, and TN31, as shown in FIG. 6A, the first to third signals B, D, and E are external output interfaces. It rises following the rising level of the power supply potential VDH (time t21 to t22). When the signal levels of the signals AI, CI, V exceed the threshold voltages of the transistors TN11, TN21, TN31, the transistors TN11, TN21, TN31 are turned on, and the first to third signals B, D, E are turned on. Is lowered to L level.

  At this time, since the parasitic capacitance of the first level converter 10a is larger than that of the second level converter 10b, the first signal B falls later than the second signal D (see times t22 and t23). The first signal B is output to the output circuit 30 and the delay circuit 43, and the second signal D is output to the OR circuit 42. The first signal B input to the delay circuit 43 is delayed by a predetermined time by the delay circuit 43 and output to the AND circuit 44 as a delay signal Bd. That is, the delay signal Bd falls at time t24 delayed by a predetermined time from time t23 when the first signal B falls.

  On the other hand, since the parasitic capacitance of the third level converter 10c is larger than that of the first level converter 10a, the third signal E that falls later than the first signal B is output from the third level converter 10c to the AND circuit 44. The Here, the AND circuit 44 outputs the signal that falls first to the L level among the third signal E and the delayed signal Bd, that is, the delayed signal Bd, is output to the OR circuit 42 as the signal F (see FIG. 6A). .

  Then, from the OR circuit 42 to which the second signal and the delay signal Bd are input, the signal that falls slowly to the L level among the second signal and the delay signal Bd, that is, the delay signal Bd is supplied to the output circuit 30 as the fourth signal. Is output (see FIG. 6B). As a result, the fourth signal G output from the second level converter 10b to the output circuit 30 falls later than the first signal B by the time (t24-t23), that is, by the delay time in the delay circuit 43. . Therefore, even if the second signal D falls earlier than the first signal B, the occurrence of the signal delay Skew of the first signal B with respect to the fourth signal G can be suppressed. Therefore, as shown in FIG. 6D, in the output buffer circuit 2 including the timing adjustment circuit TA, the malfunction signal SH is not generated as the output signal OUT.

According to the embodiment described above, the following effects are obtained in addition to the effects (2) and (4) of the first embodiment.
(5) The timing adjustment circuit TA including the third level converter 10c and the slow phase circuit 40a is provided. Based on the first signal B and the third signal E, the timing adjustment circuit TA generates a fourth signal in which the fall of the second signal at the time of power-on is delayed. That is, the timing adjustment circuit TA does not output the second signal D that falls earlier than the first signal B to the output circuit 30 when the power is turned on, and instead, the delay signal that falls later than the first signal B. Bd is output to the output circuit 30 as the fourth signal G. As a result, when the power is turned on, the fall of the fourth signal G output from the second level converter 10b to the output circuit 30 is detected, and the first signal B output from the first level converter 10a to the output circuit 30 is detected. It is possible to fall down more certainly than. Therefore, the generation of the signal delay Skew of the first signal B with respect to the fourth signal G can be suitably suppressed. This eliminates the timing at which both the signals JI and KI are at the L level when the power is turned on, so that the generation of the malfunction signal SH can be suitably suppressed.

  (6) When the transmission time of the first signal B is longer than that of the second signal D, an output circuit uses the delayed signal Bd obtained by delaying the first signal B as the fourth signal G instead of the second signal D. Output to 30. Thereby, after the first signal B falls, the fourth signal G output from the second level converter 10b side to the output circuit 30 can fall quickly (after the delay time by the delay circuit 43 elapses). Therefore, the period during which the H-level fourth signal G is output can be shortened. When the fourth signal G of H level is output, the node N60 of the final stage buffer 60 becomes high impedance.

(Third embodiment)
Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. The same members as those shown in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description of these elements is omitted.

  As shown in FIG. 7, the output buffer circuit 3 of the present embodiment has a configuration substantially similar to that of the conventional output buffer circuit 100. However, in the output buffer circuit 3, the transistors TP21 and TP22 in the second level converter circuit 22 are formed larger in size than the transistors TP11 and TP12 in the first level converter circuit 21. Specifically, the transistors TP21 and TP22 have an element size (for example, gate area) that is R times (R is a real number larger than 1 and doubled in the present embodiment) of the transistors TP11 and TP12. Thereby, the parasitic capacitance of the second level converter 10b becomes larger than the parasitic capacitance of the first level converter 10a. Accordingly, the transmission time of the second signal D is longer than that of the first signal B. Therefore, as shown in FIG. 8A, the second signal D output from the second level converter 10b is slower than the first signal B output from the first level converter 10a when the power is turned on. Fall to the level. That is, in FIG. 8A, the first signal B falls at time t31, and then the second signal D falls at time t32. As a result, the occurrence of the signal delay Skew of the first signal B with respect to the second signal D can be suppressed. Accordingly, as shown in FIG. 8C, the output buffer circuit 3 does not generate the malfunction signal SH as the output signal OUT.

According to the embodiment described above in detail, the following effects can be obtained.
(7) Transistors TP21 and TP22 whose external output interface power supply potential VDH in the second level converter 10b is connected to the source are transistors TP11 and TP11 whose external output interface power supply potential VDH in the first level converter 10a is connected to the source. The element size was formed to be larger than that of TP12. Thereby, the parasitic capacitance with respect to the external output interface power supply potential VDH in the second level converter 10b becomes larger than that in the first level converter 10a. Therefore, since the transmission time of the second signal D is longer than that of the first signal B, the second signal D can be lowered later than the first signal B when the power is turned on. Therefore, the occurrence of the signal delay Skew of the first signal B with respect to the second signal D can be suitably suppressed. This eliminates the timing at which both the signals JI and KI are at the L level when the power is turned on, so that the generation of the malfunction signal SH can be suitably suppressed.

(Other embodiments)
In addition, the said embodiment can also be implemented in the following aspects which changed this suitably.
In the first and second embodiments, the element size ratio of the transistors TP31 and TP32 to the transistors TP11 and TP12 is doubled, but the present invention is not limited to this. As the element size ratio of the transistors TP31 and TP32 with respect to the transistors TP11 and TP12 increases, the parasitic capacitance of the third level converter 10c becomes larger than that of the first level converter 10a. Therefore, the transmission time of the third signal E with respect to the first signal B becomes longer as the element size ratio of the transistors TP31 and TP32 with respect to the transistors TP11 and TP12 becomes larger.

  In the third embodiment, the element size ratio of the transistors TP21 and TP22 to the transistors TP11 and TP12 is doubled, but the present invention is not limited to this. As the element size ratio of the transistors TP21 and TP22 with respect to the transistors TP11 and TP12 increases, the transmission time of the second signal D with respect to the first signal B increases.

  The delay circuit 41 in the first embodiment may be omitted. In this case, the fourth signal G (second signal D) output from the second level converter 10b side to the output circuit 30 may be delayed based on the third signal E when the power is turned on. . As shown in FIG. 4B, the third signal E falls later than the first signal B of the first level converter 10a. Therefore, also by this third signal E, the fourth signal G output from the second level converter 10b side to the output circuit 30 is higher than the first signal B output from the first level converter 10a side to the output circuit 30. Can fall late.

  The delay circuit 43 in the second embodiment may be omitted. In this case, the fourth signal G (second signal D) output from the second level converter 10b side to the output circuit 30 may be delayed based on the first signal B when the power is turned on. . Thereby, when the power is turned on, the first signal B and the fourth signal G can be lowered to the L level substantially simultaneously.

In the above embodiments, the external output interface power supply potential VDH may be set to a voltage lower than the power supply potential VDL on the semiconductor chip core side.
The various embodiments described above can be summarized as follows.
(Appendix 1)
Based on a data input signal having an amplitude range between the first power supply potential and the reference potential, a first signal is generated that has an amplitude range between the second power supply potential different from the first power supply potential and the reference potential. A level converter,
A second level converter for generating a second signal having the amplitude range of the second power supply potential and the reference potential based on a control input signal having the amplitude range of the first power supply potential and the reference potential;
An output buffer circuit comprising: an output circuit that generates, as an output signal, a ternary value of the reference potential, the second power supply potential, and a high impedance based on the first signal and the second signal;
A third level converter that generates a third signal having an amplitude range of the second power supply potential and the reference potential based on an input signal having the amplitude range of the first power supply potential and the reference potential; Based on the third signal, a timing adjustment circuit is provided that generates a fourth signal by delaying the falling edge of the second signal when the power is turned on, and outputs the fourth signal to the output circuit,
The third level converter receives an input signal for outputting the third signal of the reference potential when the power is turned on.
The transistor connected to the source of the second power supply potential in the third level converter is formed larger than the transistor connected to the source of the second power supply potential in the first level converter. Output buffer circuit.
(Appendix 2)
2. The output buffer circuit according to appendix 1, wherein the timing adjustment circuit includes an OR circuit that generates the fourth signal having a result of an OR operation between the second signal and the third signal.
(Appendix 3)
The timing adjustment circuit includes a delay circuit that generates a delay signal obtained by delaying the third signal for a predetermined time, and outputs the delay signal to the OR circuit.
The output buffer circuit according to appendix 2, wherein the OR circuit generates the fourth signal having a result of an OR operation between the delay signal and the second signal.
(Appendix 4)
The timing adjustment circuit includes:
An AND circuit that generates a signal having a result of a logical product operation of the first signal and the third signal;
The output buffer circuit according to claim 1, further comprising an OR circuit that generates the fourth signal having a result of an OR operation between the signal generated by the AND circuit and the second signal.
(Appendix 5)
The timing adjustment circuit includes a delay circuit that generates a delay signal obtained by delaying the first signal for a predetermined time, and outputs the delay signal to the AND circuit.
The output buffer circuit according to appendix 4, wherein the AND circuit outputs a signal having a result of a logical product operation of the delay signal and the third signal to the OR circuit.
(Appendix 6)
6. The output buffer circuit according to any one of appendices 1 to 5, wherein an input signal for outputting the third signal having the reference potential is constantly input to the third level converter.
(Appendix 7)
Based on a data input signal having an amplitude range between the first power supply potential and the reference potential, a first signal is generated that has an amplitude range between the second power supply potential different from the first power supply potential and the reference potential. A level converter,
A second level converter for generating a second signal having the amplitude range of the second power supply potential and the reference potential based on a control input signal having the amplitude range of the first power supply potential and the reference potential;
An output buffer circuit comprising: an output circuit that outputs three values of the reference potential, the second power supply potential, and a high impedance as an output signal based on the first signal and the second signal;
The transistor connected to the source of the second power supply potential in the second level converter is formed larger than the transistor connected to the source of the second power supply potential in the first level converter. Output buffer circuit.

FIG. 3 is a circuit diagram illustrating an output buffer circuit according to the first embodiment. The circuit diagram which shows the internal structure of an output circuit. The wave form diagram which shows the operation | movement when a power supply level is stabilized. (A)-(e) is a wave form diagram which shows the operation | movement at the time of power-on of 1st Embodiment, respectively. A circuit diagram showing an output buffer circuit of a 2nd embodiment. (A)-(d) is a wave form diagram which shows the operation | movement at the time of power-on of 2nd Embodiment, respectively. A circuit diagram showing an output buffer circuit of a 3rd embodiment. (A)-(c) is a wave form diagram which shows the operation | movement at the time of power-on of 3rd Embodiment, respectively. The circuit diagram which shows the conventional output buffer circuit. (A)-(d) is a wave form diagram which shows the operation | movement at the time of the conventional power supply starting, respectively.

Explanation of symbols

A data input signal B first signal C control input signal D second signal E third signal G fourth signal Bd, Ed delay signal TA timing adjustment circuit TP11, TP12, TP21, TP22, TP31, TP32 Transistors 1, 2, 3 Output buffer circuit 10a First level converter 10b Second level converter 10c Third level converter 30 Output circuit 41, 43 Delay circuit 42 OR circuit 44 AND circuit

Claims (5)

Based on a data input signal having an amplitude range between the first power supply potential and the reference potential, a first signal is generated that has an amplitude range between the second power supply potential different from the first power supply potential and the reference potential. A level converter,
A second level converter for generating a second signal having the amplitude range of the second power supply potential and the reference potential based on a control input signal having the amplitude range of the first power supply potential and the reference potential;
An output buffer circuit comprising: an output circuit that generates, as an output signal, a ternary value of the reference potential, the second power supply potential, and a high impedance based on the first signal and the second signal;
A third level converter that generates a third signal having an amplitude range of the second power supply potential and the reference potential based on an input signal having the amplitude range of the first power supply potential and the reference potential; Based on the third signal, a timing adjustment circuit is provided that generates a fourth signal by delaying the falling edge of the second signal when the power is turned on, and outputs the fourth signal to the output circuit,
The third level converter receives an input signal for outputting the third signal of the reference potential when the power is turned on.
The transistor connected to the source of the second power supply potential in the third level converter is formed larger than the transistor connected to the source of the second power supply potential in the first level converter. Output buffer circuit.   2. The output buffer circuit according to claim 1, wherein the timing adjustment circuit includes an OR circuit that generates the fourth signal having a result of an OR operation between the second signal and the third signal. The timing adjustment circuit includes a delay circuit that generates a delay signal obtained by delaying the third signal for a predetermined time, and outputs the delay signal to the OR circuit.
3. The output buffer circuit according to claim 2, wherein the OR circuit generates the fourth signal having a result of an OR operation between the delay signal and the second signal. The timing adjustment circuit includes:
An AND circuit that generates a signal having a result of a logical product operation of the first signal and the third signal;
The output buffer circuit according to claim 1, further comprising: an OR circuit that generates the fourth signal having a result of an OR operation between the signal generated by the AND circuit and the second signal. . Based on a data input signal having an amplitude range between the first power supply potential and the reference potential, a first signal is generated that has an amplitude range between the second power supply potential different from the first power supply potential and the reference potential. A level converter,
A second level converter for generating a second signal having the amplitude range of the second power supply potential and the reference potential based on a control input signal having the amplitude range of the first power supply potential and the reference potential;
An output buffer circuit comprising: an output circuit that outputs three values of the reference potential, the second power supply potential, and a high impedance as an output signal based on the first signal and the second signal;
The transistor connected to the source of the second power supply potential in the second level converter is formed larger than the transistor connected to the source of the second power supply potential in the first level converter. Output buffer circuit.

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