JP2009246282A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces residual bubbles on a bonding surface of a semiconductor chip. <P>SOLUTION: The semiconductor device includes: a semiconductor chip 31; an adhesive agent 33 attached to the backside of the semiconductor chip 31; and a wiring substrate 11 that has an upper wiring 13 arranged on the substrate surface. The wiring substrate 11 includes a solder resist 17 that covers the upper wiring 13 and is connected with the adhesive agent 33, while having a groove 21 extending from a position opposite to the adhesive agent 33 to an external position of the lateral side of the adhesive agent 33 on the top side. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having a semiconductor chip bonded to a wiring board.

Semiconductor devices are required to have large capacity, multiple functions, low power consumption, small size, and the like, and at the same time, high reliability and low price are also required. In many cases, these characteristics can be achieved by using a wiring board or the like that can sufficiently draw out the characteristics of the semiconductor chip in addition to the characteristics of the semiconductor chip.

In order to reduce the price, for example, in a wiring board having a plate shape, it is common to form wiring on the uppermost surface which is the outermost surface and the bottom surface on the opposite side. Forming wiring on the front and bottom surfaces
It is often simpler than forming in a wiring board. In response to the demand for miniaturization, a wiring board that is as close as possible to the size of a semiconductor chip tends to be used, and the interval between adjacent wirings is becoming narrower and more complicated. When complicated wiring is performed, it is difficult to avoid the generation of a region (dead space) that cannot be used as a wiring region.

A dead space generated between complicated wirings formed on the wiring board causes a concave portion to be generated in the solder resist formed so as to cover the wiring. In order to reduce the dead space, for example, a method is disclosed in which a dummy pattern is formed to prevent the formation of a concave portion of the solder resist due to the thickness of the conductive pattern (wiring) (see, for example, Patent Document 1).

The disclosed dummy pattern has an effect of preventing air from being taken into the recesses that are relatively widely distributed under the adhesive surface at the center of the circuit element (semiconductor chip).
There is a problem in that it is not possible to cope with relatively small concave portions that are dispersed and generated in various places on the bonding surface of the semiconductor chip. In other words, if a small recess is formed and bubbles or the like are locally confined therein, the bubbles trapped during the thermal process undergo volume expansion, resulting in problems such as deterioration in the adhesion of the semiconductor chip and cracks in the semiconductor chip. Will occur,
The disclosed dummy pattern has a problem that it is difficult to suppress this local bubble entrapment.
Japanese Patent Laying-Open No. 2006-41019 (page 6, FIG. 5)

  The present invention provides a semiconductor device that suppresses residual bubbles on the bonding surface of a semiconductor chip.

A semiconductor device of one embodiment of the present invention includes a semiconductor chip, an adhesive attached to one surface of the semiconductor chip, and a wiring disposed on the surface, covering the wiring, and the adhesive And a wiring board having a solder resist on the surface of which a groove extending from the position facing the adhesive to the position outside the side portion of the adhesive is disposed.

ADVANTAGE OF THE INVENTION According to this invention, the semiconductor device which suppresses the bubble remaining on the adhesion surface of a semiconductor chip can be provided.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals.

A semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a diagram schematically showing the configuration of a semiconductor device. FIG. 1 (a) is a plan view showing the inside with a part cut away, and FIG. 1 (b) is an AA line in FIG. 1 (a). FIG. 2A and 2B are diagrams schematically showing a partial configuration of the semiconductor device. FIG. 2A is a plan view, and FIG. 2B is a cross-sectional view taken along the line BB in FIG. .

As shown in FIG. 1, the semiconductor device 1 includes a semiconductor chip 31, an adhesive 33 attached to the back surface, which is one surface of the semiconductor chip 31, and an upper wiring 13 disposed on the surface. Wiring 1
3 is connected to the adhesive 33 and has a solder resist 17 on the surface of which a groove 21 extending from a position facing the adhesive 33 to a position outside the side of the adhesive 33 is disposed. 11. The direction in which the semiconductor chip 31 is located with respect to the wiring board 11 is referred to as the upper side, the upper surface is referred to as the upper surface, and the opposite direction is referred to as the lower side.

The semiconductor device 1 also includes a connection terminal 14 connected to the upper wiring 13, a metal wire 41 that connects the connection terminal 14 and the semiconductor chip 31, a solder resist 17, a semiconductor chip 31,
And the sealing resin 43 covering the fine metal wire 41, the land 15 of the wiring board 11 on the opposite side of the sealing resin 43, the bump electrode 47 connected to the land 15, and the solder resist covering the land 15 18.

The wiring substrate 11 is a plate-like insulating substrate having an upper surface on which the semiconductor chip 31 is placed and an opposite lower surface, such as an epoxy resin, a polyimide resin, a glass / epoxy material, or ceramics. The wiring board 11 has a multilayer structure, and wiring can be installed inside.

As shown in FIG. 2, the upper wiring 13 which has a conductor, for example, Cu (copper) or Cu as a main component is arrange | positioned at the upper surface of the wiring board 11. As shown in FIG. A part of the upper wiring 13 is a semiconductor chip 31.
Lower part, that is, between the back surface of the semiconductor chip 31 and the upper surface of the wiring substrate 11, and a part of the upper wiring 13 is a position where the semiconductor chip 31 is placed (a semiconductor chip indicated by a two-dot chain line). It is drawn outside the boundary line 31a).

In order to connect a part of the upper wiring 13 drawn to the outside to the fine metal wire 41, the solder resist 17 is opened and the connection terminal 14 is formed. A part of the upper wiring 13 is connected to the land 15 through a through hole 45 penetrating the wiring board 11 in the vertical direction.
A lower wiring (not shown) can be disposed between the through hole 45 and the land 15.

The solder resists 17 and 18 are insulating resins and have thermosetting properties. In order to electrically protect the upper wiring 13 and the land 15, the solder resists 17, 18 are respectively outward from the upper and lower surfaces of these wirings, that is, above or below, for example, about 20
It is formed to have a film thickness of μm. In the solder resist 17, the connection terminal 14 is opened, and the solder resist 18 has an opening in the land 15. For example, the side surfaces of the solder resists 17 and 18 are formed substantially flush with the side surface of the wiring board 11.

For example, the solder resist 17 is applied to the surface of the wiring board 11 in a state of low viscosity at room temperature, and then cured by heating. The surface of the solder resist 17 above the upper wiring 13 is higher than the position of the surface of the solder resist 17 above the gap between the upper wirings 13. That is, in the solder resist 17, the recesses 23a and 23b are formed above the gap of the upper wiring 13 and inside the semiconductor chip boundary line 31a.

The concave portion 23b faces the semiconductor chip boundary line 31a, while the concave portion 23a indicates the one that enters inside from the semiconductor chip boundary line 31a. If the shape of the gap of the upper wiring 13 is the same, the recess 23a tends to become deeper within a certain range as the area of the gap increases. The recesses 23a and 23b are formed, for example, in a place where the through hole 45 is sandwiched between the upper wirings 13.

The grooves 21 on the surface of the solder resist 17 are, for example, formed in a lattice shape vertically and horizontally so as to draw a rectangle. The end of the groove 21 reaches the side surface of the solder resist 17, but the groove 21 has one end in the recess 23a at a position inside the semiconductor chip boundary line 31a, that is, the lower part of the semiconductor chip 31, and the semiconductor chip. What is necessary is just to extend so that it may have an other end outside the boundary line 31a. The interval (pitch) between adjacent grooves 21 is roughly the same as the interval between the upper wirings 13, but since it is formed vertically and horizontally, according to the pattern of the upper wiring 13,
It can be changed as appropriate. The pitch of the adjacent grooves 21 is not necessarily equal.

Moreover, although the shape of the groove | channel 21 is V shape which has a roundness in a bottom, the shape which consists of U shape, U shape which has an opening in upper part, or these combination, etc. are possible. The width of the groove 21 is, for example, about 5 μm, and the position of the bottom surface of the groove 21 is formed to be substantially the same height from the surface of the wiring board 11. That is, the depth of the groove 21 is, for example, about 5 μm where the surface position of the solder resist 17 is high, and the depth of the groove 21 is smaller than, for example, about 5 μm in the recesses 23a, 23b. When the recesses 23a and 23b are deeper than about 5 μm, the depth of the groove 21 can be adjusted to the extent that the groove 21 is carved. Moreover, it is preferable to adjust the depth of the groove | channel 21 with the thickness of the adhesive material 33, the viscosity at the time of adhesion | attachment, etc. The recess 23a,
Even if the groove 21 disappears in the deep part of 23b, the groove 21 communicating with the recesses 23a and 23b is formed, so that the remaining bubbles can be reduced.

The groove 21 is formed on the surface of the solder resist 17 using, for example, a mold (mold, plastic mold, etc., not shown) formed so as to become the desired groove 21 before the solder resist 17 is cured. It is possible to form by notching and then curing. By using the mold, the position of the bottom surface of the groove 21 can be made almost constant. Even if the bottom surface of the groove 21 is formed by pressing with the same shape, due to the difference in stress generated in the vicinity of the groove,
The amount pushed back when the mold is removed is different and is not necessarily formed in the same plane.

Further, for example, a photosensitive solder resist 17 can be used, and a desired groove 21 can be formed by a method of transferring a mask pattern by a photolithography method. In the photolithography method, grooves 2 having substantially the same depth are also formed on the upper surfaces of the deep recesses 23a and 23b.
1 can be formed.

The semiconductor chip 31 is fixed to a predetermined position on the upper surface of the solder resist 17 through, for example, a thermosetting film adhesive 33 attached to the back surface, that is, the adhesive surface.
The thickness of the adhesive material 33 is, for example, about 10 μm, and the side surface of the adhesive material 33 is formed so as to protrude substantially outward from the side surface of the semiconductor chip 31 to be slightly flush with the side surface.

The connection terminal 14 and the semiconductor chip 31 are connected by, for example, Au (gold) or a thin metal wire 41 whose main component is Au.

The sealing resin 43 covers the upper surface of the solder resist 17, the side surfaces of the adhesive 33, the side and upper surfaces of the semiconductor chip 31, and the fine metal wires 41, and the outer shape is formed in a substantially rectangular parallelepiped shape. Sealing resin 4
3 can be formed by molding, and has a side surface substantially flush with the side surface of the wiring substrate 11.

On the lower surface of the wiring substrate 11, bump electrodes 47 made of, for example, solder are formed on lands 15 connected to the lower wiring. The solder resist 18 is formed so as to cover the land 15 and the vicinity of the connection portion between the land 15 and the bump electrode 47.

The semiconductor device 1 having the above-described configuration can finally reduce bubbles temporarily left between the adhesive 33 on the back surface of the semiconductor chip 31 and the solder resist 17 as described below. Become.

The semiconductor device 1 has an adhesive 33 on the wiring substrate 11 on which the solder resists 17 and 18 are formed.
This is manufactured by a method of bonding the back surface of the semiconductor chip 31 to which is adhered. Solder resist 17
On the surface of the semiconductor chip 31, concave portions 23a and 23b exist in the gaps between the upper wirings 13, and one semiconductor chip 31 is provided.
The adhesive material 33 adhered to is substantially flat.

The wiring board 11 and the semiconductor chip 31 are juxtaposed so as to be substantially parallel, and both are brought into contact and pressed so as to maintain a parallel relationship, and a part of the adhesive 33 is deformed and temporarily bonded. By this pressing, the air present in the recesses 23b is discharged relatively easily through the grooves 21 along the surfaces of the solder resist 17 and the adhesive 33, outward from the semiconductor chip boundary line 31a. .

On the other hand, part of the air present in the recesses 23 a is initially discharged through a gap between the surface of the solder resist 17 and the surface of the adhesive 33. However, since the space between the two surfaces is gradually narrowed, the bubbles left in the closed recess 23a pass through the groove 21 and the semiconductor chip boundary line 3
It is discharged from 1a to the outside. Even if a part of the groove 21 is closed, the groove 21 is formed in a net shape, so that the possibility of finding a passage is higher than that of the groove formed independently.

The semiconductor device 1 also receives a relatively large pressure when the sealing resin 43 is molded. At this time, a part of the remaining air is discharged through the groove 21, and a part of the groove 21 is further closed. Then, the groove 21 located outside the semiconductor chip boundary line 31 a is sealed with a sealing resin 43.

As described above, the semiconductor device 1 forms the groove 21 on the upper surface of the solder resist 17 to discharge air from the recess 23 a formed in the gap of the upper wiring 13 to the outside of the bonding surface with the adhesive 33. And the remaining bubbles can be suppressed.

As a result, during a thermal process such as reflow soldering, the semiconductor device 1 generates a localized semiconductor chip 3 generated by volume expansion of trapped air and vaporization of moisture.
1, deterioration of the adhesiveness, cracks in the semiconductor chip 31, changes in element characteristics formed on the semiconductor chip 31, and the like can be reduced. The reliability of the semiconductor device 1 is improved.

Further, since the groove 21 can be formed on the upper surface of the solder resist 17 without being influenced by the upper wiring 13, the complicated upper wiring 13 can be designed relatively easily.

Further, since the solder resist 17 in which the groove 21 is formed and the adhesive 33 can partially remove the trapped air even after a part of the solder resist 17 is bonded, the surface of the adhesive 33 on the solder resist 17 side is flat. The property can be somewhat relaxed, and the material cost can be reduced.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

For example, in the embodiment, the groove on the upper surface of the solder resist is formed in a grid pattern vertically and horizontally so as to draw a rectangle. However, the groove can be a straight or curved groove that does not intersect. . Moreover, it is possible to make it the groove | channel which consists of the curve which cross | intersected in net shape.

Moreover, in the Example, although the semiconductor chip showed the example connected to the connection terminal of wiring through the metal thin wire from the two opposite sides, the metal chip from the four sides via the metal thin wire, It is possible to be connected to a connection terminal of a wiring formed at a position facing each side.

In the embodiment, an example in which one semiconductor chip is fixed to the upper surface of the solder resist has been described. However, a plurality of semiconductor chips are stacked, a plurality of semiconductor chips are arranged in parallel, or a plurality of semiconductor chips are stacked. The semiconductor chip can be fixed to the upper surface of the solder resist in a state where the stacked and parallel are combined.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows typically the structure of the semiconductor device based on the Example of this invention, FIG.1 (a) is a top view which notches one part and shows an inside, FIG.1 (b) is A of FIG.1 (a). Sectional drawing along line A. 2A and 2B are diagrams schematically illustrating a partial configuration of a semiconductor device according to an embodiment of the present invention, in which FIG. 2A is a plan view, and FIG. 2B is along a line BB in FIG. Sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 11 Wiring board 13 Upper wiring 14 Connection terminal 15 Land 17, 18 Solder resist 21 Groove 23a, 23b Recess 31 Semiconductor chip 31a Semiconductor chip boundary line 33 Adhesive material 41 Metal fine wire 43 Sealing resin 45 Through hole 47 Bump electrode

Claims (5)

A semiconductor chip;
An adhesive attached to one surface of the semiconductor chip;
A groove having a wiring disposed on a surface, covering the wiring, connected to the adhesive, and extending from a position facing the adhesive to an outer position on a side portion of the adhesive; A wiring board having a solder resist disposed in
A semiconductor device comprising: The semiconductor device according to claim 1, wherein the groove is formed in an orthogonal lattice shape on an upper surface of the solder resist. The semiconductor device according to claim 1, wherein the grooves are arranged at intervals similar to the intervals between the wirings. 4. The semiconductor device according to claim 1, wherein a cross section of the groove is formed in a V shape, a U shape, a U shape, or a combination thereof. 5. 5. The semiconductor device according to claim 1, wherein the groove has a constant bottom surface position or a constant depth of the groove. 6.

Images