JP2009237727A - Method for designing semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing a semiconductor integrated circuit in the consideration of a variation in a logic composition process. <P>SOLUTION: The method for designing the semiconductor integrated circuit includes steps of: specifying a variation value as a numerical value showing the variation of the delay time of cells; generating a netlist by a logic composition from circuit description; calculating a variation total by totaling variation values of cells configuring each of a plurality of paths reaching the input edge of a flip flop under consideration in the netlist; selecting the maximum value of the variation totals of the plurality of paths as a maximum variation total; selecting the worst value of timing slacks of the plurality of paths as the worst timing slack; and exchanging the cells of the netlist so that the maximum variation total can be decreased in a range in which the worst timing slack can be prevented from being worse than a predetermined slack value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present disclosure generally relates to computer-aided design, and more particularly to a method for designing a semiconductor integrated circuit using a computer.

  In the design process of a semiconductor integrated circuit, a circuit is first described by a hardware description language such as RTL (Register Transfer Level), logical synthesis is performed based on the circuit description such as RTL, and a netlist generated by the logical synthesis. Layout design based on the above. After this layout design, a final operation verification is performed by performing a timing verification taking into account the timing variation of each gate. When a timing violation is detected by the timing verification after the layout, the timing violation is solved by changing the layout. If the timing violation is not resolved even after changing the layout, the logic synthesis is executed again to change the netlist. However, in the logic synthesis stage, gate timing variation is not taken into account, so even if the logic synthesis is executed again and the netlist is changed, timing violation after the layout design may occur again. There is enough. For these reasons, there has been a problem that the design process is difficult to converge.

  FIG. 1 is a flowchart showing an outline of a conventional design process. In step S1 of FIG. 1, logic synthesis is performed by mapping the RTL description to the gate. That is, a net list indicating a logic gate circuit is automatically generated from the RTL description by using a logic synthesis tool. At this time, automatic circuit generation is performed so as to satisfy design constraint conditions such as area and power consumption.

  In step S2, timing optimization by timing analysis is executed. Each logic gate of the circuit generated in step S1 has a unique delay value. In step S2, the delay value of the logic gate circuit is obtained by adding the delay value of each logic gate. Based on this delay value, it is confirmed whether required timing conditions such as setup time and hold time at each flip-flop input terminal are satisfied. As a result of the confirmation, reconfiguration of the circuit, replacement of the logic gate element, and the like are executed for a portion where the timing condition is not satisfied. As a result, a netlist with optimized timing is generated.

  The above steps S1 and S2 correspond to a logic synthesis process. After this logic synthesis step, a physical synthesis step is executed.

  In step S3 in this physical synthesis process, layout design (place & route: arrangement & wiring) is performed based on the net list generated in the logic synthesis process, and timing optimization considering layout is executed. In layout design, cells (logic gates) are automatically arranged on a chip according to a net list of logic gate circuits, and wirings that connect the cells are drawn. In timing optimization, timing verification is performed based on the wiring resistance R, inductor L, and capacitance C, and the layout of the timing violation portion is changed to generate a layout with optimized timing.

  The sign-off verification process is executed after the physical synthesis process in step S3. The sign-off verification is verification performed after the layout design is completed, and is a final confirmation of whether or not the semiconductor integrated circuit satisfies a desired function or timing specification.

  In step S4 in the sign-off verification process, timing verification considering variation is executed. That is, by calculating the timing based on the library that defines the delay variation of each logic gate and the variation of the wiring RLC value, it is verified whether or not a desired timing condition is satisfied under the condition where the variation exists. . If a timing violation is detected as a result of the timing verification, the process returns to step S3 to change the layout. Although not shown in FIG. 1, as described above, if the timing violation is not eliminated even if the layout is changed, the logic synthesis is executed again to change the netlist.

The design process shown in FIG. 1 has a problem that the convergence in the timing verification (S4) considering the subsequent variations is poor because the variations are not considered at all in the logic synthesis step (S1, S2). That is, the layout change in S3 corresponding to the timing violation detection in S4 is repeatedly executed, and further, the logic synthesis corresponding to the timing violation detection in S4 is repeatedly executed repeatedly. There is a case.
JP 7-334530 A

  In view of the above, a method for designing a semiconductor integrated circuit in consideration of variations in the logic synthesis process is desired.

  In a semiconductor integrated circuit design method, a variation value, which is a numerical value indicating variation in delay time of a cell, is defined for each cell type, a net list is generated by logic synthesis from a circuit description, and a flip-flop of a target flip-flop in the net list is generated. For each of a plurality of paths reaching the input end, the variation values of the cells constituting the path are summed to calculate a variation sum, and the largest of the variation sums of the plurality of paths is selected as the maximum variation sum. The worst timing slack of the plurality of paths is defined as the worst timing slack, and the netlist cell is set so as to reduce the maximum variation total within a range in which the worst timing slack does not deteriorate below a predetermined slack value. Includes each stage to be replaced.

  According to at least one embodiment, the maximum sum of variations among a plurality of paths is regarded as the maximum variation sum, and the maximum variation sum is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value. As a result, it is possible to realize timing optimization processing in consideration of variations in the logic synthesis process.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 2 is a flowchart showing a method for designing a semiconductor integrated circuit in consideration of variations in the logic synthesis process. The processing shown in the flowchart of FIG. 2 is executed by a computer as will be described later.

  In step S1 of FIG. 2, logic synthesis is performed by mapping the RTL description to the gate. That is, a net list indicating a logic gate circuit is automatically generated from the RTL description by using a logic synthesis tool. At this time, automatic circuit generation is performed so as to satisfy design constraint conditions such as area and power consumption.

  In step S2, the maximum total variation of all flip-flops (FF) is calculated. The total maximum variation is calculated with reference to the cell type variation database 10 in which variation values, which are numerical values indicating variations in cell delay time, are defined for each cell type.

  FIG. 3 is a diagram for explaining the calculation of the maximum variation total. FIG. 3 shows a circuit corresponding to a net list generated by logic synthesis. The circuit in FIG. 3 includes flip-flops 11 to 16, NAND circuits 20 to 23, and inverters 24 and 25. A description such as “NAND3” or “INV3” shown below each gate element that is a NAND circuit or an inverter indicates the type of the corresponding gate element.

  FIG. 4 is a diagram illustrating the cell type variation data 31 for the NAND circuit in the cell type variation database 10. The cell type variation data 31 indicates relative variation values for the three types of NAND circuits NAND1, NAND2, and NAND3. These relative variation values indicate that the larger the value, the greater the variation in delay time at the gate. The ratio between the relative variation values may be the ratio of the delay time variation. For example, the variation in delay time of NAND1 having a relative variation value of 4 may be ± 2 ns, and the variation in delay time of NAND2 having a relative variation value of 5 may be ± 2.5 ns. As described above, the relative variation value is a value relatively indicating variation in delay time of the gate element when the variation in reference delay time is 1. For example, it is assumed that there is a kind of inverter having an element with the smallest variation in delay time, and the variation D in delay time of the inverter is used as a reference. In this case, the relative variation value of a certain gate element may be a value obtained by dividing the variation in delay time of the gate element by D.

  The cell type variation data 31 further indicates a relative delay value, which is a relative delay time, for three types of NAND circuits. These relative delay values indicate that the larger the value, the longer the delay time at the gate. The ratio between the relative delay values may be the ratio of the delay time. For example, the delay time of NAND1 having a relative delay value of 4 may be ± 2 ns, and the delay time of NAND2 having a relative delay value of 3 may be ± 1.5 ns. Thus, the relative delay value is a value that relatively indicates the delay time of the gate element when the reference time is 1. For example, it is assumed that an element having a minimum delay time is a certain type of inverter, and the delay time D of this inverter is used as a reference. In this case, the relative delay value of a certain gate element may be a value obtained by dividing the delay time of the gate element by D. For example, if the reference time is one clock cycle, the relative delay value is a value obtained by measuring the delay time by the number of clock cycles.

  FIG. 5 is a diagram showing the cell type variation data 32 for the inverter in the cell type variation database 10. The cell type variation data 32 indicates relative variation values and relative delay values for three types of inverters INV1, INV2, and INV3. The meanings of the relative variation value and the relative delay value are the same as in the NAND circuit.

  In FIG. 3, the numerical value shown inside each gate element is the relative variation value shown in FIG. 4 or FIG. That is, for example, since the type of the NAND circuit 21 is NAND3, it can be seen from FIG. 4 that the relative variation value is 10. This value 10 is written in the circuit symbol of the NAND circuit 21.

  In the calculation of the maximum variation total in step S2 of FIG. 2, for each of a plurality of paths reaching the input terminal of the target flip-flop in the netlist, the variation value of the cells constituting the path is totaled to calculate the total variation. The largest one of the total variations of the paths is selected as the maximum variation total. If the flip-flop 11 is the target flip-flop, there are five paths to the input end. That is, the first path from the output of the flip-flop 12 to the input of the flip-flop 11, the second path from the output of the flip-flop 13 to the input of the flip-flop 11, and the output of the flip-flop 14 to the input of the flip-flop 11. A fourth path from the output of the flip-flop 15 to the input of the flip-flop 11, and a fifth path from the output of the flip-flop 16 to the input of the flip-flop 11. Summing up the variation values of the cells that make up the path for each of these five paths is 32 for the first path, 42 for the second path, 42 for the third path, and for the fourth path. 20 for the fifth pass. Among these five path variation sums 32, 42, 42, 20, and 20, the maximum value 42 is selected as the maximum variation sum. Similarly, the maximum variation sum is obtained for all flip-flops related to the netlist.

  Next, in step S3 of FIG. 2, timing optimization by timing analysis is executed. Each logic gate of the circuit generated in step S1 has a unique delay value. In step S2, the delay value of the logic gate circuit is obtained by adding the delay value of each logic gate. Based on this delay value, it is confirmed whether required timing conditions such as setup time and hold time at each flip-flop input terminal are satisfied. As a result of the confirmation, reconfiguration of the circuit, replacement of the logic gate element, and the like are executed for a portion where the timing condition is not satisfied. As a result, a netlist with optimized timing is generated.

  In step S4, a variation optimization process for improving the maximum variation total is executed. Specifically, for the flip-flop of interest, the worst timing slack of the plurality of paths is the worst timing slack. Then, the netlist cells are switched so that the maximum variation total is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value.

  FIG. 6 is a diagram for explaining the worst timing slack. 6 shows the same circuit as FIG. 3, and the same components as those of FIG. 3 are referred to by the same numerals, and a description thereof will be omitted. In FIG. 6, the numerical value shown on each gate element which is a NAND circuit or an inverter is a relative delay value shown in FIG. 4 or FIG. That is, for example, since the NAND circuit 21 is of NAND3 type, it can be seen from FIG. 4 that the relative delay value is 2. This value 2 is written on the circuit symbol of the NAND circuit 21.

  For each of the first to fifth paths described above, the total value of the relative delay values is 6, 8, 8, 4, and 4. The timing slack of a certain path is the difference between the actual arrival time of the signal at the end point of the path and the required arrival time. That is, the timing slack is the difference between the time at which a signal reaches the end point of the path and the latest time at which the signal should reach the end point in order to satisfy the timing requirements. For example, it is assumed that the flip-flops 12 to 16 output a signal at the same timing (time T = 0), and the required arrival time that the signal should reach at the input terminal of the flip-flop 11 is T = 13. . T = 13 is a numerical value representing time in the same unit as the relative delay value. That is, for example, when the reference delay time is D, the time interval from the signal output timing time (T = 0) to the required arrival time is divided by D to be 13. In this case, the timing slack of the first path from the output of the flip-flop 12 to the input of the flip-flop 11 is 7 (= 13−6). Similarly, the timing slack of the second path from the output of the flip-flop 13 to the input of the flip-flop 11 is 5 (= 13−8). The timing slack of the third path from the output of the flip-flop 14 to the input of the flip-flop 11 is 5 (= 13−8). The timing slack of the fourth path from the output of the flip-flop 15 to the input of the flip-flop 11 is 9 (= 13−4). Further, the timing slack of the fifth path from the output of the flip-flop 16 to the input of the flip-flop 11 is 9 (= 13−4).

  As described above, in the variation optimization process in step S4 of FIG. 2, the worst timing slack of the plurality of paths is set to the worst timing slack. The timing slack of the five paths is 7, 5, 5, 9, and 9. The smaller the value of the timing slack, the less timing there is. Therefore, the worst timing slack among the five timing slacks is 5. In the variation optimization process in step S4, the netlist cells are switched so that the maximum variation total is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value. For example, the netlist cells are switched within a range in which the worst timing slack does not become smaller than zero. If the worst timing slack is 0 or more, the required timing requirement is satisfied. However, if the worst timing slack becomes negative, the required timing requirement is not satisfied. Therefore, replacing the netlist cells within a range in which the worst timing slack does not become smaller than 0 means that the maximum variation sum is reduced within a range in which the required timing requirement is satisfied. Further, for example, the net list cells may be switched within a range in which the worst timing slack does not become smaller than 1 with a margin. The replacement of netlist cells will be described in detail later.

  Steps S1 to S4 described above in FIG. 2 correspond to the logic synthesis step. After this logic synthesis step, a physical synthesis step is executed.

  In step S5 in this physical synthesis process, layout design (place & route: arrangement & wiring) is performed based on the net list generated in the logic synthesis process, and timing optimization considering layout is executed. In layout design, cells (logic gates) are automatically arranged on a chip according to a net list of logic gate circuits, and wirings that connect the cells are drawn. In timing optimization, timing verification is performed based on the wiring resistance R, inductor L, and capacitance C, and the layout of the timing violation portion is changed to generate a layout with optimized timing.

  The sign-off verification process is executed after the physical synthesis process in step S5. In step S6 in the sign-off verification process, timing verification considering variation is executed. That is, by calculating the timing based on the library that defines the delay variation of each logic gate and the variation of the wiring RLC value, it is verified whether or not a desired timing condition is satisfied under the condition where the variation exists. . If a timing violation is detected as a result of the timing verification, the process returns to step S5 to change the layout. Although not shown in FIG. 2, if the timing violation is not eliminated by changing the layout, logic synthesis may be executed again to change the netlist.

  The following describes a process of replacing netlist cells so that the maximum variation sum is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value. In this process, the cells sequentially found may be replaced by tracing a plurality of paths upstream from the input end of the flip-flop.

  Taking the circuit of FIG. 6 as an example, when tracing the path upstream from the input end of the flip-flop 11, the NAND circuit 23 is first found. Therefore, this NAND circuit 23 is a target of the cell replacement process. The type of NAND circuit 23 is NAND3. Referring to FIG. 4, it can be seen that NAND1 and NAND2 can be used as NAND circuits having a relative variation value smaller than that of NAND3. In this case, since the relative variation value of NAND1 is smaller, it is first considered to replace the NAND circuit 23 with NAND1. At this time, worst timing slack is calculated when the target cell is replaced with another type of cell having a smaller variation value, and it is determined whether or not the calculated worst timing slack is worse than a predetermined slack value.

  FIG. 7 is a diagram for explaining replacement of cells. In FIG. 7, the same elements as those of FIG. 6 are referred to by the same numerals, and a description thereof will be omitted.

  The circuit shown in FIG. 7 differs from the circuit shown in FIG. 6 in that the NAND circuit 23 of the type NAND3 is replaced with a NAND circuit 23A of the type NAND1. The NAND circuit 23 has a relative variation value of 10 and a relative delay value of 2, whereas the NAND circuit 23A has a relative variation value of 4 and a relative delay value of 4. By this cell replacement, the maximum variation total is reduced (improved) from 42 to 36, and the worst timing slack is reduced (deteriorated) from 5 to 3 (= 13-10). That is, the worst timing slack is 3 when the target cell is replaced with another type of cell having a smaller variation value. If the predetermined slack value is 0, this worst timing slack is better (larger) than the predetermined slack value. Therefore, the process of replacing the NAND circuit 23 of the type NAND3 with the NAND circuit 23A of the type NAND1 reduces the maximum variation total within a range where the worst timing slack does not become worse than the predetermined slack value. Therefore, this replacement process is executed as an effective process, and the net list is changed.

  Thereafter, when the path is traced upstream from the input end of the flip-flop 11, for example, the NAND circuit 22 is found next. Therefore, this NAND circuit 22 is a target of cell replacement processing. When branching into a plurality of paths as it goes upstream, each of the plurality of paths may be checked in order. At this time, the processing may be configured such that a path corresponding to the maximum variation total is stored, and cells not on this path are excluded from replacement targets.

  The type of NAND circuit 22 is NAND3. Referring to FIG. 4, it can be seen that NAND1 and NAND2 can be used as NAND circuits having a relative variation value smaller than that of NAND3. In this case, since the relative variation value of NAND1 is smaller, it is first considered to replace the NAND circuit 22 with NAND1.

  FIG. 8 is a diagram for explaining replacement of cells. In FIG. 8, the same components as those of FIG. 7 are referred to by the same numerals, and a description thereof will be omitted.

  The circuit shown in FIG. 8 differs from the circuit shown in FIG. 7 in that the NAND circuit 22 of the type NAND3 is replaced with a NAND circuit 22A of the type NAND1. By this cell replacement, the maximum variation sum remains 36, and the worst timing slack remains 3. Therefore, the process of replacing the NAND circuit 22 of the type NAND3 with the NAND circuit 22A of the type NAND1 is a process in a range where the worst timing slack does not become worse than the predetermined slack value (0 in this example). Therefore, this replacement process is executed as an effective process, and the net list is changed. In this cell replacement process, the maximum variation total 36 does not decrease, although the worst timing slack is within a range that does not become worse than the predetermined slack value. In such a case, the procedure may be such that the netlist is not changed.

  Thereafter, when the path is traced upstream from the input terminal of the flip-flop 11, for example, the inverter 25 is found next. Therefore, the inverter 25 is a target of the cell replacement process.

  The type of the inverter 25 is INV3. Referring to FIG. 5, it can be seen that INV1 and INV2 can be used as inverters having a relative variation value smaller than that of INV3. In this case, since the relative variation value of INV1 is smaller, it is first considered to replace the inverter 25 with INV1.

  FIG. 9 is a diagram for explaining replacement of cells. 9, the same components as those of FIG. 8 are referred to by the same numerals, and a description thereof will be omitted.

  The circuit shown in FIG. 9 is different from the circuit shown in FIG. 8 in that an inverter 25 of type INV3 is replaced with an inverter 25A of type INV1. By this cell replacement, the maximum variation total is 36 to 32, and the worst timing slack is 3 to 1 (= 13-12). Therefore, the process of replacing the inverter 25 of the type INV3 with the inverter 25A of the type INV1 reduces the maximum variation sum by a process in which the worst timing slack is not worse than the predetermined slack value (0 in this example). . Therefore, this replacement process is executed as an effective process, and the net list is changed.

  Thereafter, when the path is traced further upstream from the input end of the flip-flop 11, for example, the inverter 24 is found next. Therefore, the inverter 24 is a target for cell replacement processing.

  The type of the inverter 24 is INV3. Referring to FIG. 5, it can be seen that INV1 and INV2 can be used as inverters having a relative variation value smaller than that of INV3. In this case, since the relative variation value of INV1 is smaller, it is first considered to replace the inverter 24 with INV1.

  FIG. 10 is a diagram for explaining the replacement of cells. 10, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted.

  The circuit shown in FIG. 10 is different from the circuit shown in FIG. 9 in that the inverter 24 of type INV3 is replaced with an inverter 24A of type INV1. By this cell replacement, the maximum variation sum is 32 to 28, and the worst timing slack is 1 to -1 (= 13-14). Therefore, the process of replacing the inverter 24 of type INV3 with the inverter 24A of type INV1 is a process in which the worst timing slack becomes worse than a predetermined slack value (0 in this example). Therefore, this replacement process is invalid and the netlist is not changed.

  Referring to FIG. 5 again, since it has been found that INV1 cannot be used among INV1 and INV2 that can be used as inverters having a relative variation value smaller than INV3, whether INV2 can be used next is examined.

  FIG. 11 is a diagram for explaining replacement of cells. In FIG. 11, the same components as those of FIG. 9 are referred to by the same numerals, and a description thereof will be omitted.

  The circuit shown in FIG. 11 differs from the circuit shown in FIG. 9 in that the inverter 24 of type INV3 is replaced with an inverter 24B of type INV2. By this cell replacement, the maximum variation total is 32 to 29, and the worst timing slack is 1 to 0 (= 13-13). Therefore, the process of replacing the inverter 24 of the type INV3 with the inverter 24B of the type INV2 reduces the maximum variation total in a process in which the worst timing slack is not worse than a predetermined slack value (0 in this example). . Therefore, this replacement process is executed as an effective process, and the net list is changed.

  As described above, cells sequentially found by tracing a plurality of paths upstream from the input end of the flip-flop are considered as replacement targets. By exchanging, the net list is changed so that the maximum variation total is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value. For example, the process may be repeated until there is no cell to be replaced or no further effective replacement process is possible, and the maximum variation total may be reduced. Alternatively, the processing may be terminated when the maximum variation total becomes a predetermined value or less.

  The difference between the semiconductor integrated circuit design method shown in FIG. 1 and the semiconductor integrated circuit design method shown in FIG. 2 will be described below. FIG. 12 is a diagram illustrating an example of a circuit to be designed. The circuit shown in FIG. 12 includes flip-flops 41 and 42 and 40 inverters 43-1 to 43-40. A signal output from the output terminal of the flip-flop 41 propagates through the 40-stage inverters 43-1 to 43-40 connected in series and reaches the input terminal of the flip-flop 42.

  FIG. 13 is a diagram for explaining the data capture timing of the flip-flop 42. In FIG. 13A, the data signal data is output from the output terminal of the flip-flop 41 at time T = 0, and the data signal is synchronized with the rising edge of the clock signal clk at the input terminal of the flip-flop 42 at time T = 10. Capture. In FIG. 13A, the length of the bar 51 hatched with diagonal lines in the column of the data signal data indicates the propagation time (delay time) of the data signal data from the output end of the flip-flop 41 to the input end of the flip-flop 42. ). That is, data output from the output terminal of the flip-flop 41 at T = 0 reaches the input terminal of the flip-flop 42 at T = 5. A hatched bar 52 shown in the column of the data signal data indicates a time during which the data signal data is valid at the input terminal of the flip-flop 42. An arrow 53 indicates the setup time of the flip-flop 42. Therefore, for example, if the length of the arrow is 2.5, the required arrival time that the data signal should reach at the input terminal of the flip-flop 42 is T = 7.5. Since the data signal data reaches the input terminal of the flip-flop 42 before the request arrival time T = 7.5, the request timing is satisfied.

  The logic synthesis step in the semiconductor integrated circuit design method of FIG. 1 considers only that the required timing is satisfied without considering variations. Therefore, when the timing relationship as shown in FIG. 13A is satisfied, the logic synthesis process is completed. However, after that, when timing verification is performed in consideration of variations in the sign-off process, for example, a timing violation as shown in FIG. 13B is detected. In FIG. 13B, the bar 54 indicates variations in the arrival time of the data signal data. Since the right end of the bar 54 is located later in time than the left end of the arrow 53, the required timing is not satisfied under the worst conditions. In order to converge such timing violations, it is necessary to change the layout or redo the logic synthesis, and the convergence of the design process is poor.

  FIG. 14 is a diagram for explaining timing optimization by the design process of the semiconductor integrated circuit of FIG. 14, the same parts as those in FIG. 13 are referred to by the same numerals, and a description thereof will be omitted. FIG. 14A is a diagram similar to FIG. 13B, and the length of the bar 51 hatched with diagonal lines indicates the length of the data signal data from the output end of the flip-flop 41 to the input end of the flip-flop 42. The propagation time (delay time) is shown. A hatched bar 52 indicates a time during which the data signal data is valid at the input end of the flip-flop 42. An arrow 53 indicates the setup time of the flip-flop 42. Since the right end of the bar 54 indicating the variation in the arrival time of the data signal data is located temporally after the left end of the arrow 53, the required timing is not satisfied under the worst condition.

  The logic synthesis step in the semiconductor integrated circuit design method of FIG. 2 performs timing optimization in consideration of variations. Therefore, the illegal timing relationship as shown in FIG. 14A can be corrected to the timing relationship as shown in FIG. 14B in the logic synthesis step. That is, in the circuit shown in FIG. 12, the cells (inverters) are replaced so that the maximum total variation is reduced. At this time, cell replacement is performed within a range in which the worst timing slack does not become worse than a predetermined slack value. In FIG. 14B, the length of the bar 61 hatched with diagonal lines indicates the propagation time (delay time) of the data signal data increased by cell replacement. A hatched bar 62 indicates the time that the data signal data is valid at the input end of the flip-flop 42. Since the replacement of the cells is executed within a range in which the worst timing slack does not become worse than a predetermined slack value (for example, 0), the data signal data reaches the input terminal of the flip-flop 42 before the required arrival time T = 7.5. It is guaranteed that

  In FIG. 14B, the bar 64 indicates the variation in the arrival time of the data signal data. Due to the cell replacement process, the width of the bar 64 in FIG. 14B is reduced compared to the width of the bar 54 in FIG. That is, the maximum variation total is decreasing. As a result, the right end of the bar 64 is positioned in time before the left end of the arrow 53, so that the required timing is satisfied even in the worst condition. As described above, timing optimization is performed in consideration of variations in the logic synthesis process, so that the convergence of timing violation is improved in timing verification considering variations in the subsequent sign-off process.

  FIG. 15 is a diagram showing a configuration of an apparatus for executing a semiconductor integrated circuit design method according to the present invention.

  As shown in FIG. 15, the apparatus for executing the semiconductor integrated circuit design method is realized by a computer such as a personal computer or an engineering workstation. 15 includes a computer 510, a display device 520 connected to the computer 510, a communication device 523, and an input device. The input device includes a keyboard 521 and a mouse 522, for example. The computer 510 includes a CPU 511, a RAM 512, a ROM 513, a secondary storage device 514 such as a hard disk, a replaceable medium storage device 515, and an interface 516.

  The keyboard 521 and the mouse 522 provide an interface with the user, and various commands for operating the computer 510, user responses to requested data, and the like are input. The display device 520 displays the results processed by the computer 510 and displays various data to enable interaction with the user when operating the computer 510. The communication device 523 is for performing communication with a remote place, and includes, for example, a modem or a network interface.

  A method for designing a semiconductor integrated circuit is provided as a computer program executable by the computer 510. This computer program is stored in the storage medium M that can be mounted on the replaceable medium storage device 515, and is loaded from the storage medium M to the RAM 512 or the secondary storage device 514 via the replaceable medium storage device 515. Alternatively, the computer program is stored in a remote storage medium (not shown), and is loaded from the storage medium to the RAM 512 or the secondary storage device 514 via the communication device 523 and the interface 516.

  When there is a program execution instruction from the user via the keyboard 521 and / or the mouse 522, the CPU 511 loads the program from the storage medium M, the remote storage medium, or the secondary storage device 514 to the RAM 512. The CPU 511 uses the free storage space of the RAM 512 as a work area, executes the program loaded in the RAM 512, and advances the process while appropriately interacting with the user. The ROM 513 stores a control program for controlling basic operations of the computer 510.

  By executing the computer program, the computer 510 executes the semiconductor integrated circuit design method as described in the above embodiments.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

It is a flowchart which shows the outline of the conventional design process. 5 is a flowchart illustrating a method for designing a semiconductor integrated circuit in consideration of variations in a logic synthesis process. It is a figure for demonstrating calculation of the largest variation total. It is a figure which shows the variation data for every cell type about the NAND circuit in the variation database for every cell type. It is a figure which shows the variation data for every cell type about the inverter in the variation database for every cell type. It is a figure for demonstrating worst timing slack. It is a figure for demonstrating replacement of a cell. It is a figure for demonstrating replacement of a cell. It is a figure for demonstrating replacement of a cell. It is a figure for demonstrating replacement of a cell. It is a figure for demonstrating replacement of a cell. It is a figure which shows an example of the circuit of design object. It is a figure for demonstrating the data acquisition timing of a flip-flop. FIG. 3 is a diagram for explaining timing optimization by a design process of the semiconductor integrated circuit of FIG. 2. It is a figure which shows the structure of the apparatus which performs the design method of the semiconductor integrated circuit by this invention.

Explanation of symbols

10 Cell type variation database 11 to 16 Flip-flops 20 to 23 NAND circuits 24 and 25 Inverter 31 Cell type variation data 32 Cell type variation data 510 Computer 511 CPU
512 RAM
513 ROM
514 Secondary storage device 515 Exchangeable media storage device 516 Interface 520 Display device 521 Keyboard 522 Mouse 523 Communication device

Claims (5)

A variation value, which is a numerical value indicating variation in the delay time of the cell, is defined for each cell type,
A net list is generated from the circuit description by logic synthesis,
For each of a plurality of paths leading to the input terminal of the target flip-flop in the netlist, the variation value of the cells constituting the path is summed to calculate a variation sum, and the largest of the variation sums of the plurality of paths is calculated. Select the thing as the maximum variation total,
The worst timing slack of the plurality of paths is set as the worst timing slack, and the cells of the netlist are switched so that the maximum variation total is reduced within a range in which the worst timing slack does not become worse than a predetermined slack value. A method of designing a semiconductor integrated circuit including each stage. A layout design based on the netlist with the cells replaced,
2. The method of designing a semiconductor integrated circuit according to claim 1, further comprising each step of performing timing verification in consideration of variations with respect to a circuit having a layout generated by the layout design.   2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the step of replacing the cells is a step of replacing cells sequentially found by tracing the plurality of paths upstream from the input end. The step of replacing the cells is as follows:
Calculating the worst timing slack when the target cell is replaced with another type of cell having a smaller variation value;
2. The method for designing a semiconductor integrated circuit according to claim 1, further comprising: determining whether the calculated worst timing slack is worse than the predetermined slack value.   2. The method of designing a semiconductor integrated circuit according to claim 1, wherein the predetermined slack value is zero.

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