JP2009075822A - Semiconductor circuit design apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor circuit design apparatus capable of optimizing a signal delay time, in consideration of an environment of cells disposed on a signal path. <P>SOLUTION: The semiconductor circuit design apparatus includes a circuit information storage unit, a cell information storage unit for storing the dispersion of the signal delay time of the cell caused by the variation of the set environment of the cell disposed on the signal path, a timing calculation unit for calculating the signal delay time of the signal path logically synthesized, an analysis unit for analyzing the variation of the set environment of the set points of a plurality of existing cells set on a certain signal path, an extraction part for extracting, from the cell information storage unit, a plurality of substitution cells so as to minimize the sum of the dispersion distribution of signal delay times in regard to the set environment of each cell while the sum of signal delay times of each cell on the signal path is maintained within a target range of the signal delay time of the path, and a substitution unit for substituting the plurality of substitution cells for the plurality of existing cells. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor circuit design apparatus.

  A semiconductor integrated circuit device such as an LSI has a signal path that connects between semiconductor elements constituting the device and transmits signals between the semiconductor elements. In the signal path, logic cells such as buffers, logic gates, and flip-flops are interposed. The logic cell has a certain delay time and delays the signal by the delay time. The delay time in a logic cell varies depending on the surrounding environment where the logic cell is arranged.

  However, the conventional semiconductor integrated circuit design apparatus has not optimized the delay time in consideration of changes in the surrounding environment. When the delay time due to changes in the surrounding environment is not taken into account, the timing variation of the signal in the entire signal path cannot be reduced.

  In addition, when the variation in delay time due to the change in the surrounding environment of each logic cell is not taken into account, a large size logic cell is used in order to cope with the worst case guarantee of the signal timing variation. However, increasing the size of the logic cell causes an increase in the chip size of the semiconductor integrated circuit.

  Provided is a semiconductor circuit design apparatus capable of reducing variations in signal delay time in consideration of the surrounding environment of logic cells arranged in a signal path.

  A semiconductor circuit design apparatus according to an embodiment of the present invention is a semiconductor circuit design apparatus for designing a signal path between elements constituting a semiconductor integrated circuit, and stores circuit information for storing circuit information of the semiconductor integrated circuit. A cell information storage unit for storing a variation in a cell delay time indicating a delay time of the logic cell due to a change in a setting environment of the logic cell arranged on the signal path, and logic synthesis based on the circuit information A timing calculation unit for calculating a delay time indicating the delay time of the signal path, an analysis unit for analyzing a change in a setting environment of a set location of a plurality of existing logic cells set on the signal path, and the cell When a plurality of logic cells stored in the information storage unit are set on the signal path, a delay time variation distribution related to the setting environment is set on the signal path. An extraction unit that extracts a plurality of replacement logic cells that cancel each other so as to approach the sum of the average values of the cell delay times of the plurality of logic cells, and a replacement that replaces the plurality of existing logic cells with the plurality of replacement logic cells Department.

  A semiconductor circuit design apparatus according to an embodiment of the present invention is a semiconductor circuit design apparatus for designing a signal path between elements constituting a semiconductor integrated circuit, and stores circuit information for storing circuit information of the semiconductor integrated circuit. A cell information storage unit for storing a variation in a cell delay time indicating a delay time of the logic cell due to a change in a setting environment of the logic cell arranged on the signal path, and logic synthesis based on the circuit information A timing calculation unit for calculating a delay time indicating the delay time of the signal path, an analysis unit for analyzing a change in a setting environment of a set location of a plurality of existing logic cells set on the signal path, and the setting An extraction unit for extracting a replacement logic cell having a variation distribution of delay time related to the environment smaller than that of the existing logic cell, and replacement for replacing the existing logic cell with the replacement logic cell It is equipped with a door.

  The semiconductor circuit design apparatus according to the present invention can reduce the variation in the signal delay time in consideration of the surrounding environment of the logic cell arranged in the signal path.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing an example of the configuration of the semiconductor integrated circuit design apparatus according to the first embodiment of the present invention. The semiconductor integrated circuit design apparatus includes a circuit information storage unit 10, a cell information storage unit 20, a target timing calculation unit 30, a path timing calculation unit 40, an environment analysis unit 60, a cell extraction unit 70, and a cell replacement unit. 80 and a circuit information output unit 90.

  A semiconductor integrated circuit design apparatus designs a signal path wiring structure in order to supply a signal to a semiconductor element constituting the semiconductor integrated circuit. A signal path wiring structure (hereinafter referred to as a signal path) is a wiring structure configured by wiring and logic cells to supply signals to semiconductor elements (for example, memory elements such as flip-flops) constituting a semiconductor integrated circuit. It is. The logic cell (hereinafter also referred to as a cell) is, for example, a logic gate (AND gate or OR gate), a flip-flop, a buffer, or the like. The circuit information storage unit 10 stores circuit information of the semiconductor integrated circuit, and the semiconductor integrated circuit design device designs the arrangement and signal paths of the semiconductor elements based on the circuit information. The cell information storage unit 20 stores a variation distribution of signal delay times due to a change in setting environment of a plurality of cells arranged on a signal path. The setting environment is, for example, the temperature of the cell arrangement location in the semiconductor chip, the power supply voltage supplied to the cell, or the cell process variation at the cell arrangement location (transistor size (channel width (W) / channel length ( L) is a variety of environments at the position where the cell is arranged, etc. The variation in the cell signal delay time means a variation in the signal delay time of the cell in a certain setting environment. Variations in the signal delay time of a cell include variations in the delay time of the cell in accordance with the temperature of the cell arrangement location, variations in the delay time of the cell in accordance with the power supply voltage supplied to the cell, and variations in the transistors constituting the cell. This is a variation in delay time of the cell according to a process variation in size, etc. Usually, the setting environment changes depending on the position where the cell is arranged. When the environment changes, the variation distribution of the signal delay time of the cell changes, and the variation of the variation distribution of the signal delay time is unique to the cell and is determined depending on the setting environment. The information on the variation distribution of the signal delay time of the cell is previously determined as a variable corresponding to the setting environment and stored in the cell information storage unit (cell library) 20.

  The target timing calculation unit 30 calculates a target timing (signal delay time) to be satisfied by each path of the signal path based on the circuit information. At this time, the signal delay time calculated by the target timing calculation unit 30 is hereinafter referred to as a target delay time. The target delay time is a delay time calculated for each signal path based on a preset standard, and is a temporal range (standard) that the signal delay time of the signal path should be satisfied. The path timing calculation unit 40 calculates the timing (signal delay time) of each path of the logically synthesized signal path. At this time, the signal delay time calculated by the path timing calculation unit 40 is hereinafter referred to as a current delay time.

  The environment analysis unit 60 analyzes the setting environment of an existing cell set in a certain signal path. For example, the environment analysis unit 60 calculates the temperature of the cell arrangement location, the power supply voltage supplied to the cell, or the cell process variation at the cell arrangement location.

  The cell extraction unit 70 extracts a plurality of replacement cells (replacement cells) on the signal path from the plurality of cells stored in the cell information storage unit 20. When these plurality of replacement cells are set on the signal path, the variation distribution of delay times related to the setting environment cancels out so as to approach the sum of the average values of the cell delay times of the plurality of replacement cells. Cell. More specifically, the cell extraction unit 70 first selects some combinations of a plurality of logic cells on the signal path such that the sum of the average values of the signal delay times becomes the target delay time from the cell information storage unit 20. . Here, the average value of the signal delay time of each cell is an average value including the signal delay time of all setting environments. Next, the cell extraction unit 70 determines that the distribution distribution of the signal delay time of each cell related to a certain setting environment analyzed by the environment analysis unit 60 among the selected combination of logic cells is the signal delay time of each cell. A combination which is opposite to each other with respect to the average value is extracted.

  If the variation distribution of the signal delay time of each cell is opposite to the average value of the signal delay time of each cell, the variation distribution of the signal delay time cancels each other, and the variation of the signal delay time of the entire path is reduced. Can be made.

  The cell replacement unit 80 replaces the existing cell that has been set with the replacement cell extracted by the cell extraction unit 70. As a result, the signal delay time of the signal path varies little with respect to a certain setting environment, and the target delay time can be satisfied. The circuit information output unit 90 outputs circuit information satisfying the target delay time from the circuit information storage unit 10. For example, the circuit information output unit 90 is an interface or a monitor.

  As described above, the semiconductor circuit design apparatus according to the present embodiment can optimize the signal delay time of the signal path in consideration of the surrounding environment of the cell. Thereby, the variation in the delay time of the signal path can be reduced while keeping the signal delay time within the range of the target delay time.

  FIG. 2 is a flowchart showing a circuit design method by the semiconductor circuit design apparatus according to the present embodiment. FIG. 3 is a conceptual diagram showing the circuit design method according to the present embodiment. With reference to FIG. 2 and FIG. 3, the present embodiment will be described in more detail.

  First, the target timing calculation unit 30 calculates the target delay time that each path of the signal path should satisfy based on the circuit information (S10). The route timing calculation unit 40 calculates the current delay time of each route of the logically synthesized signal route (S20).

  The environment analysis unit 60 analyzes the setting environment of an existing cell set in the signal path (S40).

  The cell extraction unit 70 extracts a plurality of cells from the cell information storage unit 20 based on the target delay time and the setting environment analyzed by the environment analysis unit 60 (S50). For example, as shown in FIG. 3, it is assumed that a signal path P10 including two cells C10 and C20 is set between the flip-flop FF1 and the flip-flop FF2. The target delay time between the flip-flops FF1 and FF2 is, for example, 1.2 nanoseconds (ns). As described above, assuming that the target delay time is 1.2 ns, the cell extraction unit 70 selects a combination of cells in which the total sum of the average values of the signal delay times is 1.2 ns when set in the signal path P10. . For example, the cell extraction unit 70 may include (0.6 ns, 0.6 ns) cell combinations, (0.7 ns, 0.5 ns) cell combinations, (0.8 ns, 0.4 ns) cell combinations, etc. Select. The numerical value in the parenthesis indicates the average value of the signal delay time of each cell.

  Next, the cell extraction unit 70 extracts cell combinations in which variations in signal delay time relating to a certain setting environment exist on the opposite sides with respect to the average value of the signal delay times. For example, the average value of the signal delay time of the entire cell C10 is 0.6 ns. The variation distribution of the delay time of the cell C10 related to the setting environment A (for example, the power supply voltage) at the arrangement location of the cell C10 has an average value of 0.5 ns and a standard deviation of 0.1. The variation distribution of the delay time of the cell C10 related to the set environment B (for example, temperature) at the location where the cell C10 is arranged has an average value of 0.7 ns and a standard deviation of 0.1. Moreover, the average value of the signal delay time of the whole cell 20 is also 0.6 ns. The average value of the variation distribution of the delay time of the cell C20 with respect to the setting environment A at the arrangement location of the cell C20 is 0.7 ns, and the standard deviation of the variation distribution is 0.1. The average value of the variation distribution of the delay time of the cell C20 related to the setting environment B (for example, temperature) at the arrangement location of the cell C20 is 0.5 ns, and the standard deviation of the variation distribution is 0.1. For the setting environments A and B, the cells C10 and C20 vary on the opposite side with respect to the average value of the overall signal delay time of each of the cells C10 and C20. Therefore, by combining the cell C10 and the cell C20, the variation distribution of the signal delay time with respect to the setting environments A and B is canceled and minimized.

  By extracting the combination of the cells C10 and C20 having such a variation distribution of the signal delay time from the cell information storage unit 20, the signal delay time of the entire signal path P10 satisfies the target delay time, and the setting environment A It is possible to minimize the variation in the signal delay time in B and B.

  The average value of the signal delay times of the cells C10 and C20 is a case where the target delay time (1.2 ns) of the entire path is a combination of cells of (0.6 ns, 0.6 ns) as described above.

  The configurations of the cells C10 and C20 may be different. In this case, the cell extraction unit 70 selects a combination of (0.7 ns, 0.5 ns) cells and the like. For example, if the overall signal delay time of the cell C10 is 0.7 ns and the overall signal delay time of the cell C20 is 0.5 ns, the cell extraction unit 70 sets the overall signal delay time for the setting environments A and B. What is necessary is just to extract the some cell which is mutually opposite on the average value (0.7 ns about cell C10, 0.5 ns about cell C20) as the cells C10 and C20.

  The specific example shown in FIG. 3 is an example, and the present embodiment is not limited to this. For example, the target delay time may be in a range based on a standard of 1.2 ± t (ns). There may be one setting environment or three or more setting environments. Further, the number of cells may be three or more.

  Further, when there are a plurality of setting environments, the cell extraction unit 70 may extract a plurality of cells that offset the variation in signal delay time due to the setting environment having the largest variation. This is because it can be expected that the variation distribution of the signal delay time is greatly different for each cell as the variation of the setting environment is larger. In other words, it is because the probability that the signal delay time of the route will deviate from the target delay time is higher in a setting environment with larger fluctuations. By canceling the variation in the signal delay time due to such a setting environment, the signal delay time of the path easily satisfies the target delay time.

  Next, the cell replacement unit 80 replaces the existing cell originally set by the cell extracted by the cell extraction unit 70 (S60). The replacement work in steps S20 to S60 is executed for all signal paths. When the replacement operation is completed for all signal paths, the circuit information output unit 90 outputs or displays the circuit information after the cell replacement (S70).

  According to the present embodiment, by combining the cells C10 and C20, it is possible to cancel the variation in signal delay time of each cell in the setting environment, and to realize variation minimization of signal delay time in consideration of the surrounding environment of the cell. it can. Thereby, the semiconductor integrated circuit design device according to the present embodiment can suppress the yield reduction due to the signal delay time of the entire signal path.

(Second Embodiment)
FIG. 4 is a conceptual diagram showing a circuit design method by the semiconductor circuit design apparatus according to the second embodiment of the present invention. In the second embodiment, the cell extraction unit 70 extracts a cell having a variation distribution of the signal delay time smaller than that of an existing cell in a setting environment having a large variation.

  For example, when the variation of the setting environment A (for example, process variation) is the largest at the installation position of the cell C10, the cell extraction unit 70 extracts the cell C10 having a small variation in signal delay time in the setting environment A. When the setting environment B (for example, the power supply voltage) varies greatly at the installation position of the cell C20, the cell extraction unit 70 extracts the cell C20 having a small variation in signal delay time in the setting environment B. As described above, the second embodiment can reduce the variation in the signal delay time of the entire signal path by extracting the cell having the small variation in the signal delay time in the setting environment having a large variation.

1 is a block diagram showing an example of the configuration of a semiconductor integrated circuit design device according to a first embodiment of the present invention. The flowchart which shows the circuit design method by the semiconductor circuit design apparatus by this embodiment. The conceptual diagram which shows the circuit design method by this embodiment. The conceptual diagram which shows the circuit design method by the semiconductor circuit design apparatus according to 2nd Embodiment which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Circuit information storage part 20 ... Cell information storage part 30 ... Target timing calculation part 40 ... Path | route timing calculation part 60 ... Environment analysis part 70 ... Cell extraction part 80 ... Cell replacement part 90 ... Circuit information output part

Claims (4)

A semiconductor circuit design apparatus for designing a signal path between elements constituting a semiconductor integrated circuit,
A circuit information storage unit for storing circuit information of the semiconductor integrated circuit;
A cell information storage unit for storing variation of a cell delay time indicating a delay time of the logic cell due to a change in a setting environment of the logic cell arranged on the signal path;
A timing calculation unit for calculating a path delay time indicating a delay time of the signal path logically synthesized based on the circuit information;
An analysis unit for analyzing a change in a setting environment of a setting location of a plurality of existing logic cells set on the signal path;
Among the plurality of logic cells stored in the cell information storage unit, when set on the signal path, a variation distribution of delay time related to the setting environment is calculated for the plurality of logic cells set on the signal path. An extraction unit that extracts a plurality of replacement logic cells that cancel each other so as to approach the sum of the average values of the cell delay times;
A semiconductor circuit design apparatus comprising: a replacement unit that replaces the plurality of existing logic cells with the plurality of replacement logic cells.   2. The semiconductor circuit design according to claim 1, wherein a variation distribution of delay times in the setting environment of the plurality of replacement logic cells is opposite to each other with respect to an average value of the cell delay times of the replacement logic cells. apparatus. A semiconductor circuit design apparatus for designing a signal path between elements constituting a semiconductor integrated circuit,
A circuit information storage unit for storing circuit information of the semiconductor integrated circuit;
A cell information storage unit for storing variation of a cell delay time indicating a delay time of the logic cell due to a change in a setting environment of the logic cell arranged on the signal path;
A timing calculation unit for calculating a path delay time indicating a delay time of the signal path logically synthesized based on the circuit information;
An analysis unit for analyzing a change in a setting environment of a setting location of a plurality of existing logic cells set on the signal path;
An extraction unit for extracting a replacement logic cell having a variation distribution of delay time related to the setting environment smaller than that of the existing logic cell;
A semiconductor circuit design apparatus comprising: a replacement unit that replaces the existing logic cell with the replacement logic cell.   4. The semiconductor circuit design according to claim 3, wherein the extraction unit extracts a replacement cell having a delay time variation distribution smaller than that of the existing cell with respect to a setting environment having the largest variation among the plurality of setting environments. apparatus.

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