JP2000082092A - Design method for integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily design a wave pipeline circuit which can reduce its power consumption by performing a wave pipelining process including the partial deletion of component elements of a non-wave pipelining circuit that is generated in a simulation process and an adjustment process following by the partial deletion of component elements against the pupelining circuit. SOLUTION: A wave pipelining process including the partial deletion of component element and an adjustment process following to this partial direction of component elements is performed to a non-wave pipelining circuit which is generated in the synthesizing, layout and distribution and real distribution capacitance simulation processes. In a wave pipelining process, to perform deletion of a thip-tlop for example, an adjustment process is carried out to inset a delay circuit 306 according to the comparison result obtained between a stage delay time and the threshold. Under such conditions, the less significant bits are outputted from a signal line 313 to the circuit 306 and then inputted to a following pipeline stage 304 via a signal line 314 with a delay time equal to that of the most significant bit in an adjustment process.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an integrated circuit design method, and more particularly to an integrated circuit design method for performing synthesis processing, placement and wiring processing, and real wiring capacity simulation processing using a register transfer level description in a hardware description language. More particularly, the present invention relates to an integrated circuit design method capable of designing a wave pipeline circuit in accordance with an ASIC design method using a hardware description language.

[0002]

2. Description of the Related Art In recent years, the trend of high speed, large capacity, and miniaturization of integrated circuits has become remarkable, and it is difficult for humans to design at the gate level to improve efficiency, or It is often difficult. Therefore, when designing an integrated circuit, VHDL, Ver.
hardware description language such as ilog-HDL (HD
L: Hardware Description Language), and a design method of generating a gate circuit using a logic synthesis tool or a placement / wiring tool based on the description is often used. Circuit design using such HDL is as follows.
In particular, ASICs (Application Specif
This is an important technology in ic integrated circuits.

HDL such as VHDL or Verilog-HDL is a high-level language similar to a programming language, and can describe various stages from a high abstraction level to a level close to a gate level. is there. Typical levels are an architecture level that describes the algorithm of the entire system, an operation (behavior) level that models the operation specifications of the modules that make up the architecture, and the location and clock of the registers. And a register transfer level (hereinafter referred to as RTL), which is a level at which a logic circuit can be generated. At present, a tool that can generate a gate circuit as described above can synthesize from an RTL description, and it is necessary to perform an RTL description in HDL at a stage prior to a synthesis process and a placement and routing process. It will be. Therefore, in a general ASIC design method, RTL description is performed in a hardware description language, synthesis processing and placement and routing processing are performed based on the RTL description, and delay time is adjusted by simulation or the like.

[0004] On the other hand, in order to increase the speed of a microprocessor, a pipeline technique for executing a plurality of processes simultaneously in parallel has been generalized. For example, in the case of a CPU, processes such as instruction fetch, instruction decode, and instruction execution are each set as a stage (stage), and each stage is processed in parallel. By setting the following instruction as a processing target, it is possible to increase the speed. In a circuit that performs such processing, much of the power is consumed by a clock line used for the processing and a flip-flop used as a register. Therefore, the method of wave pipelining that eliminates the flip-flops that can be deleted from the designed pipeline circuit and suppresses the clock supply to the flip-flops is effective for reducing power consumption.

As for the use of the wave pipeline circuit according to the prior art, there is a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. Hei 8-263985. It is planned.

[0006]

However, in general, it is more difficult to implement a wave pipeline in a logic circuit than in the above-described SRAM. This means that the delay time in data bit units is uniform in a memory circuit such as an SRAM as described above, but is not always uniform in a logic circuit. In this case, the difference between the delay times is large. In particular,
A configuration that lacks a register (flip-flop), such as a wave pipelined circuit, is originally not suitable for an RTL description that defines data transfer between registers. Performing the line conversion process involves inherent difficulties.

FIGS. 24 to 28 are diagrams for explaining a problem that arises when an attempt is made to make a wave pipeline in a circuit design using an RTL description. FIG.
4 is a conceptual diagram of an RTL description showing a pipeline circuit that does not perform wave pipeline processing, and FIG. 25 is a wave pipeline circuit in which a specific flip-flop group is deleted from the circuit shown in FIG.

The RTL description of FIG. 24 includes an input flip-flop group 2401, pipeline stages 2402 and 2404, an intermediate flip-flop group 2403, and an output flip-flop group 2405. These flip-flop groups and the pipeline stages are connected by signal lines 2411 to 2414, respectively, and a clock 2421 is supplied to the flip-flop groups 2401, 2403, and 2405. Each flip-flop group has flip-flops equal to or more than the number of bits of data to be processed.

FIG. 26 is a diagram for explaining the difference between the data to be processed by the pipeline circuit and the delay time for each bit constituting the data. FIG.
This indicates that addition processing is performed on data S and data T each having n bits. in this case,
Usually, the least significant bit s constituting each data
The process for n and tn is performed first, and then the process including the carry process is performed for the upper bits sequentially from the lower bits. N shown in FIG.
The bit data is data output as a result of the addition processing in FIG. As shown in the figure, the delay time till the output of each bit is the delay time tD of the least significant bit D.
Is the smallest, and the higher-order bit has a longer delay time, and the most significant bit A has the largest delay time tA.

FIG. 27 is a timing chart showing the operation of the pipeline circuit shown in FIG. In the figure, (a) is the clock indicated by reference numeral 2421 in FIG. 24, and the processing is executed in accordance with the rise of this clock signal. (b) shows the output from the input flip-flop group 2401 in FIG. 24, (e) shows the output from the intermediate flip-flop group 2403 in FIG. 24, and (h) shows the output from the output flip-flop group 2405 in FIG. I have.

[0011] Pipeline stages 2402 and 2
In 404, processing is performed on the data, respectively, but as described with reference to FIG. 26, the delay time for each bit constituting the data to be processed is different. (C) and (d) of FIG. 27 show the outputs from the paths that have the maximum and minimum delay times in the pipeline stage 2402. (F) and (g) of FIG.
4 shows the output from the path that has the maximum and minimum delay times.

Hereinafter, processing in the pipeline circuit shown in FIG. 24 will be described with reference to the timing chart of FIG. In response to the rising edge of the clock 2421 shown in FIG.
The data to be processed is fetched and output as attention data D1 shown in FIG. Data D1 is
Via the signal line 2411, the pipeline stage 24
02 is input. In the processing in the pipeline stage 2402, the delay time for each bit differs as described above. Therefore, in the data output from the pipeline stage 2402, FIG.
As shown in (c) and (d), the maximum delay is dl11,
The minimum delay is dl12.

The pipeline stage 240 shown in FIG.
The data processed in 2 is output to the intermediate flip-flop group 2403 via the signal line 2412, and the intermediate flip-flop group 2403 inputs the data in response to the rising edge of the supplied clock 2421. The data input to the intermediate flip-flop group 2403 is
This is output to the pipeline stage 2404 via the signal line 2413 in FIG. 24 as the attention data D3 shown in FIG. Data input to the pipeline stage 2404 is processed and output. In this case as well, the delay time differs for each bit as in the case of the pipeline stage 2402.
As shown in (f) and (g), the data output from the pipeline stage 2404 has a maximum delay of dl3.
1. The minimum delay is dl32.

As shown in FIG. 24, data processed in the pipeline stage 2404 is
4 and output to the output flip-flop group 2405. The output flip-flop group 2405 inputs data in response to the rising of the supplied clock 2421 and outputs the data as the attention data D5 shown in FIG. I do.
The output data D5 is the output of the pipeline circuit shown in FIG.

As described above, in the pipeline circuit in which the RTL is described as shown in FIG. 24, the output from the included pipeline stage is appropriately processed even if there is a variation in the delay time. Therefore, based on such an RTL description, it is possible to perform synthesis processing and placement / wiring processing using a tool or the like.

FIG. 25 is an RTL showing a wave pipeline circuit in which the intermediate flip-flop group 2403 has been deleted from the pipeline circuit (non-wave pipelined circuit) of FIG.
It is a conceptual diagram of description. By such a wave pipeline, in the circuit of FIG. 25, the size can be reduced by eliminating the flip-flop group 2403 of FIG. On the other hand, power for supplying the clock 2421 can be saved. As shown, this wave pipeline circuit is based on the circuit shown in FIG. 24, in which pipeline stages 2502 and 2504 are directly connected via a signal line 2512 and has no flip-flop group between both stages. It has become.

FIG. 28 is a timing chart showing the operation of the wave pipeline circuit shown in FIG. In the figure, (a) is the clock indicated by 2521 in FIG. (b) is an input flip-flop group 2501 in FIG.
(G) is the output flip-flop group 2505 in FIG.
Shows the output from. (B) of the figure shows the data output from the pipeline stage 2502, and (f) shows the data output from the pipeline stage 2504 as (d) and (e).
Indicates the output from the path that provides the maximum and minimum delay time in the pipeline stage 2504.

The processing in the wave pipeline circuit shown in FIG. 25 will be described below with reference to the timing chart of FIG. In response to the rising edge of the clock 2521 shown in FIG. 28A, data to be processed is fetched into the input flip-flop group 2501 in FIG. 25 and output as the attention data D1 shown in FIG. . Data D1 is input to pipeline stage 2502 via signal line 2511. Pipeline stage 2
In the process at 502, the delay time for each bit is different as described above, so that the data output from the pipeline stage 2502 is the same as FIG.
As shown in FIG. 8 (c), the maximum delay is dl11 and the minimum delay is dl12.

Therefore, the valid data D2 is the clock 2
Output is started at a time delayed by dl11 which is the maximum delay after the rise of 521, and is output until a time delayed by dl12 which is the minimum delay after the next rise of the clock 2521. Then, a period after outputting the valid data D2 is a data invalid period tn_v.

In FIG. 25, pipeline stage 2
The valid data D2 output from the signal line 502
Is input to the pipeline stage 2504 via
Processing in the pipeline stage 2504 is performed. As shown in FIGS. 28 (d) and (e), the maximum delay is d
l21 and the minimum delay are dl22. Therefore, FIG.
The valid data D4 output from the pipeline stage 2504 shown in (1) is started to be output at a time when dl21 (maximum delay) has elapsed from the start of the valid data D2 output from the pipeline stage 2502, and the valid data D2
From the end to the time delayed by dl12 (minimum delay). However, as shown, since the clock 2521 does not rise during the output period of the valid data D4, the output flip-flop group 2505 that has output the valid data D4 cannot capture this data. Therefore, correctly processed data is not output from the wave pipeline circuit.

As described above, in a circuit in which it is difficult to adjust the delay time difference, it is difficult to simply designate the elimination of the flip-flop in the RTL description to achieve the wave pipeline. In designing a circuit, it is difficult to improve the efficiency of circuit design processing by performing RTL description and manually performing a gate-level design without using a synthesis / placement / wiring tool or the like. The point was a problem.

In order to avoid such difficulties in making a wave pipeline, it is possible to apply the technique disclosed in Japanese Patent Application Laid-Open No. 6-250817. The pipelined circuit disclosed in this publication is intended to reduce the circuit scale by using a clock synchronous switch instead of a flip-flop without performing wave pipelining for removing the flip-flop. When designing such a circuit, the adjustment of the delay time difference is easy, and the circuit scale can be reduced.
Compared to the case of wave pipelining, clock distribution cannot be reduced.
The effect of reducing power consumption is not very large. Also, as shown in FIG. 1 of JP-A-6-250817, when the switch is a MOS switch, its output is in a floating state when the switch is turned off, which may cause noise generation. It becomes a problem.

The present invention has been made in view of such a problem, and realizes a design of a wave pipeline circuit in the design of an integrated circuit according to a general ASIC design flow including an RTL description, thereby saving power. An object of the present invention is to provide an integrated circuit design method capable of easily designing a wave pipeline circuit that can be designed.

[0024]

In order to achieve the above object, an integrated circuit design method according to the first aspect of the present invention uses a register transfer level description in a hardware description language to perform synthesis processing, placement and wiring processing. And an integrated circuit design method for designing a pipeline circuit including a plurality of processing stages by performing a real wiring capacity simulation process. Wave pipeline processing including deletion of some of the components and adjustment processing accompanying the deletion is performed on the pipelined circuit. Thereby, for a non-wave pipelined circuit designed according to a general ASIC design method with an RTL description,
Wave pipelining is performed with adjustment processing that can avoid inconvenience caused by a large difference in delay time that can occur in a logic circuit.

According to a second aspect of the present invention, in the method of the first aspect, the specified data temporary holding means is deleted in the wave pipeline processing. In this way, the design is made to omit the temporary holding means with large power consumption and to suppress the clock supply.

According to a third aspect of the present invention, there is provided an integrated circuit designing method, wherein the wave pipeline processing is performed from the non-wave pipeline circuit.
When the specified temporary holding means extraction processing for extracting the specified data temporary holding means and the extracted data temporary holding means are deleted and the processing stages before and after that are directly connected,
A stage delay time acquisition process for acquiring a delay time for the processing of specific data in the preceding and following processing stages, and a comparison process using the delay time acquired in the stage delay time acquisition process are performed, and according to the result of the comparison process. And a delay time adjustment process for adjusting the delay time accompanying the deletion of the designated data temporary holding means. Thus, the adjustment process is performed according to the delay time before and after the data temporary holding unit to be deleted.

According to a fourth aspect of the present invention, there is provided an integrated circuit designing method according to the third aspect, wherein the delay time adjusting processing is performed on specific data in a processing stage located before the designated data temporary holding means. If all the holding times are smaller than a predetermined value, the holding time is extended by inserting a delay means. Thereby, the adjustment is performed so that the valid data output period is not too short due to the delay time being too short.

According to a fifth aspect of the present invention, there is provided an integrated circuit designing method according to the third aspect, wherein the delay time adjusting processing is performed on specific data in a processing stage located before the designated data temporary holding means. If all the holding times are smaller than a predetermined value, the holding time is extended by inserting a temporary holding means for adjustment. Thereby, adjustment is performed so that the data output from the preceding processing stage is processed in accordance with the subsequent clock.

According to a sixth aspect of the present invention, in the integrated circuit designing method according to the third aspect, the delay time adjustment processing is performed on specific data in a processing stage located before the designated data temporary holding means. If all the holding times are smaller than a predetermined value, the designated data temporary holding means is not deleted and used as the adjustment temporary holding means. Thus, the above-described adjustment is performed using the data temporary holding unit that is not deleted.

According to a seventh aspect of the present invention, in the integrated circuit design method according to the fifth or sixth aspect, the delay time adjustment processing is performed by adjusting a phase of a clock supplied to the adjustment temporary holding means. It further includes an adjustment process. Thereby, adjustment is performed so that the data output from the preceding processing stage is processed in accordance with the appropriately delayed clock.

According to an eighth aspect of the present invention, there is provided an integrated circuit design method according to the first aspect, wherein a part of the component to be deleted is determined by an evaluation process. Is to delete the data temporary holding means in accordance with the above determination. Thereby, a deletion target is appropriately selected.

According to a ninth aspect of the present invention, in the method for designing an integrated circuit according to the eighth aspect, the evaluation processing is performed for each of the data temporary holding units included in the non-wave pipelined circuit. The method includes a time characteristic extraction process for acquiring a time characteristic value indicating the characteristic of the means, and a classification process for classifying each data temporary holding unit based on the acquired time characteristic value. In the above, the data temporary holding means is deleted according to the above classification. Thereby, a deletion target is appropriately selected according to the time characteristic.

According to a tenth aspect of the present invention, in the method for designing an integrated circuit according to the ninth aspect, the evaluation processing includes, for each data temporary holding unit, the data temporary holding unit based on a result of the classification process. Whether or not to be subject to deletion and the necessity / unnecessity of the adjustment process accompanying the deletion, and further including a level determination process of giving level information indicating the type, in the wave pipelining process, according to the level information The temporary data holding means is deleted and the adjustment process is performed. With this, the target to be deleted is appropriately selected according to the time characteristic and the level information is given,
Execute the process corresponding to the level information.

An integrated circuit design method according to claim 11 is the method according to claim 1, in which the data temporary holding means is deleted in the wave pipelining process, and is an object of the deletion. For the data temporary holding means, the wiring length on the input side and the output side is extracted, and when the extracted wiring length exceeds a predetermined value, the data temporary holding means is replaced with a buffer circuit. This avoids the adverse effect of deleting the temporary data holding means by replacing it with a buffer circuit.

According to a twelfth aspect of the present invention, there is provided an integrated circuit designing method according to the eleventh aspect, wherein the data temporary holding means to be deleted outputs normal and inverted output signals. The above replacement is performed by a buffer circuit including an inverter circuit. This allows
An adverse effect due to the deletion of the temporary data holding means is avoided by replacing the buffer circuit with an inverter circuit.

According to a thirteenth aspect of the present invention, in the integrated circuit design method according to the first aspect, in the wave pipelining process, the temporary data holding means is deleted, and the data is to be deleted. For the temporary data holding unit, a library conversion process for replacing the temporary data holding unit with a temporary data holding unit having a library value different from the library value of the temporary data holding unit, and an optimization process corresponding to the library conversion process are performed. Things. As a result, the adverse effects of deleting the temporary data storage
Avoid by the optimization processing corresponding to the library conversion processing.

According to a fourteenth aspect of the present invention, there is provided an integrated circuit design method according to the thirteenth aspect, further comprising: arrangement position information indicating an arrangement of each component in the pipeline circuit;
This is for extracting actual wiring capacity information indicating the wiring capacity in the pipeline circuit, and performs the above-mentioned optimization processing based on the extracted arrangement position information and the actual wiring capacity information. As a result, the deleterious effect of deleting the temporary data holding means can be handled in the library conversion process.
It is avoided by an optimization process based on the placement maintaining information and the actual wiring capacity information.

According to a fifteenth aspect of the present invention, there is provided an integrated circuit designing method according to the thirteenth aspect, wherein an optimization variation indicating a change of the circuit due to the optimization processing is obtained. Based on the fluctuation amount, it is determined whether or not the above-described optimization processing can be executed and whether or not the above-mentioned data temporary holding unit can be deleted. Thus, the influence of the optimization processing is checked, and whether or not the processing can be executed is appropriately determined.

In the integrated circuit designing method according to a sixteenth aspect, in the method according to the thirteenth aspect, the library conversion process includes replacing the temporary data holding means with the temporary data holding means. A delay circuit is inserted in the vicinity. Thereby, the difference in delay time is appropriately adjusted.

[0040]

Embodiment 1 of the present invention. The integrated circuit design method according to the first embodiment of the present invention performs a wave pipeline process for deleting a specific flip-flop in the integrated circuit design method according to the ASIC design flow. FIG. 1 is a flowchart illustrating a processing procedure according to the first embodiment. Hereinafter, the processing procedure of the integrated circuit design according to the first embodiment will be described with reference to the flow of FIG. In step 101, an RTL description and a design constraint file are read. In the synthesis processing step of the next step 102, by synthesizing these,
Generate a synthesis result netlist. Then, Step 1
In the placement and routing processing step 03, the placement and routing of the logic cells is performed based on the synthesis result netlist generated in step 102, and a placement and routing layout is generated. The placement and routing processing in step 103 can be performed using a layout CAD or the like. Step 104
In the actual wiring capacitance simulation step, a delay simulation is performed based on the synthesis result netlist and the placement and routing results, and the circuit and layout are corrected to adjust the delay time, and the corrected netlist and the corrected Generate a layout. The modified netlist and the modified layout represent a non-wave pipelined circuit.

In step 105, a wave pipeline specification file for specifying a flip-flop to be deleted is read. Then, in the wave pipelining step of step 106, the flip-flop specified by the pipeline specification file is deleted based on the corrected netlist and the corrected layout, and the input / output of the flip-flop is short-circuited. A necessary correction process is performed, and a wave pipelining process of deleting a clock wiring for the flip-flop is performed. Thereafter, in the output step 107, the final net list and the final layout are output. The final netlist and the final layout represent a wave pipeline circuit.

FIG. 2 is a flowchart showing a detailed processing procedure in the wave pipelining step shown in the flow of FIG. Hereinafter, the processing procedure of the wave pipelining according to the first embodiment will be described with reference to the flow of FIG. In the designated flip-flop extraction step of step 201, the flip-flop designated in the wave pipelined designation file is extracted for the circuit indicated by the modified netlist and the modified layout, that is, for the non-wave pipelined circuit. .
Next, in the stage delay time extraction step of step 202, the delay times of the operation stage (pipeline stage), which is the processing stage located before the flip-flop extracted in step 201, and the operation stage located after, are extracted. Is done.

In step 203, a threshold value to be described later is input. In the stage delay time adjusting step in step 204, the delay time extracted in step 202 is compared with the threshold value input in step 203. Is Then, as a result of the comparison, step 2
When it is determined that the delay time in the calculation stage extracted in 02 is larger than the threshold value, an adjustment process described later is executed.

In the designated flip-flop deletion step of Step 205, the deletion of the flip-flop extracted in Step 201 and the deletion of the clock wiring for the flip-flop are executed. Then, the operation stages located before and after the deleted flip-flop are combined to generate a final layout. In a subsequent netlist modification step 206, the netlist is modified to generate a final netlist.

FIG. 4 is a diagram for explaining the threshold value read in step 203 of the flow of FIG. This figure is a diagram for explaining a difference in delay time between bits constituting data to be processed, similarly to FIG. 26B described above. As shown in FIG. 26 (b), the delay time tD of the least significant bit D is the minimum, the higher bit has a longer delay time, and the delay time tA of the most significant bit A is the largest. Becomes In the figure, t
MC indicates one machine cycle, and in the first embodiment, the difference between one machine cycle and the delay time is used as a threshold. Therefore, in step 204 of the flow of FIG. 2, when it is determined that the stage delay time acquired in step 202 is larger than the threshold value, an adjustment process is performed. The specified flip-flop is deleted without performing the adjustment processing.

FIGS. 3, 6, and 7 are diagrams for explaining the adjustment processing performed in step 204 of the flow of FIG. FIGS. 5 and 8 are timing charts for explaining the operation of the circuit obtained when the adjustment processing shown in FIGS. 3 and 6 is performed.

In the wave pipeline processing according to the first embodiment, an intermediate flip-flop group (2403 in FIG. 24) functioning as data temporary holding means is deleted from the circuit (non-wave pipelined circuit) shown in FIG. Is what you do. As described above, as shown in FIG. 25, simple deletion may cause inconvenience. Therefore, in the first embodiment, adjustment processing for inserting a delay circuit as shown in FIG. 3 is performed. It is. Depending on the degree of the delay time, an adjustment process for inserting a flip-flop for clock adjustment as shown in FIG. 7 or for inserting a flip-flop for clock adjustment and a delay circuit as shown in FIG. It is also possible.

In the adjustment process of inserting a delay circuit as shown in FIG. 3, the difference in delay time between the data having a large delay time and the data having a large delay time is corrected by passing data having a small delay time through the delay circuit. This is to avoid a problem due to the short data holding time shown. That is, in the case of the n-bit data shown in FIG. 4, the delay time of the lower-order n-1 bits of data is shorter than that of the data A of the most significant bit. Therefore, when the delay time of the effective data is reduced by adjusting the delay time of the data A of the most significant bit by delaying the delay time tA of the data A of the most significant bit by passing the delay data through the delay circuit, It is possible to have a length sufficient to match the rising edge of the clock, and to avoid a problem that occurs because the valid data output period is too short as shown in the timing chart of FIG. .

Designed with such adjustment processing,
Regarding the operation of the wave pipeline circuit shown in FIG.
The description will be given according to the timing chart of FIG. In the figure, (a) is the clock indicated by 321 in FIG. 3, and the processing is executed in accordance with the rise of the clock signal. (b) is the input flip-flop group 3 of FIG.
(H) from the output flip-flop group 30 of FIG.
5 shows the output. 9C shows data output from the pipeline stage 302, FIG. 9G shows data output from the pipeline stage 304, FIG. 9D shows input to the pipeline stage 304, and FIGS. f) shows the output from the path that has the maximum and minimum delay time in the pipeline stage 304.

In response to the rising edge of the clock 321 shown in FIG. 5A, the input flip-flop group 301 shown in FIG. 3 fetches data to be processed, and the fetched data is the target data shown in FIG. The signal is output as D1 and is input to the pipeline stage 302 via the signal line 311. In the processing in the pipeline stage 302, since the delay time for each bit is different, the maximum delay of the data D2 output from the pipeline stage 302 is dl11 as shown in FIG. , The minimum delay is dl12.

For example, in the n-bit data shown in FIG. 4, a difference t4 between one machine cycle (tMC) and the delay time (tA) of the most significant bit is set as a threshold value (step 203 in FIG. 2). The most significant bit A is output to the subsequent pipeline stage 304 without delay via the signal line 312, and the lower bits are output to the delay circuit 306 from the signal line 313 without delay. Signal line 3 with the same delay time as
The adjustment processing can be performed so that the input is input to the subsequent pipeline stage 304 via the processing unit 14.

As shown in (d) of the timing chart of FIG. 5, for the input data D40 to the pipeline stage 304, the end time is determined by the delay dl21 by the delay circuit 312 with respect to the minimum delay dl12.
Is added. After this, pipeline stage 3
From 04, data is output to the output flip-flop group 305 via the signal line 315.

The output from the pipeline stage 304 has a maximum delay of dl as shown in FIGS. 5 (e) and 5 (f).
41, the minimum delay is dl42. The period during which the valid data D43 is output from the pipeline stage 304 is determined as shown in FIG. 5 (g). Therefore, the output flip-flop group 305 can capture this data in response to the rising edge of the clock 321 shown in FIG. Then, as shown in FIG. 5 (h), the output flip-flop group 305 outputs appropriate valid data D5.

When the n-bit data shown in FIG. 4 is to be processed, the intermediate flip-flop group included in the non-wave pipelined circuit shown in FIG. 24 includes at least n flip-flops and a clock. Need to be supplied. Since the delay circuit included in the wave pipeline circuit of FIG. 3 only has to delay only the bits that need to be adjusted out of n bits, the circuit scale is reduced by wave pipelining, and the required power amount is reduced. Can be reduced.

In the integrated circuit design method according to the first embodiment, it is possible to exclusively perform the adjustment processing using only the delay circuit shown in FIG. However, in the adjustment processing shown in FIG. 3, the data shown in FIG.
When the difference between the delay time (tB) of the middle-order bit B and the delay time (tA) of the most significant bit A is relatively small, the delay circuit 306 may be small. On the other hand, when the difference between the delay time (tC, tD) and the delay time (tA) of the most significant bit A becomes relatively large, such as the middle-order bit C and the least significant bit D, The delay circuit 306 needs to have a larger circuit scale. In such a case, FIGS. 6 and 7
As shown in the figure, by adjusting the phase of the clock for data processing by inserting a flip-flop,
The overall circuit size can be reduced as compared with the case where a relatively large delay circuit is used.

In the adjustment processing shown in FIGS. 6 and 7, data to be delayed by delay circuit 306 in the adjustment processing of FIG.
6 and output to a subsequent stage according to a clock signal. That is, the inserted flip-flop 606 or 706 functions as a temporary holding unit for adjustment. Like the least significant bit of FIG.
If the difference between the delay times is large, the clock signal can be output at the next rising edge.
Can be performed, but if there is a medium delay time difference as in the middle bit C in FIG. 4, it cannot respond to the next rising of the clock signal. . Therefore, in such a case, as shown in FIG. 6, the clock 621 is delayed by the clock delay circuit 607 and then input to the flip-flop 606 to use the rising edge of the preceding stage.

FIG. 8 is a timing chart showing the operation of the wave pipeline circuit designed by performing the adjustment processing as shown in FIG. In the same figure, (a) is 6 in FIG.
21. (b) shows the output from the input flip-flop group 601 in FIG. 6, and (j) shows the output from the output flip-flop group 605 in FIG. (C) of FIG.
Represents the data output from the pipeline stage 602, (i) represents the data output from the pipeline stage 604, and (e) represents the data output from the pipeline stage 604.
Indicates the input to the pipeline stage 604, and (g) and (h) indicate the output from the path that provides the maximum and minimum delay time in the pipeline stage 604. (D) shows a clock signal delayed by the clock delay circuit 607 in FIG. Hereinafter, the operation of the wave pipeline circuit will be described with reference to FIG.

At the rising edge of the clock 621 shown in FIG. 8A, the target data D1 shown in FIG. 8B is output from the input flip-flop group 601 in FIG. And input to the pipeline stage 602. In the processing in the pipeline stage 602, since the delay time for each bit is different, the maximum delay of the data D2 output from the pipeline stage 602 is dl11 as shown in FIG. , The minimum delay is dl12. This data is output to the flip-flop 606 via the signal line 613 in FIG. As shown, clock 62
The period from the rise of 1 to the end of the valid data D2 after the lapse of the minimum delay dl12 is the minimum delay path data valid period (tmde).

On the other hand, the clock 622 delayed by the clock delay circuit 607 is input to the flip-flop 606 in FIG. The delayed clock 622 of FIG.
(d), and the flip-flop 606 can take in data during the period tmde in accordance with the rise. Therefore, the output of the flip-flop 606 and the input to the subsequent pipeline stage 604 shown in FIGS. 9 (e) and 9 (f) are obtained when the adjustment processing of only the delay circuit described with reference to FIG. Similarly to (3) (D40 in FIG. 5D), the data is input over a sufficient length (D40 in FIG. 8D).

Therefore, the maximum delay dl4 shown in FIG.
1 and the pipeline stage 60 shown in FIG. 6I determined by the minimum delay dl42 shown in FIG.
5, the output D43 can be processed at the rising edge of the clock 621, as in the case shown in FIG. Is output.

In the wave pipeline circuit shown in FIG. 7, the clock 721 is supplied to the flip-flop 706 without passing through a delay circuit. The same operation as that of the circuit of FIG. 6 is performed except that the data is processed.

In the wave pipelining process performed by the integrated circuit design method according to the first embodiment, the adjustment processes shown in FIGS. 3, 6, and 7 can be mixed. For example, in the circuit for processing the data to be processed shown in FIG. The adjustment process using only the delay circuit shown in FIG. 3 is performed, and the adjustment process using the flip-flop and the clock delay circuit shown in FIG. The bits can be adjusted using the flip-flops shown in FIG. 7, and the respective bits are appropriately adjusted. Further, in the adjustment processing shown in FIGS. 6 and 7, a flip-flop as a temporary holding unit for adjustment is additionally inserted. However, the flip-flop as the temporary data holding unit is not deleted. It is also possible to perform an adjustment process in which is used as a temporary holding means for adjustment. For example, when the n-bit data shown in FIG. 4 is to be processed, a flip-flop that processes upper bits is intended to delete the intermediate flip-flop group having at least n flip-flops shown in FIG. And a delay circuit may be inserted if necessary, and the flip-flops for processing the middle and lower bits may be used as the flip-flops shown in FIGS. 6 and 7 without being deleted. It is possible.

As described above, according to the integrated circuit design method of the first embodiment, in the wave pipelining for eliminating the flip-flop, the delay circuit is set in accordance with the result of comparison between the stage delay time and the threshold value. By performing the adjustment process of inserting (FIG. 3), the adjustment process of inserting a flip-flop (FIG. 7), or the adjustment process of inserting a clock delay circuit and a flip-flop (FIG. 6), a normal ASIC is realized. According to the design method, it is possible to easily design a wave pipeline circuit having a large power saving effect.

Embodiment 2 The integrated circuit design method according to the second embodiment of the present invention performs a wave pipeline process of deleting a specific flip-flop as in the first embodiment. However, in the first embodiment, the specified flip-flop is deleted. On the other hand, in the second embodiment, a flip-flop to be deleted is selected.

FIG. 9 is a flowchart showing a processing procedure according to the second embodiment. Hereinafter, the processing procedure of the integrated circuit design according to the second embodiment will be described with reference to the flow of FIG. In step 901, the RTL description and the design constraint file are read. In the synthesis processing step of the next step 902, a synthesis result net list is generated by synthesizing these. Next, in the placement and routing processing step of Step 903, Step 902
Based on the synthesis result netlist generated in step (1), the logic cells are placed and wired to generate a layout and wiring layout. In the actual wiring capacity simulation step of step 904, a delay simulation is performed based on the synthesis result netlist and the placement and routing results, and the circuit and layout are corrected to adjust the delay time, and the corrected netlist and Generate the modified layout. The modified netlist and the modified layout represent a non-wave pipelined circuit.

The above steps 901 to 904
The steps up to this are performed in the same manner as steps 101 to 104 (FIG. 1) of the first embodiment. In the first embodiment, the designated file is read prior to the wave pipeline processing, whereby the flip-flop to be subjected to the wave pipeline processing is specified.
In the second embodiment, the flip-flop to be subjected to the wave pipeline is determined by performing the evaluation processing in steps 905 to 908.

In the evaluation processing according to the second embodiment, first, in a classification method / processing level reading step of step 905, a classification method and a processing level are designated.
In the second embodiment, in step 907 described later,
For each flip-flop, a classification process is performed to determine that the flip-flop belongs to any one of the predetermined groups. In this step 905, for the processing,
How to perform the classification and how to level the flip-flops according to the classification are specified.

In the time characteristic extraction processing step of step 906, a time characteristic for classifying each flip-flop into any group is obtained. Embodiment 2
In, the maximum delay time, the minimum delay time, the delay time difference value, and the processing stage cycle time are extracted for each flip-flop.

The classification processing step of step 907 and the leveling processing step of step 908 are performed according to the classification method and processing level acquired in step 905. In the classification processing step of step 907, each flip-flop is classified so as to belong to one of the groups using the temporal characteristics of each flip-flop extracted in step 906. Then, in the leveling processing step of step 908, the level is determined for each flip-flop according to the classification result in step 907. The level indicates whether or not the processing is to be performed in the wave pipeline processing, whether or not to perform the adjustment processing when the processing is to be performed, and what kind of adjustment processing is to be performed. This step 9
In the process 08, level information indicating the level is given to each flip-flop.

Therefore, in the second embodiment, step 9
In the leveling process 08, the wave pipelining process in step 909 is executed on the flip-flops belonging to the group to be subjected to the wave pipeline process. FIG. 10 shows a detailed processing procedure in the wave pipeline processing step of step 909. Hereinafter, the wave pipeline processing will be described with reference to the flow of FIG.

In the target flip-flop extraction step of step 1001, the circuit indicated by the corrected netlist and the corrected layout, that is, the non-wave pipelined circuit, is provided in the leveling process (FIG. 9) of step 908. By checking the level information for each flip-flop, the flip-flop to be subjected to the wave pipeline processing is extracted. Next, in the input / output wiring length sum extraction step of step 1002, the sum of the wiring lengths in the modified layout is extracted for the input side and the output side of the flip-flop extracted in step 1001.

In the wire length predetermined value input step of step 1003, a wire length predetermined value used for determining whether or not to execute an adjustment process in a subsequent stage is input.
Then, in the buffer / inverter replacement processing in step 1004, the sum of the wiring length obtained in step 1002 is compared with a predetermined value of the wiring length input in step 1003 to determine whether to perform the replacement processing. decide. In the second embodiment, for a certain flip-flop, if the sum of the wiring lengths obtained in step 1002 exceeds the input predetermined value, the flip-flop is replaced with a buffer corresponding to the logic of its output. -Replace with an inverter circuit.

FIGS. 11 and 12 show the second embodiment.
FIG. 7 is a diagram for explaining a buffer / inverter replacement process in FIG. Hereinafter, the replacement of the flip-flop with the buffer / inverter circuit performed in step 1004 of the flow of FIG. 10 will be described with reference to these drawings.

FIG. 11 shows a non-wave pipelined circuit RT to be subjected to the wave pipeline processing.
It is a conceptual diagram of L description. The RTL description in FIG. 11 includes an input flip-flop group 1101, combinational logic circuits (pipeline stages) 1102 and 1104, a processing target flip-flop 1103, and an output flip-flop group 1105. The combinational logic circuit shown functions as the pipeline stage shown in FIG. The flip-flop group and the pipeline stage are connected by signal lines 1111 to 1114, respectively, and a clock 1121 is supplied to each flip-flop.

The combinational logic circuit 11 which is a pipeline stage located before the flip-flop 1103
From 02, the target FF input signal is output to the flip-flop 1103 via the signal line 1112. A flip-flop 1103 shown in FIG. 11 outputs a normal signal and an inverted signal. Signal
Further, a target FF inverted output signal is output through the signal line 1114.

In the wave pipeline processing according to the second embodiment, in the circuit (non-wave pipelined circuit) shown in FIG. It has become.

Except for the flip-flop 1103, the signal line 1112 for transmitting the input signal of the flip-flop 1103 is connected to the signal line 111 for transmitting the non-inverted output signal.
3, the capacitive load in the subsequent combinational logic circuit 1104 is the sum of the wiring load of the signal line 1112 transmitting the input signal and the wiring load of the signal line 1113 transmitting the non-inverted output signal. And this load is
A wiring capacitance larger than the wiring capacitance of the signal line 1112 which is the input of the flip-flop 1103 to be deleted (signal line 1
113 for the wiring load). Therefore, when the capacity of the combinational logic circuit 1104 with respect to the load is not sufficient, it is necessary to adjust the logic circuit or insert a repeater circuit as a relay buffer. Except for the flip-flop 1103, the same applies to a case where the wiring delay is increased due to the length of the directly connected wiring when the input / output wiring is directly connected.
Further, if only the input signal is used as the non-inverted output signal by direct connection, the inverted signal is not input to the combinational logic circuit at the subsequent stage, and the logic consistency cannot be maintained.

The buffer / inverter process in the second embodiment is performed to avoid such inconvenience. The buffer adjusts the load of the subsequent circuit and forms an inverted signal by the inverter. Ensure logical consistency. FIG. 12 is a diagram showing a buffer / inverter process for flip-flop 1103 (FIG. 11) according to the second embodiment.

As described above, in step 1004 in the flow of FIG. 10, if the sum of the input / output wiring lengths of the target flip-flop exceeds a predetermined value, a buffer / inverter replacement process is performed. 11, the signal line 1112 for transmitting the input signal of the target FF 1103,
When the sum of the wiring lengths of the signal line 1113 for transmitting the normal output signal and the signal line 1114 for transmitting the inverted output signal exceeds a predetermined value, the buffer / inverter replacement is performed.

The buffer / inverter replacement process according to the second embodiment is performed by the flip-flop 1103 shown in FIG.
Is replaced by the replacement buffer 1201 in FIG. As a result, it is possible to avoid the influence of the change in the wiring capacity and the delay time, and the replacement buffer 1
Since the output from the inverter of the inverter 201 is equivalent to the inverted output signal from the flip-flop 1103, the logical consistency is not disturbed.

The replacement buffer 1201 has a smaller circuit size than the target flip-flop 1103, and does not need to supply the clock 1221. Therefore, although the use of the replacement buffer 1201 slightly increases the circuit size as compared with the case where the replacement buffer 1201 is directly connected, the effect of reducing the circuit size and saving power by removing the flip-flop 1103 is not significantly impaired.

Returning to the flow of FIG. 10, step 1004
Step 100 after the buffer / inverter replacement process
The stage delay time adjustment step 5 is executed in accordance with the level acquired in step 908 of the flow in FIG. Adjustment processing is performed. Then, in step 1006, the input and output of the unsubstituted flip-flop are directly connected, and the target flip-flop is deleted.

In the subsequent netlist correction processing in step 1007, the netlist generated in step 904 in the flow in FIG. 9 is corrected, and the processing procedure in the flow in FIG. 10 ends. Returning to the flow of FIG. 9, the final netlist and the final layout are output, and the processing procedure shown in the flow of FIG. 9 ends.

The following is the evaluation processing of the second embodiment in the flow of FIG. 9 (steps 905 to 908 in FIG. 9).
And the wave pipeline processing (step 90 in FIG. 9).
9 and 10) will be further described with reference to FIGS. FIG. 13 is a conceptual diagram of an RTL description showing a part of a non-wave pipelined circuit, and shows a relationship between one combinational logic circuit (pipeline stage) and flip-flop groups arranged before and after it. It is. As shown, the combinational logic circuit 132
A flip-flop group 1310 is arranged at a stage preceding 0 and a flip-flop group 1330 is arranged at a stage subsequent to 0. The flip-flop group 1310 includes flip-flops 1311 to
1314; combinational logic circuit 1320; logic gates 1321 to 1326;
Include flip-flops 1331 to 1333, respectively. Note that, in this figure, clock signals supplied to the flip-flops and the combinational logic circuit are omitted.

The connection relationship between the flip-flop group 1310 and the combinational logic circuit 1320 is as follows.
The output from 311 is to logic gate 1331 and the output from flip-flop 1312 is to logic gates 1331 and 1331.
32, the output from flip-flop 1313 is input to logic gates 1332 and 1333, and the output from flip-flop 1314 is input to logic gate 1333.

The connection inside the combinational logic circuit is such that the output of logic gate 1321 is
5, the output of the logic gate 1322 is
5, the output of the logic gate 1323 is
The outputs of the logic gates 1324 and 1325 are input to the logic gate 1326.

The connection between the combinational logic circuit 1320 and the flip-flop group 1330 is determined by the logic gate 1326.
Is output to the flip-flop 1331, the output from the logic gate 1325 is input to the flip-flop 1332, and the output from the flip-flop 1323 is input to the flip-flop 1333.

The data to be processed passes through one of the paths in the connection relationship as described above. It is approximately proportional and becomes larger as the number of logic gates passing therethrough increases. Therefore, for example, the data is input from the flip-flop 1313 to the logic gate 1322 of the combinational logic circuit, and the flip-flop 1332
, The delay time when the flip-flop 1314
The delay time when the signal passes through the logic gate 1323 to the flip-flop 1333 is larger than the delay time,
11 to the logic gate 1321 to the logic gate 1324 to the logic gate 1326 to the flip-flop 1331.

FIG. 14 is a timing chart showing the operation when a signal is transmitted at a certain timing in the circuit configured as shown in FIG. FIG. 14A shows a clock, and the processing is executed in accordance with the rise of the clock signal. As shown in the figure, one unit in the clock signal is one cycle in the combinational logic circuit 1320, which is referred to as a processing stage cycle time (Tstage time). FIG. 14B shows the output from the flip-flop group 1310 in FIG. 13, and FIG. 14F shows the output from the flip-flop group 1330 in FIG. Further, (c), (d) and (e) show each flip-flop 1 included in the flip-flop group 1330 in FIG.
331, 1332, and 1333 are shown.

The combinational logic circuit 1320 shown in FIG.
Then, the output from the flip-flop group 1310 shown in FIG. In accordance with the rise of the clock signal shown in FIG. 14A, the output from the flip-flop group 1310 shown in FIG. 14B changes (data 1410).
This data is processed in the combinational logic circuit 1320, output to the flip-flop group 1330, and captured. Accordingly, after the elapse of the processing stage cycle time shown in FIG. 14A, the output from the flip-flop group 1330 shown in FIG. 14F becomes data 1420 corresponding to the data 1410. That is, the data 1420 holds the processing result of the combinational logic circuit 1320 on the data 1410 in the flip-flop group 1330 (the flip-flops 1331 to 1333) and outputs the data at the rising edge of the clock signal (FIG. 14A). It was done.

Here, each flip-flop included in the flip-flop group 1330 shown in FIGS. 14C to 14E will be considered. Since the input to the flip-flop 1331 passes through the logic gates within three stages in the combinational logic circuit 1320, a change appears after a maximum of T1 time as shown in FIG. Similarly,
Flip-flop 1 passing through logic gates within two stages
The input of 332 passes through the one-stage logic gate after a maximum of T2 time as shown in FIG. 14 (d). The input of the flip-flop 1333 has a maximum of T3 time as shown in FIG. 14 (e). Change appears. As aforementioned,
The greater the number of logic gates that pass, the greater the delay time, so that T1>T2> T3.

Here, a case is considered where the flip-flop group 1330 is to be subjected to wave pipeline processing. If the flip-flop group 1330 is simply deleted and the output of the combinational logic circuit 1320 is directly connected to the subsequent combinational logic circuit (pipeline stage), the signal corresponding to the data 1420 shown in FIG. , Only occurs in the period T4 shown in FIG. Here, T4 is a period that starts after the lapse of the time T1 after the data to be processed (data 1410) is provided to the combinational logic circuit 1320 and ends after the lapse of the time T3 after the subsequent data (data 1411) is provided. , The processing stage is shorter than the cycle time. Therefore, if simple deletion and direct connection are performed, the subsequent processing,
That is, the processing timing in the subsequent pipeline stage is disturbed.

In order to avoid such disturbance, FIG.
4, the delay time T2 and the delay time T3 may be adjusted to the longer delay time T1. With such an adjustment, the length of the period T4 becomes equal to the processing stage cycle time, so that the subsequent processing timing is not disturbed.

As described above, the magnitude of the difference between the delay time and the processing stage cycle time poses a problem in the wave pipelining process.・ It is a factor to determine that it is unnecessary. Therefore, in the second embodiment, as described above (step 906 in FIG. 9),
The maximum delay time and the processing stage cycle time are extracted, and the difference between the two is used in the classification process. In the second embodiment, as will be described later (FIG. 16), the difference is classified into three categories, large, medium, and small. The necessity / unnecessity of the adjustment process and the adjustment method are determined.

Another problem associated with the wave pipelining in the circuit shown in FIG. 13 will be described with reference to FIG. 13 is a timing chart of a case where signals are transmitted at the same timing as in FIG. 14 (different ratios in the drawing) in the circuit of FIG. 13, and the flip-flop included in the flip-flop group 1330 shown in FIG. Focusing on 1332, this shows input from different paths to the flip-flop. Same figure
The clock signal shown in (a) and the output from the flip-flop group 1310 shown in (b) are the same as in FIG. 15 (c) to (f) are signals input to the flip-flop 1332, which are input from different paths in the combinational logic circuit 1320.

FIG. 15 (c) is a circuit diagram of FIG.
This is a case where the signal passes through a path P1 from 325 to the flip-flop 1332, and the delay time is T2. This route P
Reference numeral 1 denotes a path having the largest delay time to the flip-flop 1332, and in this case, the delay time is the maximum delay time T2 for the input of the flip-flop 1332 shown in FIG.

FIG. 15D shows the state of the flip-flop 1313.
Through the path P2 from the logic gate 1321 to the logic gate 1325 to the flip-flop 1332, and the delay time is T5. FIG. 14E shows a flip-flop 1312, a logic gate 1322, and a logic gate 1325.
This is the case where the signal passes through the path P3 of the flip-flop 1332, and the delay time is T6. FIG. 11F shows the flip-flop 1314 to the logic gate 1322 to the logic gate 1
The delay time is T7 through a route P4 from 325 to the flip-flop 1332. As shown, these delay times T5 to T7 are all smaller than the maximum delay time T2, and have different sizes from each other, and T6 has the shortest delay time.

In the circuit shown in FIG. 13, if the flip-flop 1332 is simply deleted and a wave pipeline process for short-circuiting the input and output of the flip-flop is performed, the data shown in FIG. A signal corresponding to a part of 1420 occurs only in the period of T8 shown in FIG. Here, T8 is a period that starts after the lapse of the time T2 after the data to be processed (data 1410) is provided to the combinational logic circuit 1320 and ends after the lapse of the time T6 after the subsequent data (data 1411) is provided. , The processing stage is shorter than the cycle time. Therefore, if simple deletion and direct connection are performed, the flip-flop 13 in the circuit of FIG.
The subsequent processing using the output of 32, that is, the processing timing in the subsequent pipeline stage is disturbed.

To avoid such a disturbance, FIG.
The adjustment process of adjusting the delay times T5 to T7 shown in (1) to the longer delay time T2 is considered. If the maximum delay time T2 makes the illustrated T8 sufficiently close to the processing stage cycle time,
The effect on the subsequent processing can be avoided only by adjusting in this way. Further, depending on the size of T2, by further adjusting the delay time T2 to be equal to T1, as described above, the length of the period T8 is made equal to the processing stage cycle time, and the subsequent processing timing is disturbed. You can not.

As described above, for a certain flip-flop, the variation in the delay time of the signal input to the flip-flop is a problem in the wave pipeline processing.
This is a factor that determines whether adjustment processing is necessary or not. Therefore,
In the second embodiment, as described above (step 906 in FIG. 9), a delay time difference value (difference value between the maximum delay time and the minimum delay time) is extracted as the time characteristic and used for the classification process. . In the second embodiment, as will be described later (FIG. 16), the difference is classified into three types, large, medium, and small, and whether or not the flip-flop is to be deleted is adjusted. The necessity / unnecessity of the processing and the adjustment method are determined.

FIG. 16 is a diagram for explaining the classification processing and leveling according to the second embodiment. As shown in the figure, in the second embodiment, the cycle / delay time difference value and the delay time difference value are classified into large, medium, and small, respectively, and the classification is performed by combining the two.
Then, as shown, a level is determined for each classification obtained by the combination.

When both the cycle / delay time difference value and the delay time difference value are classified as "small", the level is set to level 1. In this case, the maximum delay time T1 becomes a value close to the processing stage cycle time Tstage as shown in FIG. 14C (the flip-flop 1831 in FIG. 13), and as shown in FIG. The delay time for each input from different paths also has little variation.
Even if such a flip-flop is simply deleted and short-circuited, it has little effect on subsequent processing. Therefore, FIG.
As shown in FIG. 6, in the second embodiment, wave pipelining is performed on this level without performing adjustment processing.

When the cycle / delay time difference value is “medium” and the delay time difference value is “small”, the level is set to level 2. In this case, as shown in FIG. 14D (flip-flop 1832 in FIG. 13), the maximum delay time is somewhat different from the processing stage cycle time, and the variation in input delay time as shown in FIG. 15 is small. Things. In the second embodiment, in the case of this level, in the example of FIG. 14, a wave pipeline including an adjustment process for making T2 and the like equal to T1 is performed. This is referred to as adjustment type 1 wave pipeline processing.

When the cycle / delay time difference value is “small” and the delay time difference value is “medium”, the level is set to level 3. In this case, there is some variation in the input delay time as shown in FIG. 15, and as shown in FIG. 14 (c) (the flip-flop 1831 in FIG.
Is a value close to the processing stage cycle time Tstage. In the second embodiment, in the case of this level, in the example of FIG. 15, an adjustment process is performed such that T5 and the like are aligned with T2. This is referred to as adjustment type 2 wave pipeline processing.

As the adjustment processing of the adjustment types 1 and 2, an adjustment circuit as shown in FIGS. 17 and 18 can be inserted. FIG. 17 is a diagram illustrating an example of the adjustment type 1 in the case of the level 2. Comparing FIG. 13 with FIG. 13, in this example, an adjustment circuit 1750 is added to the path from the combinational logic circuit 1720 to the flip-flop 1732 (the object to be deleted in the wave pipelining). In the case of level 2, the input to the target flip-flop 1732 has little variation depending on the path in the combinational logic circuit 1720 and does not require adjustment. On the other hand, the difference between the delay time of the input to the flip-flop 1732 and the processing stage cycle time is such that adjustment is required.
To avoid affecting the subsequent processing.

FIG. 18 is a diagram showing an example of the adjustment type 2 in the case of level 3. Comparing FIG. 13 with FIG. 13, in this example, the logic gates 1821, 1822, and 1 in the combinational logic circuit 1720
Adjustment circuits 1851, 1852, and 1853 are added to the stage preceding 825. This allows the logic gate 1821 or 1822 to switch from the logic gate 18
25, the delay time in the path leading to the flip-flop 1732 (to be deleted in the wave pipeline) is adjusted. In the case of level 3, the input to the target flip-flop 1732 has some variation depending on the path in the combinational logic circuit 1820 and needs to be adjusted. On the other hand, the difference between the delay time of the input to the flip-flop 1732 and the processing stage cycle time is such that no adjustment is required. Therefore, the adjustment circuits 1751 to 1753 inside the combinational logic circuit 1820 avoid the influence on the subsequent processing due to the deletion of the flip-flop 1832.

Referring back to FIG. 16, one or both of the cycle / delay time difference value and the delay time difference value are “large”.
If it is classified as, it will be level 4. Also, when both are classified as "medium", the level is level 4. In such a case, if the target is to be made into a wave pipeline, the above-described adjustment processing is required, and a large number of adjustment circuits as shown in FIGS. 17 and 18 must be inserted. In addition, the effect of wave pipelining by removing flip-flops is greatly impaired. Therefore, in the second embodiment, the flip-flop corresponding to level 4 is not subjected to the wave pipelining.

As described above, according to the integrated circuit design method of the second embodiment, the evaluation processing (steps 905 to 90 in FIG. 9) is performed.
By performing 8), the flip-flop to be subjected to the wave pipeline is determined. In the evaluation process, as shown in FIG. 16, the classification and the level corresponding to the temporality of each flip-flop are performed. By performing the conversion, it is possible to perform appropriate adjustment. In addition, the wave pipeline processing (step 909 in FIG. 9, FIG.
0), the buffer / inverter replacement process (step 150 in FIG. 10) is performed based on the input / output wiring length for each flip-flop to be wave pipelined.
By performing 4), it is possible to complement the classification and leveling processing, secure the consistency of logic, and perform appropriate wave pipelining.

Embodiment 3 The integrated circuit design method according to the third embodiment of the present invention performs an optimization process (adjustment process) using a library value along with the wave pipeline. Also in the third embodiment, an integrated circuit is designed in accordance with the processing procedure shown in FIG. 9 as in the second embodiment. Become. In the second embodiment, the processing procedure shown in FIG. 10 is executed in the wave pipelining step (step 909 in FIG. 9). In the third embodiment, the processing procedure shown in the flowchart in FIG. Is what you do. Hereinafter, the processing procedure of the wave pipeline processing according to the third embodiment will be described with reference to the flow of FIG.

The extraction of the target flip-flop in step 1901, the extraction of the sum of the input / output wiring length in step 1902, and the input of the predetermined wiring length in step 1903 are executed in the same manner as steps 1001 to 1003 in the flow of FIG. In the second embodiment, the buffer / inverter replacement processing is performed thereafter, but in the third embodiment, the processing is not immediately performed.

In the following step 1904, a temporary library conversion process is performed. Here, the library value is a database (library) called a cell library used in logic synthesis. The setup time, the hold time, the delay time, and the like set as the characteristic value of each flip-flop. The setup time, hold time, and the like will be described later. Also in the third embodiment, since the same evaluation processing as in the second embodiment (steps 905 to 908 in FIG. 9) is performed, a wave pipeline processing step (step 909 in FIG. 9) is performed.
In, each flip-flop is classified and leveled. Therefore, in this step 1904, the flip-flop to be subjected to the wave pipeline processing (extracted in step 1901)
Is replaced with a temporary flip-flop having a library value corresponding to the determined level (classification). In the process of step 1904, it is possible to simply replace the flip-flop. However, here, the replacement involves the insertion of a delay circuit to the input terminal of the temporary flip-flop.

In the subsequent placement and wiring information input step of step 1905, cell layout and wiring capacity are extracted from the layout before the wave pipeline processing, and the extracted information is read. In the delay time adjustment step of step 1906, the delay time of the path to the temporary flip-flop replaced in step 1904 is adjusted in accordance with the constraint based on each temporary library value. This adjustment process can be performed using an automatic logic synthesis tool or the like.

In the area / power consumption increase extraction step of step 1907, an increase in circuit area and an increase in power consumption in the adjustment processing in step 1906 are extracted.
Then, in the determination step of the subsequent step 1908, the increase in the area / power consumption obtained in step 1907 is compared with the decrease due to the elimination of the flip-flop. Shall not be performed. Therefore, step 190
If the determination in step 8 indicates "processing unnecessary", the subsequent processing is not executed, thereby substantially eliminating step 19.
Replacement of flip-flop in step 04 and step 19
To undo the result of the adjustment process in 05,
The wave pipelining process ends.

If the determination in step 1908 indicates "processing required", that is, if the reduction due to the flip-flop deletion exceeds, the subsequent step of the flow in FIG. 19 is executed. Subsequent buffer / inverter replacement processing in step 1909 is performed in step 1 of the flow in FIG.
Therefore, in the third embodiment, the replacement process using the buffer / inverter circuit is performed only when the sum of the input / output wiring lengths is larger than a predetermined value, as in the second embodiment. It will be. The deletion of the target flip-flop in step 1910 and the modification of the netlist in step 1911 correspond to step 100 in FIG.
6 and 1007, and the third embodiment is executed.
Is completed.

Here, the temporary library conversion in step 1904 will be described with reference to FIGS. 20 and 21.
FIG. 20 is a diagram showing a part of a circuit to be wave pipelined, and FIG. 21 is a timing chart for explaining a delay state of a signal input to a flip-flop included in the circuit of FIG. It is.

The circuit shown in FIG. 20 has a combinational logic circuit 2020 which is a pipeline stage and its input side,
And output side flip-flop groups 2010 and 2
030. The flip-flop groups 2010 on the input side include flip-flops 2011 to 2014.
However, the flip-flop group 2030 on the output side includes flip-flops 2031 to 2034. As in FIG. 13 and the like, the clock signal supplied to each part is omitted.

FIG. 21 shows a signal delay state in the circuit of FIG. FIG. 7A shows a clock signal, and the processing stage cycle time, which is one cycle of the combinational logic circuit 2020 (pipeline stay), is as follows.
It is Tstage shown in the figure.

Each of the flip-flops 2031 to 2034 of the output-side flip-flop group shown in FIG. 20 takes in the output from the combinational logic circuit 2020 in synchronization with the rise of this clock signal.

FIGS. 21B to 21E show delay times of signals input to the flip-flops 2031 to 2034. FIG. As described above, the signal input to each flip-flop has a different delay time depending on the path. For the flip-flop 2031, the maximum delay time is TD (2031, max) shown in FIG. The delay time is TD (2031, min). Flip-flop 203
The same applies to 2 to 2034, and the maximum and minimum delay times are as shown in FIGS.

In the third embodiment, each of the flip-flops is classified according to two criteria in the temporary library conversion. The first criterion is whether the difference between the processing stage cycle time and the maximum delay time of the flip-flop input is greater than a first predetermined value, and the second criterion is the maximum delay of the flip-flop input. Whether the difference between the time and the minimum delay time is greater than a second predetermined value. In FIG. 21, the first predetermined value is Ta, and the second predetermined value is Tb. The four cases shown in FIGS. 4B to 4E are examples showing four classifications using the first and second criteria.

The flip-flop 2031 shown in FIG.
For the first criterion, the processing stage cycle time
The difference between Tstage and TD (2031, max), which is the maximum delay time of the flip-flop input, is smaller than a first predetermined value Ta,
Regarding the second criterion, the difference Ts2031 between the maximum delay time TD (2031, max) and the minimum delay time TD (2031, min) of the flip-flop input is smaller than a second predetermined value Tb. . In such a case, even if the flip-flop is simply deleted, the influence on the subsequent processing is small. Therefore, in the third embodiment, FIG.
No replacement is performed in the temporary library conversion in step 1904, and the adjustment processing in step 1906 is not substantially performed.

The flip-flop 2032 shown in FIG.
For the first criterion, the processing stage cycle time
The difference between Tstage and TD (2032, max), which is the maximum delay time of the flip-flop input, is smaller than a first predetermined value Ta,
Regarding the second criterion, the difference Ts2032 between the maximum delay time TD (2032, max) and the minimum delay time TD (2032, min) of the flip-flop input is larger than the second predetermined value Tb. . In such a case, the subsequent processing is affected.
Replace with a temporary flip-flop. Here, the temporary flip-flop used for the replacement has a hold time, which is one of its characteristics, a time Th obtained by subtracting the second predetermined value Tb from the processing stage cycle time Tstage. As a result, by performing the adjustment processing in step 1906 of FIG. 19, the time corresponding to Ts2032 shown in FIG. 21C is set to be smaller than Tb, thereby avoiding the influence on the subsequent processing. .

The flip-flop 2033 shown in FIG.
For the first criterion, the processing stage cycle time
The difference Td2033 between Tstage and the maximum delay time TD (2033, max) of the flip-flop input is larger than the first predetermined value Ta, and for the second reference, the maximum delay time TD ( 2033, max) and the minimum delay time TD (2033,
min) is smaller than the second predetermined value Tb. As described above, in the replacement process in step 1904 in FIG. 19, a delay circuit is also inserted. In such a case, the time difference Td
A delay circuit that causes a delay of 2033 is inserted before the flip-flop 2033. This avoids the influence on the subsequent processing, and does not perform the replacement in the temporary library conversion in step 1904 in FIG.
06 is not substantially performed.

The flip-flop 2034 shown in FIG.
For the first criterion, the processing stage cycle time
The difference Td2034 between Tstage and the maximum delay time TD (2034, max) of the flip-flop input is larger than the first predetermined value Ta, and for the second reference, the maximum delay time TD ( 2034, max) and the minimum delay time TD (2034, max)
min) is larger than the second predetermined value Tb. In such a case, a delay circuit that causes a delay corresponding to the time difference Td2034 is inserted before the flip-flop 2034, and is replaced with a temporary flip-flop. Here, the temporary flip-flop used for the replacement has a hold time, which is one of its characteristics, a time Th obtained by subtracting the second predetermined value Tb from the processing stage cycle time Tstage. As a result, similarly to the case of the flip-flops 2032 and 2033, the influence on the subsequent processing is avoided.

Here, the change of the library value will be described with reference to FIGS. 22 and 23. FIG. 22 is a diagram showing a part of a circuit to be subjected to the wave pipeline processing, and FIG. 23 is a timing chart showing a state of the output side flip-flop in the circuit of FIG.

The circuit shown in FIG. 22 includes a combinational logic circuit 2220 which is a pipeline stage, its input side flip-flops 2211 and 2212, and its output side flip-flop 2231. A signal 2251 is provided.

The signal A is input from the input side flip-flop 2211 and the signal B is output from the input side flip-flop 2212.
Is input to the combinational logic circuit 2220, which generates an output signal C according to the combinational logic using the input signals A and B as variables and outputs this to the output-side flip-flop 2231. The output side flip-flop 2231 captures the output from the combinational logic circuit 2220 in accordance with the rising of the supplied clock signal 2251.

Consider a case where logic synthesis is performed on an RTL description of a circuit as shown in FIG. As described above, a library (database called a cell library) is generally used in logic synthesis.
In logic synthesis using a library, first, FIG.
A portion corresponding to each flip-flop illustrated and a portion corresponding to a combinational logic circuit are extracted and separated from the RTL description having the above configuration. Then, each separated flip-flop equivalent portion is assigned to a flip-flop cell in the library, and the combinational logic circuit equivalent portion is replaced with a logic circuit cell (for example, a NAND circuit cell or a NOR circuit cell) in the library.

When such a logical configuration is completed, delay information is extracted from each library for each cell, and it is checked whether or not a constraint called a timing constraint is satisfied. Or equivalent conversion of logic or the like, and performs a deformation process so as to satisfy the timing constraint. If the constraints are satisfied, a netlist is output for the configured logic circuit. If necessary, processing for minimizing the area may be executed before outputting the netlist. In addition, when delay information is extracted from the library, the load capacity is estimated using the temporary wiring capacity model, and the load capacity dependent component in the delay time is calculated.

FIG. 23 shows an operation state after the combination. In FIG. 22, a combinational logic circuit 2220
Are input side flip-flops 2211 and 2212
The arithmetic processing is performed on the signals A and B input from the. At this time, due to a delay in a logic circuit cell or the like constituting the combinational logic circuit 2220, a certain data indefinite period occurs, and the combinational logic circuit 2220
Path that produces the largest delay time in the network (critical path)
If the critical path time elapses,
The data output from the combinational logic circuit 2220 is determined.

The output-side flip-flop 2231 captures and holds the data output from the combinational logic circuit 2220 in accordance with the rise of the clock signal 2251. Generally, the flip-flop generally has a setup time and a hold time before and after the rise of the clock signal. This requires a data confirmation period called time. The set-up time and the hold time indicate the time characteristic of the flip-flop, and in FIG. 23, the set-up time Tsetup and the hold time Thold are periods illustrated.

When these are taken into consideration, the timing constraints in the logic synthesis are given as the following two simultaneous inequalities. Input flip-flop delay time + combinational logic circuit delay time + setup time ≦ 1 cycle time Input flip-flop delay time + combinational logic circuit delay time ≧ hold time In a library in which flip-flop cells are registered, generally, each registered flip-flop cell is registered. The setup time and the hold time are set for each time. That is, when library values such as setup time and hold time are changed,
The change may not satisfy the timing constraints.

Therefore, as in the third embodiment, the provisional library conversion processing for performing the replacement with the provisional flip-flop (when the step 1904 in FIG. 19 is performed, the timing constraint condition may not be satisfied at this stage. This is based on the premise that readjustment will be performed in the subsequent optimization processing, where optimization processing is a method that has become popular with the recent miniaturization of LSIs. Due to the miniaturization of the LSI, the actual wiring capacitance delay simulation after layout (step 90 in FIG. 9)
When 4) is performed, the wiring capacity deviates significantly from the above-described temporary wiring capacity model, and a sudden increase in wiring capacity that cannot be predicted at the stage of logic synthesis may occur. In some cases, timing constraints may not be satisfied due to a large increase in wiring capacitance.
It is supposed to occur quite frequently. Therefore, optimization of a circuit after synthesis using actual wiring capacity information and cell placement information (Location Based Optimization: LBO, In P
lace Optimization (IPO) method was devised. According to this method, the actual wiring capacity information and cell arrangement information are read, and the actual wiring capacity is used to replace the overloaded cell with a cell having a driving capacity corresponding to the load capacity, or By dividing a long wiring or the like, adjustment is made so that only a portion that does not satisfy the timing constraint condition is changed.

In the third embodiment, the necessary timing is assigned as a setup time or a hold time of the temporary flip-flop, and the temporary flip-flop is replaced with the flip-flop to be subjected to the wave pipeline (see FIG. 19). In step 1904), a condition that does not satisfy the timing constraint condition is once created, and processing is performed by the above-described optimization method. By changing only that part, the timing constraint condition is appropriately satisfied and the final condition is satisfied. The purpose is to achieve the timing necessary for the pipeline processing.

That is, in the third embodiment, a buffer / inverter replacement process based on the input / output wiring length is executed as an optimization process, similar to the second embodiment. Prior to such optimization processing, the amount of increase in area and increase in power consumption is acquired as the amount of variation (optimization variation) by the optimization process, and the obtained amount is evaluated to determine whether or not to execute the optimization. It is.

As described above, according to the integrated circuit design method of the third embodiment, in the wave pipelining process (step 909 in FIG. 9), the temporary library conversion step (step 1904 in FIG. 19) is executed. By replacing the flip-props to be subjected to the wave pipeline with temporary flip-flops, it is possible to perform appropriate wave pipeline by the evaluation processing as in the second embodiment. Even if it is difficult to make sufficient adjustments based on simulations due to the miniaturization and complexity of circuits, it is possible to realize the necessary timing state by adapting to the conditions such as the actual wiring capacity by the subsequent optimization processing. Become.

In the third embodiment, the wave pipelining step (step 9) in the processing procedure shown in FIG.
09), the library conversion processing is performed. However, the same library conversion processing may be performed in the wave pipelining step (step 106) in the processing procedure shown in FIG. 1 (Embodiment 1). It is possible. In this case, the stage delay time adjustment processing (step 20) in the procedure of the wave pipeline shown in FIG.
Subsequent to 4), library conversion processing is performed in the same manner as in the third embodiment, and accordingly, step 190 in FIG.
The same effect can be obtained by executing the adjustment processing as shown in FIG.

In the second embodiment and the third embodiment, the designation is read in step 905 in FIG. 9 to perform the classification as shown in FIG.
Although each flip-flop is classified in step 907 based on the time characteristic acquired in step 6, it is also possible to read the classification method and the processing level after first acquiring all the time characteristic values. is there. However, if it is assumed that the classification method and the like are to be obtained in advance according to the processing procedure shown in the second embodiment, this information can be used, for example, to process the flip-flop that is not at the processing target level. By omitting a part or the like, it is possible to improve the processing efficiency.

In the second embodiment and the third embodiment, a predetermined value of the wiring length is input in step 1003 of FIG. 10 and step 1903 of FIG. 19, and this value is used. When it is desired to delete all flip-flops in a specific portion of the circuit, the predetermined value input in the step is set to a value of 0.
It is also possible to delete all at once. In such a case, step 1002 (FIG. 10) or step 19
It is also possible to improve the efficiency of the process by omitting the process of extracting the sum of the input / output wiring lengths in step 02 (FIG. 19).

[0140]

According to the integrated circuit design method of the first aspect,
An integrated circuit design method for designing a pipeline circuit including a plurality of processing stages by performing synthesis processing, placement and wiring processing, and real wiring capacity simulation processing using register transfer level description in a hardware description language, Wave pipeline processing including non-wave pipeline processing circuits generated by the synthesis processing, the placement and wiring processing, and the real wiring capacity simulation processing, including the deletion of some of the components and the adjustment processing accompanying the deletion. By performing processing, R
For a non-wave pipelined circuit designed according to a general ASIC design method with a TL description, a wave pipeline including an adjustment process that can avoid inconvenience caused by a large difference in delay time that can occur in a logic circuit. Therefore, it is possible to easily design a wave pipeline circuit having a large power saving effect.

According to the integrated circuit design method of the second aspect, in the method of the first aspect, in the wave pipelining process, the designated data temporary holding means is deleted, so that power consumption is reduced. The above-mentioned effect can be obtained by designing so as to omit the temporary holding means having a large size, and by designing to suppress the clock supply.

According to the integrated circuit design method of the third aspect, in the method of the second aspect, the wave pipelining process extracts the specified data temporary holding means from the non-wave pipelined circuit. The designated temporary holding means extraction processing and the stage delay time for obtaining the delay time for the processing of specific data in the preceding and following processing stages when the extracted data temporary holding means is deleted and the preceding and following processing stages are directly connected. Acquisition processing, performing a comparison process using the delay time acquired in the stage delay time acquisition process, according to the result of the comparison process, accompanying the deletion of the specified data temporary holding unit,
By including the delay time adjustment processing for adjusting the delay time, the adjustment processing is performed according to the delay time before and after the data temporary holding unit to be deleted. It is possible to avoid a problem caused by a difference in delay time, which may occur when a proper deletion process is performed, by the adjustment process.

According to the integrated circuit design method of the fourth aspect, in the method of the third aspect, the delay time adjustment processing is performed on specific data in a processing stage located before the designated data temporary holding means. If the holding time is smaller than a predetermined value, the holding time is extended by inserting a delay means, so that the effective data output period is not too short because the delay time is too short. Since the adjustment is performed as described above, it is possible to avoid a problem due to the wave pipeline.

According to the integrated circuit design method of the fifth aspect, in the method of the first aspect, the delay time adjustment processing is performed for specific data in a processing stage located before the designated data temporary holding means. When the holding time is smaller than the predetermined value, by inserting the temporary holding means for adjustment, the holding time is extended,
Since the data output from the preceding processing stage is adjusted so that it is processed according to the subsequent clock,
When the problem due to the wave pipeline is avoided and the difference between the delay times is relatively large, the circuit scale can be made smaller than when a delay unit is inserted.

According to a sixth aspect of the present invention, in the third aspect of the present invention, the delay time adjustment processing is performed for a specific data in a processing stage located before the designated data temporary holding means. If the holding time is smaller than a predetermined value, the specified data temporary holding unit is not deleted, and is used as an adjustment temporary holding unit. Since adjustments are made, problems due to wave pipelining can be avoided, and if the difference in delay time is relatively large,
It is possible to reduce the circuit size more than inserting delay means.

According to a seventh aspect of the present invention, in the method of the fifth or sixth aspect, the delay time adjusting process includes adjusting a phase of a clock supplied to the temporary holding means for adjustment. By further including processing, data output from the preceding processing stage is adjusted so that it is processed in response to the appropriately delayed clock, so that problems due to wave pipelining can be avoided. However, when the difference between the delay times is relatively large, it is possible to reduce the circuit size more than inserting delay means.

According to the integrated circuit design method of the eighth aspect, in the method of the first aspect, a part of the components to be deleted is determined by an evaluation process. And the fact that the data temporary holding means is deleted in accordance with the above-mentioned determination, with an adjustment process for the non-wave pipelined circuit, which can avoid inconvenience caused by a large difference in delay time that can occur in the logic circuit. Since a wave pipeline is formed to delete the specified component according to the evaluation processing, it is possible to easily design a wave pipeline circuit having a large power saving effect.

According to a ninth aspect of the present invention, in the method of the eighth aspect, the evaluation processing is performed for each of the data temporary holding units included in the non-wave pipelined circuit. And a classification process for classifying each data temporary holding means based on the acquired time characteristic value. Is to delete the temporary data holding means according to the above classification, so that the temporary holding means consuming a large amount of power is omitted according to the classification, and the above-mentioned effect is obtained by designing to suppress the clock supply.

According to the integrated circuit design method of claim 10,
10. The method according to claim 9, wherein the evaluation processing includes, for each of the data temporary holding means, whether or not the data temporary holding means is to be deleted, and an adjustment processing associated with the deletion, based on a result of the classification processing. The method further includes a level determination process for giving level information indicating whether or not it is necessary or unnecessary, and the type. In the wave pipelining process, the data temporary holding unit is deleted and the adjustment process is performed according to the level information. Thus, it is possible to determine whether or not deletion is possible and necessary adjustment processing based on the classification processing and the level determination processing, and perform appropriate wave pipelining.

According to the integrated circuit design method of claim 11,
2. The method according to claim 1, wherein, in the wave pipelining process, the temporary data holding means is deleted, and the wiring lengths of the data temporary holding means to be deleted on the input side and the output side thereof are set. If the extracted wiring length exceeds a predetermined value, the temporary data holding means is replaced with a buffer circuit, thereby removing the temporary data holding means and increasing the capacity load. , It is possible to perform appropriate wave pipeline processing.

According to the integrated circuit design method of the twelfth aspect,
12. The method according to claim 11, wherein when the temporary data holding means to be deleted outputs normal and inverted output signals, the replacement is performed by a buffer circuit including an inverter circuit. In addition, it is possible to perform an appropriate wave pipeline by avoiding the adverse effect on the logical consistency due to the deletion of the temporary data holding unit.

According to the integrated circuit design method of claim 13,
2. The method according to claim 1, wherein in the wave pipeline processing, the temporary data holding unit is deleted, and the library value of the temporary data holding unit to be deleted is By performing the library conversion processing for replacing the temporary data holding means having a different library value with the temporary data holding means and the optimization processing corresponding to the library conversion processing, the circuit can be miniaturized and the simulation can be performed based on the simulation. Even when the adjustment is difficult, it is possible to perform an appropriate wave pipeline by avoiding the adverse effect of deleting the data temporary holding unit.

According to the method of designing an integrated circuit of claim 14,
14. The method according to claim 13, wherein arrangement position information indicating an arrangement of each component in the pipeline circuit and actual wiring capacitance information indicating a wiring capacitance in the pipeline circuit are extracted. Since the above-described optimization processing is performed based on the arrangement position information and the actual wiring capacity information, appropriate optimization processing can be performed.

According to the integrated circuit designing method of claim 15,
14. The method according to claim 13, wherein an optimization variation amount indicating a change of the circuit due to the optimization processing is obtained.
By deciding whether or not to execute the above-mentioned optimization processing and whether or not to delete the above-mentioned temporary data holding means based on the above-mentioned obtained optimization fluctuation amount, the optimization processing which is basically a local processing is performed. Thereby, it is possible to avoid a situation in which the total area and power consumption increase.

According to the integrated circuit design method of claim 16,
14. The method according to claim 13, wherein the library conversion process is performed more flexibly by replacing the temporary data holding means and inserting a delay circuit near the replaced data temporary holding means. Adjustment can be performed.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a processing procedure of an integrated circuit design method according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing a detailed processing procedure of a wave pipelining process in the integrated circuit design method of the embodiment.

FIG. 3 is a diagram showing a first example of an adjustment process included in the wave pipelining process in the integrated circuit design method according to the embodiment;

FIG. 4 is a diagram for explaining data to be processed by a circuit in the integrated circuit design method according to the embodiment and threshold values in wave pipelining;

FIG. 5 is a timing chart showing an operation of the wave pipeline circuit that has been subjected to the adjustment processing of the first example in the integrated circuit design method according to the embodiment;

FIG. 6 is a diagram illustrating a second example of the adjustment processing included in the wave pipeline processing in the integrated circuit design method according to the embodiment;

FIG. 7 is a diagram illustrating a third example of the adjustment processing included in the wave pipeline processing in the integrated circuit design method according to the embodiment;

FIG. 8 is a timing chart showing an operation of the wave pipeline circuit that has been subjected to the adjustment process of the second example in the integrated circuit design method of the embodiment.

FIG. 9 is a flowchart illustrating a processing procedure of an integrated circuit design method according to a second embodiment of the present invention;

FIG. 10 is a flowchart showing a detailed processing procedure of a wave pipelining process in the integrated circuit design method of the embodiment.

FIG. 11 is a diagram showing a circuit before replacement for explaining a buffer / inverter replacement process in the integrated circuit design method according to the embodiment;

FIG. 12 is a diagram showing a circuit after replacement for describing a buffer / inverter replacement process in the integrated circuit design method according to the embodiment;

FIG. 13 is a diagram showing a circuit to be subjected to a wave pipeline process for explaining a delay time adjustment process in the integrated circuit design method according to the embodiment;

FIG. 14 is a timing chart illustrating a delay time adjustment process in the integrated circuit design method according to the embodiment;

FIG. 15 is a timing chart for explaining a delay time adjustment process in the integrated circuit design method according to the embodiment;

FIG. 16 is a diagram for explaining a classification method and a processing level in the integrated circuit design method of the embodiment.

FIG. 17 is a diagram showing a circuit in which adjustment of adjustment type 1 has been performed, for describing a delay time adjustment process in the integrated circuit design method according to the embodiment;

FIG. 18 is a diagram showing a circuit in which adjustment of adjustment type 2 has been performed, for explaining a delay time adjustment process in the integrated circuit design method of the embodiment.

FIG. 19 is a flowchart showing a processing procedure of a wave pipelining process in the integrated circuit design method according to the third embodiment of the present invention.

FIG. 20 is a diagram showing a circuit to be subjected to a wave pipeline process for explaining a temporary library conversion process in the integrated circuit design method according to the embodiment;

FIG. 21 is a timing chart for explaining temporary library conversion processing in the integrated circuit design method of the embodiment.

FIG. 22 is a diagram showing a circuit to be subjected to a wave pipeline process for describing a temporary library conversion process in the integrated circuit design method according to the embodiment.

FIG. 23 is a timing chart for explaining temporary library conversion processing in the integrated circuit design method of the embodiment.

FIG. 24 is a diagram for describing an RTL description of a pipeline circuit according to a conventional integrated circuit design method.

FIG. 25 is a diagram for explaining an RTL description of a wave pipeline circuit according to a conventional integrated circuit design method.

FIG. 26 is a diagram for explaining a configuration of data to be processed by the pipeline circuit and a difference in delay time.

FIG. 27 is a timing chart showing an operation of a pipeline circuit designed by an integrated circuit design method according to a conventional technique.

FIG. 28 is a timing chart showing an operation of a wave pipeline circuit designed by an integrated circuit design method according to a conventional technique.

[Explanation of symbols]

S101, S901 RTL description / design constraint file reading step S102, S902 synthesis processing step S103, S903 placement and wiring processing step S104, S904 real wiring capacity simulation step S105 Wave pipeline creation designation file reading step S106, S909 Wave pipeline processing step S107, S9010 Result output step S201 Designated flip-flop extraction step S202 Stage delay time extraction step S203 Threshold value input step S204 Stage delay time adjustment step S205 Designated flip-flop deletion step S206 Netlist modification step S905 Classification method / processing level reading step S906 Time characteristic extraction processing step S907 Classification processing step 910 Leveling processing step S1001, S1901 Target flip-flop extraction step S1002, S1902 Input / output wiring length sum extraction step S1003, S1903 Wiring length predetermined value input step S1004, S1909 Buffer / inverter replacement processing step S1005, S1906 Stage delay time adjustment step S1006 S1910 Target flip-flop deletion step S1007, S1911 Netlist correction step S1904 Temporary library conversion step S1905 Placement and wiring information input step S1907 Area / power consumption increase extraction step S1918 Judgment step 301, 601, 701, 901, 1101, 240
1,2501 input flip-flop group 302,602,702,902,1102,240
2,2502 pipeline stage 2403 intermediate flip-flops 304,604,704,904,1104,240
4,2504 pipeline stage 305,605,705,905,1105,240
5,2505 output flip-flop group 308,607,1750,1801,1802,18
03 delay circuit 606, 706 flip-flop 1103 target flip-flop 1310, 1710, 1810, 2010 input-side flip-flop group 1320, 1720, 1820, 2020, 2220 combinational logic circuit 1330, 1730, 1830, 2030 output-side flip-flop group 1311 1312, 1313, 1314, 1331,
1332, 1333, 1711, 1712, 1713,
1714, 1731, 1732, 1733, 1811,
1812, 1813, 1814, 1831, 1832,
1833, 2011, 1021, 2013, 2014
2031, 2032, 2033, 2034, 2211,
2212, 2231 flip-flops 1321, 1322, 1323, 1324, 1325
1326, 1721, 1722, 1723, 1724,
1725, 1726, 1821, 1822, 1823,
1824, 1825, 1826 logic gates 321, 621, 721, 921, 1121, 225
1,221,5211 clocks 311,312,313,314,315,611,6
12,613,614,615,711,712,71
3,714,715,1111,1112,1113
1114, 1116, 2411, 2412, 2413,
2414, 2511, 2512, 2514 signal lines

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/82 W

Claims (16)

[Claims] An integrated circuit for designing a pipeline circuit including a plurality of processing stages by performing synthesis processing, placement and wiring processing, and real wiring capacity simulation processing using a register transfer level description in a hardware description language. In the design method, a non-wave pipelined circuit including the plurality of processing stages and the data temporary holding unit between the processing stages, which is generated by the synthesis processing, the placement and routing processing, and the actual wiring capacity simulation processing, And performing a wave pipelining process including a deletion of a part of the constituent elements and an adjustment process accompanying the deletion. 2. The integrated circuit design method according to claim 1, wherein the specified data temporary holding means is deleted in the wave pipeline processing. 3. The integrated circuit design method according to claim 2, wherein the wave pipelining process includes extracting the designated temporary data holding unit from the non-wave pipelined circuit. Processing, when the extracted data temporary holding means is deleted, and when the preceding and following processing stages are directly connected, a stage delay time obtaining process for obtaining a delay time for processing of specific data in the preceding and following processing stages; A delay time adjustment process that performs a comparison process using the delay time acquired in the stage delay time acquisition process, and adjusts the delay time in accordance with the result of the comparison process when the designated data temporary holding unit is deleted. And a method of designing an integrated circuit. 4. The integrated circuit design method according to claim 3, wherein the delay time adjustment processing is performed by setting a holding time for specific data in a processing stage located before the designated data temporary holding means. If the value is less than
A method for designing an integrated circuit, wherein the holding time is extended by inserting a delay means. 5. The integrated circuit design method according to claim 3, wherein the delay time adjustment processing is performed by setting a holding time for specific data in a processing stage located before the designated data temporary holding means. If the value is less than
A method for designing an integrated circuit, wherein the holding time is extended by inserting a temporary holding means for adjustment. 6. The integrated circuit design method according to claim 3, wherein the delay time adjustment processing is performed by setting a holding time for specific data in a processing stage positioned before the designated data temporary holding means. If the value is less than
An integrated circuit design method, wherein the designated data temporary holding means is used as an adjustment temporary holding means without being deleted. 7. The integrated circuit designing method according to claim 5, wherein the delay time adjusting process further includes a clock adjusting process for adjusting a phase of a clock supplied to the adjusting temporary holding unit. An integrated circuit design method characterized by the above-mentioned. 8. The integrated circuit design method according to claim 1, wherein a part of the constituent elements to be deleted is determined by an evaluation process. An integrated circuit design method for deleting temporary holding means. 9. The integrated circuit design method according to claim 8, wherein the evaluation processing includes, for each data temporary holding unit included in the non-wave pipelined circuit, a time indicating a characteristic of the data temporary holding unit. The method includes a time characteristic extraction process for acquiring a characteristic value, and a classification process for classifying each data temporary holding unit based on the acquired time characteristic value. An integrated circuit design method for deleting temporary data holding means. 10. The integrated circuit design method according to claim 9, wherein, in the evaluation process, whether the data temporary holding unit is to be deleted for each data temporary holding unit based on a result of the classification process. And a level determination process for giving level information indicating whether or not the adjustment process is necessary and the type of the deletion process, and the type of the adjustment process. In the wave pipelining process, the data temporary holding unit is deleted according to the level information. And an adjustment process. 11. The integrated circuit design method according to claim 1, wherein in the wave pipelining process, the temporary data holding unit is deleted. An integrated circuit for extracting a wiring length on an input side and an output side thereof and, when the extracted wiring length exceeds a predetermined value, replacing the data temporary holding means with a buffer circuit; Design method. 12. The integrated circuit designing method according to claim 11, wherein the data temporary holding unit to be deleted outputs a normal output signal and an inverted output signal, and the buffer includes an inverter circuit. An integrated circuit design method, wherein the above replacement is performed by a circuit. 13. The integrated circuit design method according to claim 1, wherein in the wave pipelining process, the data temporary holding unit is deleted. A library conversion process for performing replacement with a temporary data holding unit having a library value different from the library value of the data temporary holding unit, and an optimization process corresponding to the library conversion process are performed. Integrated circuit design method. 14. The integrated circuit design method according to claim 13, wherein arrangement position information indicating an arrangement of each component in the pipeline circuit, and actual wiring capacitance information indicating a wiring capacitance in the pipeline circuit. Wherein the optimization processing is performed based on the extracted arrangement position information and the actual wiring capacity information. 15. The integrated circuit design method according to claim 13, wherein an optimization variation indicating a change in the circuit due to the optimization processing is acquired. Based on the acquired optimization variation, An integrated circuit design method for determining whether the above-described optimization processing can be executed and whether the above-mentioned temporary data holding means can be deleted. 16. The integrated circuit designing method according to claim 13, wherein in said library conversion processing, said temporary data holding means is replaced with said temporary data holding means and a delay circuit is inserted near said replaced data temporary holding means. A method for designing an integrated circuit.