JP2007280222A - Design system of semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a design system of a semiconductor integrated circuit capable of reducing influence received by systematic manufacturing variations. <P>SOLUTION: This design system has an extracting module 12 extracting the systematic manufacturing variations from manufacturing variations information acquired from a shape measuring result of a basic pattern, an analytical pattern acquiring module 14 acquiring an analytical pattern shape of a basic circuit including the basis pattern by process simulation using a parameter provided from the systematic manufacturing variations and a performance result of the process simulation, a delay characteristic calculating module 15 calculating a signal delay characteristic of the basic circuit by using the analytical pattern shape, and a risk calculating module 16 calculating failure occurrence risk of causing failure caused by the systematic manufacturing variations in the basic circuit by comparing a design pattern shape of the basic circuit with the analytical pattern shape. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit design system, and more particularly to a design system that performs logic synthesis and layout information generation.

  In order to improve the yield of a semiconductor integrated circuit (LSI) configured by combining a plurality of standard cells (hereinafter simply referred to as “cells”), various countermeasures described below have been implemented. For example, in order to reduce the incidence of contact failure in a basic circuit such as a cell, there is a cell in consideration of yield improvement in which a plurality of vias connecting between wirings of different metal layers in a cell are arranged at each connection point. used. In order to reduce the incidence of contact failure in wiring, redundant vias (multiple vias) are arranged during or after wiring. A region having a high wiring density, which is predicted to have a high defect occurrence rate by lithography simulation, is extracted, and a wiring interval in the extracted region is widened. As a method of improving LSI performance degradation due to manufacturing variations, a library of cells (variation performance library) that is calculated assuming that the delay time of signals passing through the cell is assumed to be variable is used to calculate the statistical delay of the LSI. (For example, refer to Patent Document 1).

  However, the conventional LSI design does not take into account the effect of systematic manufacturing variations depending on the pattern on the performance of the LSI. “Systematic manufacturing variation depending on a pattern” (hereinafter, simply referred to as “systematic variation”) is a variation component of manufacturing variation with respect to a specific pattern shape. For example, it indicates that a normal wiring pitch is always transferred out of the shape of the target under the influence of a specific peripheral pattern. Conventionally, such systematic manufacturing variations have not been designed, and variations in patterns have occurred during manufacturing. Moreover, the design which avoids the deviation | shift from the shape of such a systematic target was not performed.

  Furthermore, in the past, a variation performance library has been created on the assumption that the distribution of signal delay variation in a cell or the like is a Gaussian distribution. However, a large error occurs when the actual distribution of signal delay variation is a non-Gaussian distribution. Arise. In general, systematic variations do not have a Gaussian distribution. For this reason, a variation performance library based on the premise that the distribution of signal delay variation is a Gaussian distribution cannot perform LSI performance analysis and performance optimization by accurately estimating manufacturing variation.

As described above, various problems occur in an LSI designed without considering the influence of systematic variations on the performance of the LSI.
Japanese Patent Laying-Open No. 2005-259107

  The present invention provides a semiconductor integrated circuit design system capable of reducing the influence of systematic manufacturing variations on a semiconductor integrated circuit.

  According to one aspect of the present invention, (b) an extraction module that extracts systematic manufacturing variation from manufacturing variation information acquired from the shape measurement result of the basic pattern; and (b) systematic manufacturing variation and process simulation execution results. Analysis pattern acquisition module that acquires the analysis pattern shape of the basic circuit including the basic pattern by process simulation using the obtained parameters, and (c) Delay characteristic calculation that calculates the signal delay characteristic of the basic circuit using the analysis pattern shape A module, and (d) a risk calculation module that compares the design pattern shape of the basic circuit with the analysis pattern shape and calculates a failure occurrence risk that a failure due to systematic manufacturing variation occurs in the basic circuit. Semiconductor integrated circuit design system It is provided.

  According to the present invention, it is possible to provide a semiconductor integrated circuit design system capable of reducing the influence of systematic manufacturing variations on the semiconductor integrated circuit.

  Next, first and second embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. Also, the following first and second embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the component parts. The structure and arrangement are not specified as follows. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
As shown in FIG. 1, the design system according to the first embodiment of the present invention is based on the shape measurement result of the basic pattern including circuit elements and wiring patterns formed under a plurality of manufacturing conditions. An information acquisition module 11 that acquires manufacturing variation information, an extraction module 12 that extracts systematic manufacturing variation with manufacturing reproducibility from the manufacturing variation information, a systematic manufacturing variation and a process simulation execution result. A parameter setting module 13 for setting parameters for process simulation, an analysis pattern acquiring module 14 for acquiring an analysis pattern shape of a basic circuit including a basic pattern by executing a process simulation using the set parameters, and an analysis pattern shape Using The delay characteristic calculation module 15 for calculating the signal delay characteristic of this circuit is compared with the shape of the design pattern of the basic circuit and the shape of the analysis pattern, and the failure occurrence risk that a defect due to systematic variation occurs in the basic circuit is determined. And a risk calculation module 16 for calculating.

  The “basic pattern” is a pattern of a circuit element such as a transistor constituting a cell such as a NAND circuit or a buffer, a wiring pattern, or the like. As will be described later, a plurality of basic patterns with different wiring arrangements and intervals are prepared for the circuit elements. The “manufacturing variation information” of the basic pattern is acquired as a variation in measured values when the shape of the basic pattern formed on the wafer is measured. That is, the manufacturing variation information is information on variation in a manufacturing process for forming cells and wirings.

  The “basic circuit” is a wiring pattern composed of a combination of cells or wirings and vias. That is, the “analysis pattern shape” is a cell pattern shape or a wiring pattern shape calculated by a process simulation.

  The information acquisition module 11, the extraction module 12, the parameter setting module 13, the analysis pattern acquisition module 14, the delay characteristic calculation module 15, and the risk calculation module 16 are included in the central processing unit (CPU) 10. The CPU 10 is included in the design unit 1. As shown in FIG. 1, the design system according to the first embodiment includes a design unit 1 and a measurement unit 2. The measurement unit 2 measures the shape of the basic pattern manufactured in a series of manufacturing processes.

  As shown in FIG. 2A, the delay characteristic calculation module 15 uses the analysis pattern shape to calculate the signal delay time of the basic circuit and the occurrence probability of the signal delay time, and the basic circuit. And a table creation module 152 that creates a delay characteristic table indicating the relationship between the input signal and the characteristic of the output load connected to the basic circuit and the signal delay characteristic including the signal delay time and the occurrence probability of the signal delay time. The delay characteristic calculation module 15 further includes a discrete probability calculation module 153 that calculates a discrete probability from the occurrence probability distribution of the signal delay time of the circuit. The “discrete probability” will be described later.

  As shown in FIG. 2B, the risk level calculation module 16 includes a cell risk level calculation module 161, a wiring risk level calculation module 162, and a layout risk level calculation module 163. The cell risk level calculation module 161 calculates the risk level of occurrence of a failure in which a failure due to systematic variation occurs in the cell. The wiring risk calculation module 162 calculates a failure occurrence risk that a failure due to systematic variation occurs in the wiring. The layout risk level calculation module 163 calculates a failure occurrence risk level at which a failure due to systematic variation occurs for the entire layout.

  “Defect occurrence risk” is defined as the degree of divergence of the analysis pattern shape calculated by the process simulation to which the variation parameter is applied from the design pattern shape. The greater the difference between the design pattern shape and the analysis pattern shape, the greater the risk of occurrence of defects. In the present embodiment, the risk of failure occurrence is defined as the ratio of the analysis pattern shape dimension to the design pattern shape dimension.

  1 is calculated using the signal delay characteristics of the basic circuit, the signal delay characteristics of the signal path configured by combining a plurality of basic circuits, and all included in the layout information including the plurality of signal paths. A change module 17 is further provided for changing the layout information to satisfy the permissible condition when at least one of the sums of the risk of occurrence of defects in the basic circuit does not satisfy the permissible condition.

  As shown in FIG. 2C, the change module 17 compares the sum of the failure occurrence risk of the basic circuit included in the layout information of the semiconductor integrated circuit with an allowable value, and the sum of the failure occurrence risk is allowed. The layout determination module 171 that determines whether or not the condition is satisfied, and the basic circuit included in the layout information are replaced with a basic circuit that has a low defect occurrence risk when the sum of the risk of defect occurrence does not satisfy the allowable condition A replacement module 172.

  Further, the change module 17 includes a danger placement detection module 173 that detects from the layout information of the semiconductor integrated circuit a circuit placement that increases the risk of occurrence of defects in the basic circuit due to systematic variations depending on the pattern shape of the adjacent circuit. And an arrangement correction module 174 that changes the detected circuit arrangement to reduce the risk of circuit failure.

  Further, the change module 17 uses the signal delay time included in the signal delay characteristics of the basic circuit and the probability of occurrence of the signal delay time to generate the signal delay time of the signal path including the plurality of basic circuits and the signal delay time. A path delay calculation module 175 for calculating a signal delay characteristic of the signal path including the probability, a path determination module 176 for determining whether or not the signal delay time of the signal path satisfies an allowable condition, and a signal delay time of the signal path A path correction module 177 is provided that replaces a basic circuit included in the signal path with a circuit having a small delay variation when the allowable condition is not satisfied.

  As shown in FIG. 1, the CPU 10 further includes a logic synthesis module 18 and an arrangement module 19. The logic synthesis module 18 performs logic synthesis using a register transfer level description (RTL description) that defines the logic operation of the LSI, and creates circuit connection information of the LSI. The placement module 19 includes a cell placement module 191 and a wiring placement module 192 as shown in FIG. The cell placement module 191 arranges cells based on the circuit connection information and creates LSI layout information. The wiring placement module 192 creates the layout information of the LSI by arranging the wiring based on the circuit connection information.

  Furthermore, the design unit 1 shown in FIG. 1 includes a delay characteristic library 301, a risk level library 302, a cell library 303, and a risk wiring library 304. The delay characteristic library 301 stores a delay characteristic table of a plurality of cells. The risk library 302 stores cell and wiring failure occurrence risk. The cell library 303 stores a plurality of cells that can be used for the LSI to be designed. The dangerous wiring library 304 stores a wiring dangerous pattern.

  The design unit 1 shown in FIG. 1 includes an input device 40, an output device 50, and a storage device 200. The input device 40 includes a keyboard, a mouse, a light pen, a flexible disk device, or the like. From the input device 40, the LSI designer can specify an RTL description of the LSI and set an allowable value. Furthermore, it is possible to set the form of output data from the input device 40, and it is also possible to input an instruction to execute or stop LSI design.

  As the output device 50, a display or a printer for displaying the design result, a recording device for storing in a computer-readable recording medium, or the like can be used. Here, the “computer-readable recording medium” refers to a medium capable of recording electronic data such as an external memory device of a computer, a semiconductor memory, a magnetic disk, an optical disk, a magneto-optical disk, and a magnetic tape. means. Specifically, a “flexible disk, CD-ROM, MO disk, etc.” are included in the “computer-readable recording medium”.

  The storage device 200 includes a measurement result storage area 201, a design pattern information storage area 202, a manufacturing variation information storage area 203, a systematic variation storage area 204, a parameter storage area 205, an analysis pattern shape storage area 206, a delay characteristic storage area 207, an RTL. A description storage area 208, an allowable condition storage area 209, a circuit connection information storage area 210, a path delay storage area 211, a layout information storage area 212, and a risk storage area 213 are included.

  The measurement result storage area 201 stores the measurement result of the basic pattern shape. The design pattern information storage area 202 stores design pattern shape information related to the basic circuit. The manufacturing variation information storage area 203 stores manufacturing variation information of the basic pattern shape. The systematic variation storage area 204 stores systematic variations extracted from manufacturing variation information. The parameter storage area 205 stores variation parameters set by the parameter setting module 13. The analysis pattern shape storage area 206 stores analysis pattern shape information acquired by process simulation. The delay characteristic storage area 207 stores the signal delay characteristic of the cell. The RTL description storage area 208 stores the RTL description of the LSI to be designed. The allowable condition storage area 209 stores allowable conditions applied to the LSI. The circuit connection information storage area 210 stores circuit connection information created by logic synthesis. The circuit connection information includes connection information of a plurality of cells used for the LSI to be designed. The path delay storage area 211 stores signal delay characteristics of the signal path. The layout information storage area 212 stores LSI layout information. The layout information includes information on the arrangement of cells used in the LSI and the wiring that connects the cells. The risk storage area 213 stores the failure occurrence risk calculated by the risk calculation module 16.

  FIG. 3 shows an example of a basic pattern including the gate electrode 101, the p-type diffusion region 102, and the n-type diffusion region 103. The gate electrode 101 has a fishbone structure composed of a central stripe extending in the longitudinal direction of the p-type diffusion region 102 and the n-type diffusion region 103 and a plurality of beam portions extending horizontally on the central stripe. In the basic pattern shown in FIG. 3, the width of the beam portion of the gate electrode 101 disposed on the p-type diffusion region 102 which is the channel length is L, and is disposed between the p-type diffusion region 102 and the n-type diffusion region 103. The distance between the center stripe of the gate electrode 101 and the p-type diffusion region 102 is S.

  FIG. 4 shows an enlarged view of the gate electrode 101 in the region A of FIG. A gate electrode portion A1 shown by a solid line in FIG. 4 is an example in which the gate electrode 101 is formed under the center condition which is an optimum manufacturing condition. Here, as an example of the manufacturing condition, a condition of the light quantity V determined by the relationship with the focus value F of the exposure apparatus in the photolithography process will be described. The focus value F and the light amount V are the focus value and the light amount under the exposure conditions of a photoresist film used as an etching mask when the gate electrode 101 is formed. As shown in FIG. 5, the center condition is when the center of the focus value allowed in the photolithography process coincides with the center of the allowed light quantity V. The gate electrode portion A2 indicated by a broken line in FIG. 4 is an example in which the gate electrode 101 is formed under an over condition with the same focus value F as when the gate electrode portion A1 was formed and more light than the optimum condition. The gate electrode portion A3 indicated by the alternate long and short dash line in FIG. 4 is an example in which the gate electrode 101 is formed with the same focus value F as when the gate electrode portion A1 was formed, and under conditions where the amount of light is less than the optimum condition. As shown in FIG. 4, the gate electrode portion A2 is wider than the gate electrode portion A1, and the gate electrode portion A3 is narrower than the gate electrode portion A1. That is, the channel length L varies due to variations in manufacturing conditions within an allowable range. As a result, the characteristics of the LSI vary.

  As described above, even if the manufacturing conditions are within an allowable range, manufacturing variations that affect the characteristics and yield of the LSI occur in the shape of the pattern to be manufactured. The manufacturing variation is a systematic variation that is reproducible in manufacturing.

  The systematic variation depends on the shape of the basic pattern. For example, as shown in FIG. 6, the closer the connecting portion between the beam portion of the gate electrode 101 and the central stripe, the wider the beam portion generally due to the influence of the optical proximity effect. As a result, the smaller the value of the distance S, the greater the variation ΔL of the channel length L. FIG. 7 shows an example of systematic variation. FIG. 7 shows an example of the variation ΔL of the channel length L when the distance S shown in FIG. 6 is set from 60 nm to 100 nm. Here, the variation ΔL is the ratio of the channel length L of the manufactured transistor to the design value. Since the relationship between the distance S and the variation ΔL shown in FIG. 7 is established with good reproducibility, the variation ΔL is a systematic variation. The variation ΔL may be suppressed by designing the cell with the distance S wider than the design reference value. For example, when the design reference value of the distance S is 60 μm, the variation ΔL is reduced from 30% to 10% by designing the cell with the distance S being 80 μm.

  The extraction module 12 classifies manufacturing variations into systematic variations and random variations for each manufacturing process, and extracts information on systematic variations from information on manufacturing variations. “Random variation” is a variation component having no reproducibility among manufacturing variations. Specifically, the extraction module 12 analyzes manufacturing variation information, and extracts information on variations having reproducibility in manufacturing from the manufacturing variation information as systematic variation information. Here, the manufacturing process is a series of processes for manufacturing an LSI, such as an exposure process, an etching process, and a chemical mechanical polishing (CMP) process.

An example of a method for extracting systematic variation information from manufacturing variation information will be described below. The systematic variation is a pattern bias depending on the pattern shape, and shows a distribution having a specific tendency that does not become a Gaussian distribution like a random variation. An example of systematic variation will be described with reference to FIGS. 8 (a) and 8 (b). FIG. 8A shows a pattern composed of the gate electrodes g _{a1 to} g _a5 having the channel length L0 arranged at the gate electrode distance S1. FIG. 8B shows a pattern composed of gate electrodes g _{b1 to} g _b5 having a channel length L0 arranged at a distance S2 between the gate electrodes. Examples of forming the patterns shown in FIGS. 8A and 8B on the wafer are shown in FIGS. 9A and 9B, respectively. As shown in FIGS. 9A and 9B, the channel length of the formed gate electrode g _a3 is the channel length L1, and the channel length of the gate electrode g _b3 is the channel length L2. That is, the channel length L after the formation changes according to the distance S between the gate electrodes.

10A and 10B, the distribution of the occurrence probability P _S1 of the channel length L1 and the distribution of the occurrence probability P _S2 of the channel length L2 are shown by solid lines, respectively. 10A and 10B show the distribution of the channel length when the gate electrode g _a3 and the gate electrode g _b3 are formed as isolated single patterns without other patterns around them. Probability distribution. As shown in FIG. 10A and FIG. 10B, the smaller the distance S between the gate electrodes, the greater the difference between the distribution of the generation probability of the channel length and the distribution of the generation probability of the single pattern.

The channel length distribution is approximated by a polynomial function using the distance S between the gate electrodes as a parameter. As a method of approximating the manufacturing variation distribution such as the channel length variation distribution by a polynomial function, for example, a response phase method, an average value distribution approximation method, or the like can be adopted. Data for obtaining the polynomial function is obtained from the measurement result of the test element group (TEG) or the measurement result of a lot manufactured in the past. Here, in the distribution of manufacturing variation, a portion that can be fitted to the above polynomial function is defined as a bias due to systematic variation. Further, a portion of the manufacturing variation distribution other than the bias due to the systematic variation is defined as a random variation distribution (random distribution). That is, the random distribution is a variation distribution that does not depend on the distance S between the gate electrodes. The overall manufacturing variation is the sum of the systematic variation and the random variation. FIG. 11 shows the distribution of the occurrence probability P _S1 of the channel length L1 and the distribution of the occurrence probability P _S2 of the channel length L2, and the curve FL of the polynomial function of the channel length distribution with the distance S between the gate electrodes as a parameter. The graph is shown. In FIG. 11, the portion where the distribution of the occurrence probability P _{S1 and} the distribution of the occurrence probability P _S2 and the curve FL of the polynomial function overlap is biased due to systematic variation, and the portion not overlapping is random variation.

  In addition to the gate electrode distance S, there are a number of factors causing manufacturing variations, and the example described using the above channel length is a simple example in which the polynomial function parameter is only the gate electrode distance S. Actually, there are many parameters that affect the magnitude of variation depending on the pattern shape. By extracting the main parameters that affect the manufacturing variation from a plurality of parameters, the systematic variation information can be extracted from the manufacturing variation information by the method described above. Systematic variation may be extracted from manufacturing variation using a polynomial function including a plurality of parameters.

  An example of the extracted systematic variation information is shown in FIG. FIG. 12 is a graph showing the distribution of the occurrence probability PL of the channel length L shown in FIG. The occurrence probability PL is acquired as the occurrence probability of the channel length L when a plurality of basic patterns shown in FIG. 3 are formed.

  The parameter setting module 13 sets a variation parameter for process simulation using the systematic variation information of the basic pattern. The “variation parameter” is a parameter for a process simulator set by fitting a process simulation result to a distribution of systematic variations. The parameter setting module 13 creates a model for process simulation of the basic pattern by fitting the systematic variation extracted from the measurement result of the basic pattern with the synthesis result of each process simulation result for each manufacturing process. A variation parameter is set as a parameter of each process simulator by creating a model for process simulation fitting to systematic variation.

  FIG. 13A to FIG. 13C show examples of process simulation results for each manufacturing process. For example, FIGS. 13A to 13C show distributions of occurrence probabilities P1, P2, and P3 of the channel length L calculated by three types of process simulations of exposure simulation, focus simulation, and etching simulation, respectively. FIG. 14 shows an example in which the curve SL obtained by synthesizing the process simulation results shown in FIGS. 13A to 13C is fitted to the occurrence probability PL obtained from the measured values shown in FIG. Indicates. The black circles shown in FIG. 14 are the occurrence probabilities PL shown in FIG. In the above, an example of synthesizing three types of process simulation results has been described, but it goes without saying that the process simulation results to be synthesized are not limited to three types.

  The analysis pattern acquisition module 14 executes a process simulation to which the variation parameter is applied, and acquires the analysis pattern shape of the cell. That is, the analysis pattern shape is calculated by process simulation as a pattern shape of a cell manufactured by a manufacturing process in which systematic variations occur. Hereinafter, a case where an analysis pattern shape of a gate electrode of a transistor included in a cell is acquired as an analysis pattern shape of the cell will be described as an example.

  FIG. 15 shows a cell including transistors T1 to T7 in which only the gate electrodes g1 to g7 are illustrated. In FIG. 15, V1 is a power supply line, and V2 is a GND line. An enlarged view of region B shown in FIG. 15 is shown in FIG. A gate electrode portion B1 shown by a solid line in FIG. 16 is a process simulation result when the gate electrode g7 is formed under the center condition. A gate electrode portion B2 indicated by a broken line in FIG. 16 is a process simulation result when the gate electrode g7 is formed under an over condition. A gate electrode part B3 indicated by a one-dot chain line in FIG. 16 is a process simulation result when the gate electrode g7 is formed under an under condition.

  The analysis pattern acquisition module 14 executes the process simulation of the cell shown in FIG. 15 using the variation parameter, thereby acquiring the analysis pattern shapes of the gate electrodes g1 to g7. FIG. 17 shows the distribution of the occurrence probability PL of the channel length L7 of the gate electrode g7 calculated by the process simulation using the variation parameter.

Next, a method for acquiring the analysis pattern shape of a cell in consideration of adjacent cells will be described. FIG. 18 shows an example in which cells C1 to C5 are arranged. In the following description including the cells C1 to C5, it is assumed that all the cells are defined by a rectangular area. The target cell from which the analysis pattern shape is acquired is designated as cell C1. A cell C2 is arranged on the left side of the cell C1, a cell C3 on the right side, a cell C4 on the upper side, and a cell C5 on the lower side. As shown in FIG. 18, the distance from the cell C1 to the cell C2~C5 is the distance DIS ₁₂ ~DIS ₁₅ respectively. A systematic variation depending on the pattern shape of the circuit elements in the cells C2 to C5 occurs in the circuit elements included in the cell C1. For example, the magnitude of systematic variation occurring in the gate electrode of the transistor included in the target cell C1 varies depending on the gate electrode pitch of the transistors included in the cells C2 to C5.

The size of the systematic variation occurring in the target cell C1 by the effect of cell C2~C5 depends on the distance DIS ₁₂ ~DIS _15. Therefore, the distance DIS ₁₂ ~DIS ₁₅ by changing the running process simulation, to obtain the diffraction pattern shape of the gate electrode included in the target cell C1. That is, the analysis pattern acquisition module 14 executes a process simulation including the distances DIS _{12 to} DIS ₁₅ as parameters, and acquires the analysis pattern shape of the gate electrode included in the target cell C1. The analysis pattern acquisition module 14 acquires analysis pattern shapes for all the gate electrodes included in the target cell C1.

  The discrete probability calculation module 153 calculates the discrete probability PLd by approximating the occurrence probability PL of the channel length L7 shown in FIG. 17 with the occurrence probabilities PL1 to PL3 of the representative dimensions L71 to L73 of the channel length L7, for example. FIG. 19 shows the calculated discrete probability PLd. The representative dimension L71 is selected so as to include the channel length L7 when the gate electrode g7 is formed under the center condition. Hereinafter, the shape pattern formed under the center condition is referred to as “center shape”. The representative dimension L72 is selected so as to include the channel length L7 when the gate electrode g7 is formed under the over condition. Hereinafter, the shape pattern formed under the over condition is referred to as “over shape”. The representative dimension L73 is selected so as to include the channel length L7 when the gate electrode g7 is formed under the under condition. Hereinafter, the shape pattern formed under the under condition is referred to as “under shape”. Further, the representative dimensions L71 to L73 are selected so as to include the majority of the channel length L7 calculated by the process simulation, for example, 99.7%. The representative dimensions of the channel lengths L1 to L6 of the gate electrodes g1 to g6 are selected in the same manner. In the above, the example in which the three representative dimensions L71 to L73 are selected has been described. However, the representative dimensions may be two or more.

The delay time calculation module 151 calculates the signal delay time of the cell by circuit simulation in consideration of the shape variation of each element included in the cell. The “cell signal delay time” is the time from when the input signal is input to the cell until the output signal is output. For example, in the cell shown in FIG. 15, when the input signal is output via all the transistors T1 to T7 each having the gate electrodes g1 to g7, the representative dimensions of the gate electrodes g1 to g7 of the transistors T1 to T7. The cell signal delay time is calculated for each combination. FIG. 20 shows an example of the cell signal delay time calculated by the delay time calculation module 151. In FIG. 20, when the shape of the channel length L7 of the gate electrode g7 is an over shape and the shape of the channel lengths L1 to L6 of the gate electrodes g1 to g6 is a center shape, the signal delay time of the cell is the delay time td. Indicates. Here, the delay time td is a delay time of a signal path passing through all the transistors T1 to T7. The occurrence probability of the signal delay time is the product of the occurrence probabilities of the shapes of the transistors. That is, the generation probability Ptd shown in FIG. 20 includes the probability P _T11 to the probability P _T61 that the shape of the channel length of the transistors T1 to T6 is the center shape, and the probability P _T72 that the shape of the channel length of the transistor T7 is the over shape. Is the product of

As described above, the cell signal delay time is calculated assuming a center shape, an over shape, and an under shape for each transistor included in the cell. Therefore, if the number of transistors included in the cell of n, the signal delay time of the cell delay time calculation module 151 calculates becomes as 3 ^n. The larger the difference between the maximum value and the minimum value of the calculated signal delay time, the larger the delay variation. However, the delay variation may be a difference between the maximum value and the minimum value of the signal delay time having an occurrence probability of a certain value or more.

In the case of a cell having a plurality of input terminals, the signal delay time of the cell in the path from each input terminal to the output terminal is calculated. For example, as shown in FIG. 21, in the case of the cell C _X having the input terminals I1, I2 and the output terminal Z, the signal delay time of the cell in the path from the input terminal I1 to the output terminal Z and the output from the input terminal I2 The signal delay time of the cell in the path to the terminal Z is calculated. It is assumed that the rising time of the input signal input to the input terminals I1 and I2 of the cell C _X is ts.

A transistor having a large influence on the cell signal delay time may be selected, and the cell signal delay time may be calculated in consideration of only the shape of the selected transistor. For example, in the cell C _X shown in FIG. 21, when the shape of the output transistor that drives the output load is the center shape, the over shape, and the under shape, the shape of the transistors other than the output transistor is the center shape. The signal delay time of each cell is calculated. By selecting a transistor that takes the shape into account, the number of cell signal delay times calculated by the delay time calculation module 151 can be reduced.

Next, a method in which the table creation module 152 creates a delay characteristic table will be described. Hereinafter, a case where a delay characteristic table is created for the signal delay time tz from the input terminal I1 to the output terminal Z of the cell _CX shown in FIG. 21 will be described as an example.

As already described, the occurrence probability of the signal delay time of the cell is calculated as a product of the occurrence probabilities of the shapes of the basic patterns included in the cell. FIG. 22 shows an example of the distribution of occurrence probabilities of the signal delay time tz of the cell C _X. The occurrence probability of the signal delay time tz of the cell C _X shown in FIG. 22 is calculated based on the systematic variation of the channel length L of the transistors included in the cell C _X in the same manner as the method described with reference to FIG. The The discrete probability calculation module 153 is a discrete unit approximated by the occurrence probabilities P _{Z1 to} P _Z3 of the representative delay values t _{Z1 to} t _Z3 of the signal delay time tz based on the distribution of the occurrence probabilities of the signal delay time tz shown in FIG. Probability is calculated. FIG. 23 shows the calculated discrete probability. The representative delay values t _{Z1 to} t _Z3 are selected so as to include most of the signal delay time tz, for example, 99.7% of the signal delay time tz.

The table creation module 152 creates a signal delay characteristic D including the signal delay time of the cell C _X approximated to the discrete probability and the occurrence probability of the signal delay time. The signal delay characteristic D is expressed by the following equation (1):

D = {(TD1, P1), (TD2, P2), (TD3, P3)} (1)

In Expression (1), TD1 to TD3 are signal delay times used as representative delay values when calculating discrete probabilities, and P1 to P3 are occurrence probabilities of signal delay times TD1 to TD3.

In general, the signal delay time of the cell depends on the characteristics of the input signal input to the input terminal I1 of the cell _CX and the output load connected to the output terminal Z. For example, the signal delay time tz varies depending on the rise time ts of the input signal and the capacitance value Y of the output load. The table creation module 152 creates a delay characteristic table including a signal delay characteristic D determined for each combination of the rise time ts and the capacitance value Y. FIG. 24 shows an example of the delay characteristic table. FIG. 24 shows signal delay characteristics when the rise time ts is changed from 0.01 [ns] to 1.0 [ns] and the capacitance value Y is changed from 1 [fF] to 100 [fF]. For example, if the rise time ts is 0.1 [ns], the capacitance value Y is 50 [fF], a signal delay characteristic D _23. The signal delay characteristic D ₂₃ is expressed by the following equation (2):

D ₂₃ = {(TD1 ₂₃ , P1 ₂₃ ), (TD2 ₂₃ , P2 ₂₃ ), (TD3 ₂₃ , P3 ₂₃ )} (2)

TD1 ₂₃ , TD2 ₂₃ and TD3 ₂₃ are signal delay times used as representative delay values, and P1 ₂₃ , P2 _{23 and P323} are the occurrence probabilities of the signal delay times TD1 ₂₃ , TD2 ₂₃ and TD3 ₂₃ , respectively. When the rise time ts is 0.1 [ns] and the capacitance value Y is 50 [fF], the signal delay time m _{23 in} consideration of the occurrence probability is calculated by the equation (3):

m ₂₃ = TD1 ₂₃ × P1 ₂₃ + TD2 ₂₃ × P2 ₂₃ + TD3 ₂₃ × P3 ₂₃ (3)

FIG. 24 is a delay characteristic table showing the relationship between the rise time ts of the input signal and the capacitance value Y of the output load, and the signal delay characteristic D including the occurrence probability of the signal delay time tz and the signal delay time tz. Of course, the delay characteristic table may be created in consideration of factors that affect the occurrence probability of the signal delay time tz and the signal delay time tz other than the rise time ts and the capacitance value Y of the output load. Note that the characteristics of the input signal and the output load used for creating the delay characteristic table are incorporated in the table creation module 152, for example. Alternatively, the table creation module 152 may refer to the characteristics of the input signal and the output load stored in the storage device 200 when creating the delay characteristic table.

In the above description, an example in which the delay characteristic table is created in consideration of the systematic variation of the channel length L has been shown. The delay characteristic table may be created in consideration of systematic variations of basic patterns other than the channel length L. For example, the delay characteristic table may be created in consideration of the variation ΔW in the gate width W of the transistor. FIG. 25 shows the distribution of the occurrence probability PW of the gate width W of the gate electrode g7 shown in FIG. 15 calculated by the process simulation. FIG. 26 shows an example of the discrete probability PWd obtained by approximating the occurrence probability PW shown in FIG. 25 with the occurrence probabilities P _{W1 to} P _W3 of the representative dimensions W1 to W3 of the gate width. The representative dimensions W1 to W3 are selected so as to include most of the distribution of the gate width W, for example, 99.7%, similarly to the representative dimensions L71 to L73.

  As already described, the delay time calculation module 151 calculates the signal delay time for all combinations of the representative dimensions of the gate electrodes g1 to g7 of the transistors T1 to T7 for the cell shown in FIG. When considering the variation ΔL of the channel length L and the variation ΔW of the gate width W, the signal delay time is calculated for all combinations of the representative dimensions of the channel length L and the gate width W.

FIG. 27 shows an example of the signal delay time of the cell shown in FIG. 15 calculated by the delay time calculation module 151. FIG. 27 shows a case where the channel length and gate width of the gate electrode g7 are over-shaped, the channel length of the gate electrodes g1 to g6 is over-shaped, and the gate width of the gate electrodes g1 to g6 is center-shaped. It shows that the signal delay time in the cell is the delay time te. The occurrence probability of the signal delay time shown in FIG. 27 is a product of the occurrence probabilities of the shapes of the transistors. That is, the probability Pte of occurrence shown in FIG. 27 is the probability P _T121 that the shape of the channel length of the transistor T1 is the over shape and the shape of the gate width is the center shape, and the shape of the channel length of the transistor T2 is the over shape and the gate width. The probability P _T221 that the shape is the center shape, the probability P _T321 that the channel length shape of the transistor T3 is the over shape and the gate width shape is the center shape, and the channel length shape of the transistor T4 is the over shape and the gate width shape. probability P _T421 is center shape, the probability P _T521, the shape of the shape of the channel length over the shape and the gate width of the transistor T6 is center shape is the center shape shape of the shape of the channel length over the shape and the gate width of the transistor T5 channel length and gate of the probability P _T621, and the transistor T7 is Shape-wide is the product of the probability P _T722 an over shape together.

When the number of transistors included in the cell is n, the signal delay time calculated by the delay time calculation module 151 is ³²ⁿ . As described above, the number of signal delay times calculated by the delay time calculation module 151 can be reduced by selecting only the transistors having a large influence on the signal delay time in the cell and calculating the signal delay time. The delay characteristic table calculated by the method described above is stored in the delay characteristic library 301.

  Hereinafter, a method in which the risk level calculation module 16 calculates the failure level risk level at which a failure due to systematic variation occurs in the LSI will be described.

  The cell risk calculation module 161 compares the design pattern shape of the target cell with the analysis pattern shape of the target cell obtained by the process simulation using the variation parameter, and a defect due to systematic variation occurs in the target cell. Calculate the risk of failure occurrence. For example, the defect occurrence risk of the basic pattern included in the target cell is calculated as the ratio of the channel length calculated by the process simulation applying the variation parameter to the design value of the channel length of the transistor. The failure occurrence risk level of the target cell is calculated as the sum of the failure occurrence risk levels of the basic patterns included in the target cell.

The cell risk level calculation module 161 calculates the defect occurrence risk level Def _CELL of the target cell using the following equation (4):

Def _CELL = DefC + ΣDefP + ΣDefG ... (4)

In Expression (4), “DefC” is the risk of occurrence of a defect in the target cell when arranged alone. “DefP” is a defect occurrence risk of the target cell calculated by executing a process simulation in which the distance between the target cell and the adjacent cell is changed as described with reference to FIG. The term “ΣDefP” in Equation (4) represents the sum of the failure occurrence risk DefP calculated for all combinations of the target cell and the adjacent cells adjacent to the target cell. “DefG” is a defect occurrence risk for each wiring grid when a process simulation is executed on the assumption that wirings or vias are arranged in each wiring grid in the target cell. FIG. 28 shows an example in which wiring is arranged on a wiring grid that can be wired in a cell. In FIG. 28, the wirings H1 to H16 arranged on the wiring grid in the cell are hatched. By executing a process simulation in which the wiring parameters are arranged in the wirings H1 to H16 and the variation parameter is applied, the defect occurrence risk DefG is calculated for each wiring grid that can be wired in the cell. The term “ΣDefG” in Equation (4) represents the sum of the failure occurrence risk DefG of all the wiring grids in the target cell. The cell defect occurrence risk Def _CELL calculated by Expression (4) is stored in the risk library 302 for each cell.

The failure occurrence risk of the wiring that electrically connects the cells is also calculated in the same manner as the failure occurrence risk Def _{CELL of the} cell. That is, the manufacturing variation information about the wiring and via is obtained from the measurement result of the basic pattern of the wiring and via. The basic pattern of wiring and via will be described later. A process simulation result is fitted to systematic variations extracted from manufacturing variation information, and variation parameters for process simulation of wiring and vias are set. A process simulation using the set variation parameter is executed, and the analysis pattern shapes of the wiring and via are calculated. The wiring risk calculation module 162 compares the shape of the wiring and via design pattern with the analysis pattern shape obtained by executing the process simulation, and determines the wiring failure as the degree of deviation of the analysis pattern shape from the design pattern shape. Calculate the occurrence risk. That is, the wiring defect occurrence risk is a risk that a defect due to systematic variation occurs in the wiring. Here, the defect generated in the wiring includes, for example, a variation from the design pattern of the manufactured wiring shape accompanied by a variation in wiring resistance and wiring capacity so as to affect the performance and yield of the LSI.

FIGS. 29A to 29D show examples of basic patterns of wiring patterns including a plurality of wirings. In FIG. 29A to FIG. 29D, the target wiring to be measured is hatched. As shown in FIGS. 29 (a) to 29 (d), a basic pattern is created in which the distance between adjacent wirings, the number of wirings continuously arranged, and the like are changed, and manufacturing variation information of the target wirings Is acquired. The wiring pitch and wiring width of the basic pattern depend on the design rule applied to the LSI to be designed.
30A to 30D show examples of basic patterns of wiring patterns including a plurality of vias. 30A to 30D, vias are shown as squares, wiring grids on which vias can be arranged are shown as intersections of broken lines, and target vias to be measured are shown as black squares. As shown in FIGS. 30A to 30D, a basic pattern in which the position and number of vias arranged adjacent to each other is changed is created, and manufacturing variation information of the target via is acquired. The wiring grid in which vias can be arranged depends on the design rule applied to the LSI to be designed.

The wiring risk level calculation module 162 calculates the wiring failure occurrence risk level Def _WIRE in an arbitrary wiring layer using the equation (5):

Def _WIRE = ΣDefW + ΣDefV (5)

The term “ΣDefW” in Equation (5) represents the sum of the failure occurrence risk DefW calculated for all the wirings arranged in the same wiring layer. The term “ΣDefV” represents the sum of the failure occurrence risk DefV calculated for all the vias arranged in the same wiring layer.

As illustrated in FIG. 29A to FIG. 29D and FIG. 30A to FIG. 30D, wiring defect occurrence risk DefW for each wiring pattern in which wirings and vias are arranged in combination. DefV is calculated. The wiring defect occurrence risk Def _WIRE calculated by Expression (5) is stored in the risk library 302 for each wiring pattern. Also, a pattern including a wiring having a defect occurrence risk level DefW or DefV of a certain value (for example, 0.001%) or more is stored in the dangerous wiring library 304 as a “dangerous wiring pattern”.

Note that wiring delay information including the wiring resistance and wiring capacitance of the target wiring is stored in the delay characteristic library 301 for each wiring pattern. The wiring delay information of the target wiring is affected by the wiring arranged in the vicinity. For this reason, for example, an RC correction coefficient considering adjacent wiring is set as wiring delay information. The “RC correction coefficient” is a coefficient used for correcting the influence of the adjacent wiring when calculating the wiring resistance and wiring capacitance of the wiring. Hereinafter, an example in which the RC correction coefficient is set will be described with reference to the wiring patterns shown in FIGS. 31 (a) and 31 (b). In FIGS. 31A and 31B, the wiring tracks WT _{1 to} WT ₇ are indicated by broken lines, and the wiring is hatched. Wiring pattern shown in FIG. 31 (a) the target wiring is arranged to set the RC correction coefficient on the wiring track WT ₄ of wiring tracks WT ₁ ~WT _7, adjacent to the wiring tracks WT _1, WT ₃ and WT ₆ This is an example in which wiring is arranged. The wiring pattern shown in FIG. 31B is an example in which the wiring of interest is arranged only in the wiring track WT ₄ among the wiring tracks WT _{1 to} WT ₇ . Here, let us consider wiring pattern information created by assigning “1” to a wiring track in which wiring is arranged, and “0” to a wiring track in which no wiring is arranged. The wiring pattern information in FIG. 31A is “101010”, and the wiring pattern information in FIG. 31B is “0001000”. An RC correction coefficient is calculated for every possible wiring pattern information, and a correction coefficient table is created in advance. The RC correction coefficient stored in the correction coefficient table is calculated by simulation using the analysis pattern shape for each wiring pattern. As a result, it is possible to set an RC correction coefficient in consideration of systematic variation for the wiring included in the LSI.

  FIG. 32 shows an example of the RC correction coefficient of the wiring pattern shown in FIG. As shown in FIG. 32, the RC correction coefficient of the wiring pattern information “10101010” is 0.99780, and the RC correction coefficient of the wiring pattern information “0001000” is 1.00000. When setting the RC correction coefficient in consideration of the length of the adjacent wiring portion, use wiring pattern information in which the wiring grid through which the wiring passes is “1” and the wiring grid through which the wiring does not pass is “0”. Thus, the RC correction coefficient of the wiring pattern can be set in the same manner as described above.

The layout risk level calculation module 163 extracts the failure occurrence risk level of cells, wirings and vias included in the LSI layout from the risk level library 302, and calculates the failure occurrence risk level Def _all of the entire layout. The defect occurrence risk level Def _all is calculated by using the following equation (6) as the sum of the cell defect occurrence risk level Def _CELL and the wiring defect occurrence risk level Def _WIRE :

Def _all = Def _CELL + Def _WIRE
= Def _CELL + ΣDefW + ΣDefV (6)

The layout determination module 171 determines whether or not the layout failure probability Def _all of the LSI to be designed satisfies an allowable condition. Specifically, the layout determination module 171 compares the layout defect occurrence risk Def _all calculated using Expression (6) with a predetermined layout allowable value. The layout allowable value is set so that the LSI performance, yield, and the like due to variations from the shape of the design pattern such as transistors are within the allowable range. The layout allowable value may be set for the failure occurrence risk level Def _all , or may be set for the cell failure occurrence risk level Def _CELL or the wiring failure occurrence risk level Def _WIRE . Further, the defect occurrence risk level may be set for each of DefC, DefP, DefG, DefW and DefV.

The layout determination module 171 determines that the failure occurrence risk satisfies the allowable condition when the absolute value of the failure occurrence risk Def _all is equal to or less than the layout allowable value. When the absolute value of the defect occurrence risk Def _all is larger than the layout allowable value, it is necessary to change the layout in order to achieve the desired performance and yield of the LSI. For example, when the layout allowable value is set to 25%, if the sum of the failure occurrence risk of cells, wirings and vias is greater than 25%, the LSI layout is changed, and the layout failure occurrence risk Def _all is A new layout that satisfies a predetermined layout tolerance is created.

The layout of the LSI is changed, for example, by replacing a cell having a high failure occurrence risk Def _CELL included in the layout before the change with a cell having a low failure occurrence risk Def _CELL . That is, the replacement module 172 extracts a cell having a high failure occurrence risk Def _CELL included in the layout information before the change, and a cell having a low failure occurrence risk Def _CELL having the same function as the extracted cell (in the following, Replaced with “yield priority cell”). The method for extracting cells having a high defect occurrence risk Def _CELL is, for example, a method for extracting a cell having the highest defect occurrence risk Def _CELL among the cells included in the layout, or a certain value (for example, 0.001%) or more. For example, a method of extracting a cell having a defect occurrence risk Def _CELL may be employed. Note that the yield priority cells of the cells used in the LSI to be designed are stored in the cell library 303.

  The “yield priority cell” is a cell designed with priority on yield improvement, and is designed with a design rule looser than the design reference value, for example. Specifically, when the design reference value of the distance S shown in FIG. 2 is 60 μm, the yield priority cell is designed by setting the distance S to 80 μm. As shown in FIG. 6, when the cell is designed with the distance S being 80 μm, the cell area is larger than when the distance S is 60 μm, but the variation ΔL is reduced from 30% to 10%. .

As an example of the yield priority cell, the yield priority cell of the cell C _X1 shown in FIG. 33 is shown in FIGS. A cell C _X1 illustrated in FIG. 33 includes the logic circuit X10, the logic circuit Y10, and the logic circuit Z10. As shown in FIG. 33, the logic circuit X10 includes a gate electrode X101, a p-type diffusion region X102, and an n-type diffusion region X103. Hereinafter, the distance between the center stripe of the gate electrode and the p-type diffusion region is referred to as “p distance”, and the distance between the center stripe of the gate electrode and the n-type diffusion region is referred to as “n distance”. The p distance and the n distance of the logic circuit X10 are S _X1 . The logic circuit Y10 includes a gate electrode Y101 and a p-type diffusion region Y102. The p distance of the logic circuit Y10 is S _Y1 . The logic circuit Z10 includes a gate electrode Z101 and an n-type diffusion region Z103. The n distance of the logic circuit Z10 is S _Z1 . Diffusion region distance between the p-type diffusion region Y102 of p-type diffusion region X102 and logic circuit Y10 of the logic circuit X10 is S _p1. The distance between the gate electrodes of the center stripe of the gate electrode Y101 of the logic circuit Y10 and the center stripe of the gate electrode Z101 of the logic circuit Z10 is S _g1 .

The cell C _X2 shown in FIG. 34 is a yield priority cell of the cell C _{X1 in which} the logic circuit X10 is replaced with the logic circuit X11 having the p distance and the n distance S _X2 (S _X1 <S _X2 ). In the logic circuit X11, the p distance and the n distance are increased by narrowing the width in the direction in which the beam portion of the gate electrode X101 of the p-type diffusion region X102 and the n-type diffusion region X103 extends. That is, the gate width of the logic circuit X11 is smaller than the gate width of the logic circuit X10. Therefore, the number of beam portions of the gate electrode X101 of the logic circuit X11 is increased from that of the logic circuit X10, and the transistor characteristics such as the gate capacity and the load driving force are made the same in the logic circuit X11 and the logic circuit X10. As a result, the cell area of the cell C _X2 is larger than that of the cell C _X1 , but since S _X1 <S _X2 , the defect occurrence risk Def _CELL of the cell C _X2 is smaller than that of the cell C _X1 .

The cell C _X3 shown in FIG. 35 is a yield priority cell of the cell C _{X1 in which} the logic circuit Y10 is replaced with a logic circuit Y11 with a p distance of S _Y2 and the logic circuit Z10 is replaced with a logic circuit Z11 with an n distance of S _Z2. (S _Y1 <S _Y2 and S _Z1 <S _Z2 ). In the logic circuit Y11, the p distance is increased by narrowing the width in the direction in which the beam portion of the gate electrode Y101 of the p-type diffusion region Y102 extends. In the logic circuit Z11, the n distance is increased by narrowing the width in the direction in which the beam portion of the gate electrode Z101 of the n-type diffusion region Z103 extends. Therefore, the number of beam portions of the gate electrode Y101 of the logic circuit Y11 is increased from that of the logic circuit Y10. Further, the number of beam portions of the gate electrode Z101 of the logic circuit Z11 is increased from that of the logic circuit Z10. As shown in FIG. 35, the distance between the gate electrodes of the cell C _X3 is S _g2 (S _g1 <S _g2 ). As a result, a large cell area of the cell C _X3 is compared to cell C _X1, failure risk of the cell C _X1 as compared to the cell C _X1 Def _CELL is small.

In the cell C _X4 shown in FIG. 36, the logic circuit X10 shown in FIG. 33 is replaced with the logic circuit X11 shown in FIG. 34, and the logic circuit Y10 and the logic circuit Z10 are replaced with the logic circuit Y11 and the logic circuit Z11 shown in FIG. _Are the yield priority cells of the cell C _X1 , respectively. The cell area of the cell C _X4 is larger than that of the cell C _X1 , but the defect occurrence risk Def _CELL of the cell C _X3 is also small compared to the cells C _X2 and C _X3 .

The cell C _X5 shown in FIG. 37 is a yield priority cell of the cell C _{X1 where} the distance between the diffusion regions of the cell C _X4 shown in FIG. 36 is S _p2 (S _p1 <S _p2 ). Although larger cell area of the cell C _X5 is compared to cell C _X4, failure risk of the cell C _X5 compared to cell C _X4 Def _CELL is small.

The cell C _X6 shown in FIG. 38 is a yield priority cell of the cell C _{X1 in} which dummy patterns DM1 and DM2 are added to the cell C _X1 . The dummy patterns DM1 and DM2 are arranged in parallel with the direction in which the beam portions of the gate electrodes X101, Y101, and Z101 extend. As shown in FIG. 38, the dummy pattern DM1 is arranged between the left side of the cell C _X6 and the logic circuit X10. The dummy pattern DM2 is disposed between the right side of the cell C _X6 and Y10 and Z10. By disposing the dummy patterns DM1 and DM2, it is possible to suppress manufacturing variations due to pitch variations of the beam portions of the gate electrode depending on the layout of the cells arranged adjacent to the left and right of the cell C _X6 . Although larger cell area of the cell C _X6 is compared to cell C _X1, failure risk of the cell C _X5 compared to cell C _X1 Def _CELL is small.

The cell C _X7 to cell C _X10 shown in FIGS. 39, 40, 41, and 42 are provided with dummy patterns DM1 and DM2 in the cells C _X2 to C _X5 shown in FIGS. 34, 35, 36, and 37, respectively. This is an added example. Similar to the cell C _X6, the manufacturing variation of the pitch variation caused cell C _X6 ~ cell C _X10 in the gate electrode can be suppressed. 38 to 42 show an example in which the dummy patterns DM1 and DM2 are arranged at the left and right ends of the cell region, but the dummy patterns may be arranged only at the left end or only at the right end.

The yield priority cells C _X2 to C _X10 of the cell C _X1 described above are stored in the cell library 303. Yield priority cell C _X2 to cell C _X10 are used as cells to replace cell C _X1 when the LSI layout is changed.

Furthermore, the change module 17 changes the layout in order to suppress an increase in the defect occurrence risk Def _CELL due to systematic variations depending on the pattern shape of the adjacent cells. Specifically, the dangerous placement detection module 173 detects the dangerous cell placement included in the layout information. Here, the “dangerous cell arrangement” is a cell arrangement that increases the degree of failure occurrence Def _CELL caused by systematic variations depending on the pattern shape of the adjacent cells. The dangerous placement detection module 173 extracts from the layout information a cell having a defect occurrence risk level DefP of a certain value or higher, for example, 0.001% or higher, and its neighboring cells. Then, the arrangement correction module 174 corrects the cell arrangement including the detected cells as described below to reduce the failure occurrence risk Def _CELL .

FIG. 43 shows a cell arrangement including cells C ₁₀ and C ₂₀ arranged adjacent to each other. Cell C ₁₀ has a gate electrode g ₁₁ to g _17, p-type diffusion region PD ₁₀ and the n-type diffusion region ND _10. Cell C ₂₀ has a gate electrode g ₂₁ to g _27, p-type diffusion region PD ₃₀ and the n-type diffusion region ND _20. Here, the gate electrode g ₁₇ of cell C ₁₀ arranged closest to the cell C _20, a distance D _g1 of the gate electrode distance between the gate electrode g ₂₁ of cell C ₂₀ arranged closest to the cell C ₁₀ To do. Since the distance D _g1 is small, systematic variations may occur in the gate electrode g ₁₀ and the gate electrode g ₂₀ due to the influence of the pattern shapes of the cells C ₁₀ and C ₂₀ . Alternatively, since the distance D _g1 is large, the pitch at which the gate electrodes are arranged becomes uneven, and systematic variations may occur in the gate electrode g ₁₀ and the gate electrode g ₂₀ . Here, the distance between the gate electrodes where the systematic variation that affects the performance and yield of the LSI does not occur is referred to as “optimum gate electrode distance”. When the distance D _g1 is not the optimum gate electrode distance, the cell arrangement needs to be corrected. Examples of correcting the cell arrangement shown in FIG. 43 are shown in FIGS.

Figure 44 extends the distance between the cell C ₁₀ and the cell C _20, an example of spread gate electrode distance of the gate electrode g ₁₀ and the gate electrode g ₂₀ a distance D _g2. If there is a possibility that systematic variation in the distance D _g1 shown is smaller than the optimum gate electrode distance is generated in the gate electrode g ₁₀ and the gate electrode g ₂₀ in Figure 43, by increasing the distance D _g2, cell C ₁₀ In addition, the defect occurrence risk Def _CELL of the cell C ₂₀ decreases.

Figure 45 is a rotation about the central position of the cell C _10, a cell C ₁₀ is an example of rotated 180 degrees. By arranging rotating the cell C _10, the gates of the gate electrode g ₂₁ of the gate electrode g ₁₇ and the cell C cell C ₂₀ arranged closest to ₁₀ of the cell C ₁₀ arranged closest to the cell C ₂₀ The inter-electrode distance _{Dg3 is set} to the optimum inter-gate electrode distance. As a result, the defect occurrence risk Def _CELL of the cells C ₁₀ and C ₂₀ decreases.

Figure 46 is an example in which the cell C ₃₀ between cells C ₁₀ and the cell C _20. Cell C ₃₀ has a gate electrode g ₃₁ to g _34, p-type diffusion region PD ₃₀ and the n-type diffusion region ND _30. Gate electrode distance between the gate electrode g ₃₄ of the gate electrode g ₂₁ and the cell C ₃₀ in the gate electrode distance D _g4, and cell C ₂₀ in the gate electrode g ₃₁ of the gate electrode g ₁₇ and the cell C ₃₀ of the cell C ₁₀ Cell _C30 is selected such that _Dg54 is the optimum distance between the gate electrodes. As a result, the defect occurrence risk Def _CELL of the cells C ₁₀ and C ₂₀ decreases.

Figure 47 is an example of replacing the cell C ₁₀ in cell C ₁₀₁ to the dummy gate electrode is added to the cell C _10. The cell C ₁₀₁ is a cell in which a dummy gate electrode g _D is added between the gate electrode g ₁₇ and the cell end of the cell C ₁₀ . By optimizing the gate electrode distance the gate electrode distance D _g6 the gate electrode g ₂₁ of the dummy gate electrode g _D and the cell C _20, failure risk Def _CELL cells C ₁₀ and cell C ₂₀ is reduced .

In the above, an example has been described in which the defect occurrence risk level Def _CELL is reduced by performing cell replacement and cell arrangement correction in order to reduce the defect occurrence risk level Def _all . The failure occurrence risk level Def _all may be reduced by reducing the failure occurrence risk level Def _WIRE by correcting the wiring pattern. Specifically, the dangerous placement detection module 173 refers to the dangerous wiring pattern stored in the dangerous wiring library 304 and detects the dangerous wiring pattern included in the LSI layout information. As already described, the dangerous wiring pattern is a wiring pattern having a large degree of deviation from the shape of the design pattern and increasing the degree of failure occurrence Def _WIRE due to systematic variation depending on the wiring pattern. Then, the placement correction module 174 corrects the detected dangerous wiring pattern as described below to reduce the failure occurrence risk Def _WIRE .

FIG. 48 shows a wiring pattern composed of the wiring LA and the wiring LB arranged adjacent to each other. The distance between wirings in the closest part between the wiring LA and the wiring LB is _defined as a distance D _W1 . A via VA is disposed in a portion of the wiring LA closest to the wiring LB. The wiring LB is disposed on the wiring track WT _B1 . Since the distance D _W1 is small, systematic variations may occur in the wiring LA and the wiring LB. Alternatively, since the distance D _W1 is large, the wiring pitch becomes uneven, and systematic variations may occur in the wiring LA and the wiring LB. Here, the inter-wiring distance at which systematic variations that affect the performance and yield of the LSI do not occur is referred to as “optimum inter-wiring distance”. That is, when the inter-wiring distance is not the optimal inter-wiring distance, the wiring pattern composed of the wiring LA and the wiring LB is a dangerous wiring pattern. When the distance D _W1 is not the optimum inter-wiring distance, it is necessary to correct the wiring arrangement. An example of correcting the wiring arrangement shown in FIG. 48 will be described with reference to FIGS. 49 to 51.

FIG. 49 shows an example in which systematic variations occur in the wiring LA and the wiring LB because the distance D _W1 is smaller than the optimal inter-wiring distance. As shown in FIG. 49, the shapes of the wiring LA and the wiring LB are deformed in the portion closest to the wiring LA and the wiring LB. FIG. 50 shows an example in which the wiring pattern including the wiring LA and the wiring LB is corrected by the related technology. In the related art, for example, when the distance between the wirings LA and LB is equal to or less than a certain value, the distance between the wirings is increased by a half pitch. Figure 50 shows an example in which the wiring distance between the wiring LA wire LB is expanded the distance D _W2, in the middle of the wiring track WT _B2 of the wiring tracks WT _B1 adjacent wiring tracks WT _B1, wire LB are disposed Indicates.

However, when the optimal distance between the wiring LA and the wiring LB is larger than the distance D _W2 , the correction of the wiring pattern by the related technique shown in FIG. 50 prevents the occurrence of systematic variations that affect the LSI characteristics and the like. Can not. FIG. 51 shows an example in which the inter-wiring distance between the wiring LA and the wiring LB is increased to a distance D _W3 that is _equal to or _larger than the optimal inter-wiring distance. The dangerous wiring pattern shown in FIG. 48 detected by the dangerous placement detection module 173 is corrected to the wiring pattern shown in FIG. 51 by the placement correction module 174, so that the risk of failure occurrence Def _WIRE can be reduced.

Next, a method of designing a signal path that suppresses signal delay and yield reduction due to systematic variation using the cell signal delay characteristic and the failure occurrence risk Def _CELL will be described. First, an example of a method for calculating the signal delay time (hereinafter referred to as “path delay time”) of the signal path included in the LSI and the occurrence probability of the path delay time using the signal delay characteristics of each cell will be described below. . As an example of the signal path, a signal path K passing through the cells Ca, Cb, and Cc is shown in FIG. The path delay calculation module 175 calculates the path delay time of the signal path K with reference to the delay characteristic tables of the cells Ca, Cb, and Cc. Here, the path delay time of the signal path K is the time until the signal input to the cell Ca is output from the cell Cc. The path delay time of the signal path K is calculated for all combinations of the representative dimensions of the circuit elements included in the cells Ca, Cb, and Cc.

  FIG. 53 shows an example of the path delay time of the signal path K calculated by the path delay calculation module 175. FIG. 53 shows that the path delay time of the signal path K is the signal delay time tk when the circuit element included in the cell Ca has an over shape and the circuit elements included in the cells Cb and Cc each have a center shape. Show. The occurrence probability Ptk of the signal delay time tk shown in FIG. 53 is a product of the occurrence probabilities of the circuit element shapes included in the cells Ca, Cb, and Cc, respectively. That is, the occurrence probability Ptk illustrated in FIG. 53 is included in the probability that the shape of the circuit element included in the cell Ca is an over shape, the probability that the shape of the circuit element included in the cell Cb is a center shape, and the cell Cc. This is the product of the probability that the shape of the circuit element pattern is the center shape.

For each cell, a signal delay characteristic including a path delay time and its occurrence probability is calculated assuming a center shape, an over shape, or an under shape for the circuit element. Therefore, in the case of a signal path including n cells, 3 ⁿ signal delay characteristics are calculated.

  The path determination module 176 determines whether the signal delay characteristic of each signal path included in the LSI satisfies an allowable condition. The permissible condition is set for each signal path so that the LSI performance or yield does not deteriorate due to signal delay in the signal path. For example, the signal delay characteristic satisfies the allowable condition when the sum of the occurrence probabilities of the path delay time satisfying a predetermined delay allowable value is 97% or more among all the path delay times included in the signal delay characteristic of the signal path. Determined to be satisfied. As the allowable delay value, either an upper limit or a lower limit, or both an upper limit and a lower limit are set. For example, the upper limit of the allowable delay value is set for the critical path of the LSI, and the path determination module 176 determines the path of the critical path when the path delay time of the critical path calculated by the path delay calculation module 175 is larger than the allowable delay value. It is determined that the delay time does not satisfy the allowable condition.

  If the path delay time does not satisfy the acceptable condition, the signal path is modified. Specifically, the path correction module 177 extracts a cell having a large delay variation from the signal path from the signal path, and extracts a cell having the same function as the extracted cell and having a smaller delay variation than the extracted cell. Replace the cell. The cell used for changing the signal path is selected from the cell library 303.

  For example, it is assumed that the signal path K shown in FIG. 52 is a critical path, and the path delay time of the signal path K is larger than a preset delay allowable value. The path correction module 177 refers to the delay characteristic table of the cells Ca, Cb, and Cc and extracts a cell having a large delay variation from the cells Ca, Cb, and Cc. As a method for extracting a cell having a large delay variation, there are a method for extracting a cell having a delay variation of a certain value or more, a method for extracting a cell having the largest delay variation among cells included in a signal path, and the like. When the cell Cb is extracted as a cell having a large delay variation, the path correction module 177 replaces the cell Cb with a cell Cd having a small delay variation and the same function as the cell Cb. FIG. 54 shows a signal path obtained by replacing the cell Cb included in the signal path K shown in FIG. 52 with the cell Cd. Replacing the cell Cb with the cell Cd reduces the variation in the path delay time of the entire signal path K, and increases the probability that the path delay time of the signal path K considering the systematic variation satisfies the delay tolerance.

  As long as the path delay time of the signal path K satisfies the allowable delay value, a cell having a small delay variation may be replaced with a cell having a large delay variation. For example, the cell Cb is replaced with a cell Ce having a delay variation larger than that of the cell Cb but a cell area smaller than that of the cell Cb and having the same function as the cell Cb. FIG. 55 shows a signal path obtained by replacing the cell Cb included in the signal path K shown in FIG. 52 with the cell Ce. By replacing the cell Cb with the cell Ce, the degree of integration of the LSI is improved.

Further, the path determination module 176 determines whether or not the failure occurrence risk of each signal path satisfies the allowable condition using the failure occurrence risk Def _CELL . Specifically, the path determination module 176 determines a signal path that includes a cell having a defect occurrence risk Def _CELL equal to or higher than a predetermined allowable value (for example, 0.001%) as a signal path that does not satisfy the allowable condition. Judge. The path correction module 177 replaces a cell having a failure occurrence risk Def _{CELL that} is equal to or higher than a predetermined allowable value with a cell that is equal to or lower than the allowable value, thereby correcting the signal path.

An example of a method for designing an LSI using the design system shown in FIG. 1 will be described below with reference to the flowcharts shown in FIGS. First, a method for calculating the signal delay characteristic, the failure occurrence risk level Def _CELL, and the failure occurrence risk level Def _WIRE will be described with reference to the flowchart shown in FIG.

  (A) In step S10, a basic pattern is formed on the wafer in a series of manufacturing processes used for LSI manufacturing using manufacturing equipment and manufacturing conditions used for manufacturing the LSI to be designed. The basic pattern is formed by a plurality of process conditions to which a center condition, an over condition, an under condition or the like is applied in each manufacturing process. The measuring unit 2 shown in FIG. 1 measures the shape of the basic pattern for each manufacturing process. The measurement result is stored in the measurement result storage area 201 via the input device 40. In addition, design pattern shape information related to basic circuits such as cells and wiring patterns is stored in the design pattern information storage area 202 via the input device 40.

  (B) In step S20, the information acquisition module 11 reads the measurement result of the shape of the basic pattern from the measurement result storage area 201. The information acquisition module 11 acquires basic pattern manufacturing variation information for each manufacturing process from the measurement result of the basic pattern shape. The acquired manufacturing variation information is stored in the manufacturing variation information storage area 203.

  (C) In step S <b> 30, the extraction module 12 reads out manufacturing variation information on the shape of the basic pattern from the manufacturing variation information storage area 203. The extraction module 12 extracts systematic variation from the manufacturing variation information. The extracted systematic variation is stored in the systematic variation storage area 204.

  (D) In step S40, the parameter setting module 13 reads the systematic variation from the systematic variation storage area 204. The parameter setting module 13 sets a variation parameter by fitting a process simulation result to systematic variation. The set variation parameter is stored in the parameter storage area 205.

  (E) In step S50, the analysis pattern acquisition module 14 reads the variation parameter from the parameter storage area 205. The analysis pattern acquisition module 14 executes a process simulation to which variation parameters are applied, and acquires analysis pattern shapes of cells and wiring patterns that may be used in the LSI to be designed. The acquired analysis pattern shape information is stored in the analysis pattern shape storage area 206.

  (F) In step S60, the delay time calculation module 151 reads the analysis pattern shape from the analysis pattern shape storage area 206. The delay time calculation module 151 calculates the signal delay time of the cell and the occurrence probability of the signal delay time using the analysis pattern shape. The signal delay characteristics including the cell signal delay time and the occurrence probability of the signal delay time are stored in the delay characteristic storage area 207.

  (G) In step S70, the table creation module 152 reads the signal delay characteristics of the cell from the delay characteristics storage area 207. The table creation module 152 creates a delay characteristic table showing the relationship between the characteristics of the input signal and the output load and the signal delay characteristic of the cell for each cell using the equation (1). The created delay characteristic table is stored in the delay characteristic library 301.

(H) In step S80, the risk level calculation module 16 reads the design pattern shape information and analysis pattern shape information of the cell and the wiring pattern from the design pattern information storage area 202 and the analysis pattern shape storage area 206, respectively. The risk level calculation module 16 compares the shape of the design pattern with the analysis pattern shape, and calculates the cell failure occurrence risk level Def _CELL and the wiring pattern failure occurrence risk levels DefW and DefV. The calculated failure occurrence risk levels Def _CELL , DefW and DefV are stored in the risk level library 302 for each cell or wiring pattern. Further, a dangerous wiring pattern including a wiring having a defect occurrence risk DefW or DefV of a certain value or more is stored in the dangerous wiring library 304.

Next, an example of a method of designing an LSI using the signal delay characteristic, the failure occurrence risk level Def _CELL, and the failure occurrence risk level Def _WIRE will be described with reference to the flowchart shown in FIG.

  (A) In step S110, the RTL description of the LSI to be designed is stored in the RTL description storage area 208 via the input device 40 shown in FIG. In addition, allowable conditions such as a delay allowable value and a layout allowable value applied to the LSI are stored in the allowable condition storage area 209. The allowable conditions may be stored in the allowable condition storage area 209 in advance.

  (B) In step S120, the logic synthesis module 18 reads the RTL description from the RTL description storage area 208. The logic synthesis module 18 performs logic synthesis based on the RTL description and creates LSI circuit connection information. The created circuit connection information is stored in the circuit connection information storage area 210.

  (C) In step S130, the path delay calculation module 175 reads the circuit connection information and the delay characteristic table from the circuit connection information storage area 210 and the delay characteristic library 301, respectively. The path delay calculation module 175 refers to the signal delay characteristics of each cell stored in the delay characteristics table, and uses the method described with reference to FIG. 52 to determine the path delay time of each signal path included in the circuit connection information. And a signal delay characteristic including the occurrence probability of the path delay time. The calculated signal delay characteristic of the signal path is stored in the path delay storage area 211. Next, the path determination module 176 reads the signal delay characteristic and the allowable delay value of the signal path from the path delay storage area 211 and the allowable condition storage area 209, respectively. The path determination module 176 determines whether or not the signal delay characteristic satisfies an allowable condition for each signal path. If the signal delay characteristic satisfies the allowable condition, the process proceeds to step S150. If the signal delay characteristic does not satisfy the allowable condition, the process proceeds to step S140.

  (D) In step S140, the path correction module 177 reads the circuit connection information and the delay characteristic table of the signal path whose signal delay characteristics do not satisfy the allowable condition from the circuit connection information storage area 210 and the delay characteristic library 301, respectively. The path correction module 177 refers to the signal delay characteristic of each cell stored in the delay characteristic table, extracts a cell having a large delay variation from the signal path whose signal delay characteristic does not satisfy the allowable condition, and delays the extracted cell. Replace with a cell with small variation. New circuit connection information whose signal path has been changed is stored in the circuit connection information storage area 210. After correcting the signal path, the process returns to step S130.

  (E) In step S150, the cell placement module 191 reads the circuit connection information from the circuit connection information storage area 210. The cell placement module 191 performs cell placement based on the circuit connection information and creates LSI layout information. The created layout information is stored in the layout information storage area 212.

(F) In step S160, the dangerous placement detection module 173 reads the layout information from the layout information storage area 212. Further, the dangerous placement detection module 173 reads out the cell failure occurrence risk Def _CELL included in the layout information from the risk library 302. The dangerous arrangement detection module 173 detects the dangerous cell arrangement from the layout information with reference to the cell defect occurrence risk Def _CELL . If a dangerous cell arrangement is detected, the process proceeds to step S170. When the dangerous cell arrangement is not detected, the process proceeds to step S200.

(G) In step S170, the arrangement correction module 174 corrects the cell arrangement using the method described with reference to FIGS. 43 to 47, and decreases the defect occurrence risk Def _CELL . New layout information in which the cell arrangement is corrected is stored in the layout information storage area 212. In step S180, the path delay calculation module 175 calculates the signal delay characteristic of the corrected signal path. Next, the path determination module 176 determines whether or not the calculated signal delay characteristic satisfies an allowable condition. If the signal delay characteristic satisfies the allowable condition, the process returns to step S160. If the signal delay characteristic does not satisfy the allowable condition, the process proceeds to step S190.

  (H) In step S190, the path correction module 177 corrects the signal path and creates new circuit connection information. Based on the new circuit connection information, the cell placement module 191 creates layout information. New layout information including the corrected signal path is stored in the layout information storage area 212. After creating new layout information, the process returns to step S180.

  (R) In step S200, the wiring arrangement module 192 reads layout information and circuit connection information from the layout information storage area 212 and the circuit connection information storage area 210, respectively. The wiring arrangement module 192 arranges wiring based on the circuit connection information and creates layout information including the wiring. The created layout information is stored in the layout information storage area 212.

  (Nu) In step S210, the dangerous placement detection module 173 reads layout information from the layout information storage area 212. The dangerous placement detection module 173 refers to the dangerous wiring pattern stored in the dangerous wiring library 304 and detects the dangerous wiring pattern included in the LSI layout information. If a dangerous cell arrangement is detected, the process proceeds to step S220. If a dangerous wiring pattern is not detected, the process proceeds to step S230.

  (L) In step S220, the layout correction module 174 corrects the wiring layout of the dangerous wiring pattern using the method already described. The new layout information whose wiring arrangement has been corrected is stored in the layout information storage area 212. After the dangerous wiring pattern is corrected, the process returns to step S210.

  (W) In step S230, the path delay calculation module 175 reads layout information from the layout information storage area 212. Further, the path delay calculation module 175 reads out the wiring delay information of the wiring pattern such as the delay characteristic table and the RC correction coefficient from the delay characteristic library 301. The path delay calculation module 175 calculates the signal delay characteristic of each signal path included in the layout information with reference to the delay characteristic table and the wiring delay information. The calculated signal delay characteristic is stored in the path delay storage area 211. Next, the path determination module 176 reads the signal delay characteristic and the allowable delay value from the path delay storage area 211 and the allowable condition storage area 209, respectively. The path determination module 176 compares the signal delay characteristic and the allowable delay value for each signal path, and determines whether the signal delay characteristic of each signal path satisfies the allowable condition. If the signal delay characteristic satisfies the allowable condition, the process proceeds to step S250. If the signal delay characteristic does not satisfy the allowable condition, the process proceeds to step S240.

  (E) In step S240, the layout is corrected so that the signal delay characteristic of each signal path satisfies the allowable condition. Specifically, for example, the replacement module 172 extracts a cell having a large delay variation from a signal path whose signal delay characteristic does not satisfy the allowable condition, and replaces the extracted cell with a cell having a small delay variation. Alternatively, the replacement module 172 replaces a wiring having a large RC correction coefficient with a wiring having a small RC correction coefficient. New layout information including the corrected signal path is stored in the layout information storage area 212. After the layout is corrected, the process returns to step S230.

(T) In step S250, the layout risk calculation module 163 reads layout information from the layout information storage area 212. Further, the layout risk level calculation module 163 reads the cell defect occurrence risk level Def _CELL and the wiring defect occurrence risk level DefW and DefV from the risk level library 302, respectively. The layout risk level calculation module 163 calculates the layout defect occurrence risk level Def _all using Equation (6). The calculated failure occurrence risk level Def _all is stored in the risk level storage area 213.

(L) In step S260, the layout determination module 171 reads the failure occurrence risk level Def _all and the layout allowable value from the risk level storage area 213 and the allowable condition storage area 209, respectively. The layout determination module 171 compares the failure occurrence risk level Def _all with the layout allowable value to determine whether the layout failure occurrence risk level Def _all satisfies the allowable condition. If the defect occurrence risk level Def _all is less than or equal to a predetermined layout allowable value, the process ends. If the defect occurrence risk level Def _all does not satisfy the allowable conditions, the process proceeds to step S270. If the allowable layout value is set for the cell defect occurrence risk Def _CELL or the wiring defect occurrence risk Def _WIRE , the defect occurrence risk Def _CELL or the wiring defect occurrence risk Def _WIRE satisfies the allowable conditions. It is determined whether or not each is satisfied.

(E) In step S270, the layout is corrected so that the defect occurrence risk level Def _all satisfies the permissible condition. Specifically, for example, the replacement module 172 reads the layout information and the cell defect occurrence risk Def _CELL from the layout information storage area 212 and the risk library 302. Substitution module 172, based on the failure risk Def _CELL of cells included in the layout information, a large cell failure risk Def _CELL and the like replace yield priority cell, reduce the failure risk Def _CELL. Here, the large cells of the failure risk Def _CELL, large cell, or failure risk Def _CELL constant value of the most failure risk Def _CELL among the cells included in the layout information (e.g., 0.001%) These cells and the like. Further, substitution module 172, a large wiring failure risk DefW or DefV extracted from the layout information, and change the extracted lines to reduce the failure risk Def _WIRE wiring. New layout information after the cell and wiring are changed is stored in the layout information storage area 212. After the layout is corrected, the process returns to step S230.

  The layout information stored in the layout information storage area 212 is output to the outside of the design system via the output device 50. Based on the layout information, a reticle or mask for manufacturing LSI is manufactured.

In the above description, an example has been described in which the dangerous placement detection module 173 detects the dangerous wiring pattern included in the layout information with reference to the dangerous wiring pattern stored in the dangerous wiring library 304 in step S210. The dangerous placement detection module 173 may detect the dangerous wiring pattern included in the layout information without referring to the dangerous wiring library 304. In other words, the dangerous placement detection module 173 extracts a wiring having a defect occurrence risk DefW or DefV of a certain value or more, for example, 0.001% or more from the layout information. Then, the arrangement correction module 174 corrects the wiring pattern including the detected wiring to reduce the defect occurrence risk Def _WIRE .

In step S220, step S240, and step S270, the dangerous wiring pattern generated due to the arrangement relationship between the wiring arranged in the wiring grid in the cell and the wiring connecting the cells, or the defect occurrence risk Def _WIRE The layout is corrected in consideration of the increase.

  In the above example, the logic synthesis module 18 creates the circuit connection information from the RTL description. However, the circuit connection information may be created from the behavior description. Further, although an example has been described in which the replacement module 172 replaces a cell having a high risk of failure occurrence with a cell having a low risk of failure occurrence, the LSI designer may manually replace the cell and change the layout.

  The series of LSI design operations shown in FIGS. 56 and 57 can be executed by controlling the design system shown in FIG. 1 with a program of an algorithm equivalent to that in FIGS. This program may be stored in the storage device 200 constituting the design system shown in FIG. Further, the program is stored in a computer-readable recording medium, and the recording medium is read into the storage device 200 shown in FIG. 1, whereby the series of LSI design operations of the present invention can be executed.

  As described above, in the design system according to the first embodiment of the present invention, the signal delay characteristic including the cell signal delay time calculated using systematic variation and the occurrence probability of the signal delay time is the delay characteristic. Stored in the library 301. Further, the risk occurrence risk of cells, wirings and vias calculated using systematic variation is stored in the risk library 302, and dangerous wiring patterns are stored in the dangerous wiring library 304. In the design system shown in FIG. 1, the path delay time of the signal path is calculated with reference to the signal delay characteristic of the cell, and the defect occurrence risk of the LSI layout is calculated with reference to the defect occurrence risk. . According to the design system shown in FIG. 1, the layout is changed when the delay time of the signal path does not satisfy the allowable condition, or when the risk of layout failure does not satisfy the allowable condition. As a result, an LSI is designed in consideration of systematic variations that affect performance and yield.

  According to the design system of the first embodiment, the influence of systematic manufacturing variations on LSI performance and yield is reduced. Furthermore, since a dangerous pattern is detected before mask data preparation (MDP) processing and optical proximity effect correction (OPC) processing, the design pattern is changed back to the upstream of LSI development in order to eliminate the dangerous pattern. There is no need. As a result, design efficiency is improved.

(Second embodiment)
As shown in FIG. 58, the design system according to the second exemplary embodiment of the present invention is different from the design system shown in FIG. 1 in that it further includes an arrangement constraint setting module 20 for setting constraint conditions for LSI layout. . Other configurations are the same as those of the first embodiment shown in FIG. In the first embodiment, the example in which the layout is changed when the signal delay characteristic of the signal path or the layout defect occurrence risk Def _all does not satisfy the permissible condition has been described. In the second embodiment, an example of a method of setting a layout constraint condition for cells and wirings and creating a layout according to the set layout constraint condition will be described.

  The placement constraint setting module 20 includes a cell constraint setting module 220, an in-cell wiring constraint setting module 221, and a wiring constraint setting module 222. The cell constraint setting module 220 sets a cell arrangement constraint condition that is a constraint on the distance between adjacent cells. The intra-cell wiring constraint setting module 221 sets intra-cell wiring constraint conditions that are constraints on the wirings arranged in the cell. The wiring restriction setting module 222 sets a wiring arrangement restriction condition that is a restriction on a wiring connecting cells.

  A method of setting the cell arrangement constraint condition will be described with reference to FIG. The cell arrangement constraint condition is set as a distance between cells. Here, the distance allowed between cells is referred to as an “inter-cell tolerance”. The allowable value between cells is set so that no defect occurs in the target cell due to the influence of systematic variations occurring in the target cell depending on the distance between adjacent cells. Specifically, the defect occurrence risk DefP of the target cell calculated by executing a process simulation in which the distance between the target cell and the adjacent cell is changed is less than a certain value (for example, 0.001%). An allowable value between cells is set. As already described, the defect occurrence risk level DefP is defined as the ratio of the analysis pattern shape to the design pattern shape of the target cell. The allowable value between cells is set for all combinations of cells stored in the cell library 303.

  (A) In steps S10 to S50 in FIG. 59, the analysis pattern shape of a cell that may be used in the LSI to be designed is acquired in the same manner as described with reference to the flowchart in FIG. The acquired analysis pattern shape is stored in the analysis pattern shape storage area 206.

  (B) In step S410, the cell risk calculation module 161 reads the analysis pattern shape of the target cell from the analysis pattern shape storage area 206. The cell risk level calculation module 161 calculates a defect occurrence risk level DefP of the target cell using the analysis pattern shape of the target cell. That is, the cell risk level calculation module 161 executes a process simulation using the distance between cells as a variation parameter, and acquires the defect occurrence risk level DefP. The calculated failure occurrence risk level DefP is stored in the risk level library 302.

  (C) In step S420, the cell constraint setting module 220 reads the failure occurrence risk level DefP from the risk level library 302. The cell constraint setting module 220 sets the cell placement constraint condition for the adjacent inter-cell distance for each combination of the target cell and the adjacent cell so that the failure occurrence risk DefP is equal to or less than a preset allowable value between cells. The set cell arrangement constraint condition is stored in the constraint condition library 305.

  The cell constraint setting module 220 sets cell placement constraint conditions for all combinations of cells stored in the cell library 303.

  Next, a method of setting the intra-cell wiring restriction condition for the wiring arranged in the cell will be described with reference to FIG. The intra-cell wiring constraint condition is set as a wiring grid that prohibits the arrangement of wiring and vias among the wiring grids in the cell. Here, the information of the wiring prohibition grid is referred to as “placement prohibition information”. The placement prohibition information is set based on the failure occurrence risk DefG. For example, a wiring grid whose defect occurrence risk DefG is equal to or greater than a wiring grid allowable value (for example, 0.001%) is set as a wiring prohibition grid.

  (A) In steps S10 to S50 in FIG. 60, an analysis pattern shape of a cell that may be used in the LSI to be designed is acquired in the same manner as described with reference to the flowchart in FIG. The acquired analysis pattern shape is stored in the analysis pattern shape storage area 206.

  (B) In step S510, the cell risk degree calculation module 161 reads the analysis pattern shape of the target cell from the analysis pattern shape storage area 206. The cell risk level calculation module 161 calculates a failure occurrence risk level DefG of the target cell using the analysis pattern shape of the target cell. That is, the cell risk calculation module 161 executes a process simulation assuming that a wiring or a via is arranged in each wiring grid in the target cell, and calculates a defect occurrence risk DefG for each wiring grid. The calculated failure occurrence risk level DefG is stored in the risk level library 302.

  (C) In step S520, the intra-cell wiring constraint setting module 221 reads the failure occurrence risk level DefG from the risk level library 302. The in-cell wiring constraint setting module 221 sets a wiring grid having a defect occurrence risk level DefG equal to or higher than a wiring grid allowable value set in advance as a wiring prohibition grid. Placement prohibition information, which is information about a wiring prohibition grid, is stored in the constraint condition library 305.

  The intra-cell wiring constraint setting module 221 sets a wiring prohibition grid for all cells stored in the cell library 303.

  A method of setting the wiring arrangement constraint condition for the wiring connecting the cells will be described with reference to FIG. The wiring arrangement constraint condition is set as a wiring pattern that cannot be used for the LSI layout among the wiring patterns composed of a combination of a plurality of wirings and vias. Here, a wiring pattern that cannot be used for layout is referred to as a “placement prohibition pattern”. The placement prohibition pattern is set so that no defect occurs in the target wiring due to the influence of systematic variation of adjacent wiring. Specifically, the placement prohibition pattern is set so that the defect occurrence risk DefW or DefV of the target wiring calculated for each wiring pattern is less than a predetermined wiring allowable value (for example, 0.001%).

  (A) In steps S10 to S50 in FIG. 61, the analysis pattern shape of the wiring pattern is acquired in the same manner as described with reference to the flowchart in FIG. The acquired analysis pattern shape is stored in the analysis pattern shape storage area 206.

  (B) In step S610, the wiring risk calculation module 162 reads the analysis pattern shape of the wiring pattern from the analysis pattern shape storage area 206. The wiring risk calculation module 162 calculates the wiring defect occurrence risk DefW and DefV using the analysis pattern shape of the wiring pattern. The calculated failure occurrence risk levels DefW and DefV are stored in the risk level library 302.

  (C) In step S620, the wiring constraint setting module 222 reads the failure occurrence risk level DefG from the risk level library 302. The wiring constraint setting module 222 sets a wiring pattern having a defect occurrence risk level DefW or DefV larger than a wiring allowable value as an arrangement prohibition pattern. The placement prohibition pattern is stored in the constraint condition library 305.

  Hereinafter, an example of a method for designing an LSI using the design system shown in FIG. 58 will be described with reference to a flowchart shown in FIG. It is assumed that the delay characteristic table is stored in the delay characteristic library 301 and the cell and wiring defect occurrence risk is stored in the risk library 302 by the method described with reference to the flowchart shown in FIG. In addition, the inter-cell tolerance, the intra-cell wiring grid placement prohibition information, and the wiring placement prohibition pattern, which are set by the method described with reference to the flowcharts shown in FIGS. Assume that it is stored.

  (A) In steps S110 to S140 of FIG. 62, the signal delay characteristics of the signal paths included in the LSI to be designed satisfy the allowable conditions in the same manner as described with reference to the flowchart shown in FIG. Until the signal path is corrected.

  (B) In step S 710, the cell placement module 191 reads out circuit connection information and cell placement constraint conditions from the circuit connection information storage area 210 and the constraint condition library 305. The cell placement module 191 creates the LSI layout information by performing the cell placement of the LSI to be designed based on the circuit connection information so as to satisfy the cell placement constraint conditions. That is, the cell arrangement module 191 arranges each cell such that the distance between the cells is equal to or greater than the allowable value set for each cell combination. The created layout information is stored in the layout information storage area 212.

  (C) In step S720, the path delay calculation module 175 reads layout information from the layout information storage area 212. The path delay calculation module 175 calculates the signal delay characteristic of the signal path included in the layout information. Next, the path determination module 176 determines whether or not the calculated signal delay characteristic satisfies an allowable condition. If the signal delay characteristic satisfies the allowable condition, the process proceeds to step S740. If the signal delay characteristic does not satisfy the allowable condition, the process proceeds to step S730.

  (D) In step S730, the path correction module 177 corrects the signal path and creates new circuit connection information. Based on the new circuit connection information, the cell placement module 191 creates layout information so as to satisfy the cell placement constraint conditions. New layout information including the corrected signal path is stored in the layout information storage area 212. After creating new layout information, the process returns to step S720.

  (E) In step S740, the wiring placement module 192 reads the layout information and the circuit connection information from the layout information storage area 212 and the circuit connection information storage area 210, respectively. Further, the wiring arrangement module 192 reads out the intra-cell wiring restriction condition and the wiring arrangement restriction condition from the restriction condition library 305. The wiring placement module 192 creates layout information by arranging wiring based on the circuit connection information so as to satisfy the intra-cell wiring restriction condition and the wiring placement restriction condition. In other words, the wiring placement module 192 prohibits the placement of wiring and vias on the wiring prohibited grid set as the intra-cell wiring restriction condition, and does not configure the placement prohibition pattern set as the wiring placement restriction condition. Place. The created layout information is stored in the layout information storage area 212.

  (F) In step S750, the path delay calculation module 175 reads layout information from the layout information storage area 212. Further, the path delay calculation module 175 reads out the wiring delay information of the wiring pattern such as the delay characteristic table and the RC correction coefficient from the delay characteristic library 301. The path delay calculation module 175 calculates the signal delay characteristic of each signal path included in the layout information with reference to the delay characteristic table and the wiring delay information. The calculated signal delay characteristic is stored in the path delay storage area 211. Next, the path determination module 176 reads the signal delay characteristic and the allowable delay value from the path delay storage area 211 and the allowable condition storage area 209, respectively. The path determination module 176 compares the signal delay characteristic and the allowable delay value for each signal path, and determines whether the signal delay characteristic of each signal path satisfies the allowable condition. If the signal delay characteristic satisfies the allowable condition, the process proceeds to step S770. If the signal delay characteristic does not satisfy the allowable condition, the process proceeds to step S760.

  (G) In step S760, the layout is modified so that the signal delay characteristic of each signal path satisfies the allowable condition. Specifically, for example, the replacement module 172 extracts a cell having a large delay variation from a signal path whose signal delay characteristic does not satisfy the allowable condition, and replaces the extracted cell with a cell having a small delay variation. Alternatively, the replacement module 172 replaces a wiring having a large RC correction coefficient with a wiring having a small RC correction coefficient. However, the layout is corrected so as to satisfy the cell and wiring arrangement constraint conditions. New layout information including the corrected signal path is stored in the layout information storage area 212. After the layout is corrected, the process returns to step S750.

(H) In step S770, the layout risk calculation module 163 reads the layout information from the layout information storage area 212. Furthermore, the layout risk level calculation module 163 reads the cell failure occurrence risk level Def _CELL and the wiring failure occurrence risk level DefW and DefV from the risk level library 302, respectively. The layout risk level calculation module 163 calculates the layout defect occurrence risk level Def _all using Equation (6). The calculated failure occurrence risk level Def _all is stored in the risk level storage area 213.

(R) In step S780, the layout determination module 171 reads the failure occurrence risk level Def _all and the layout allowable value from the risk level storage area 213 and the allowable condition storage area 209, respectively. The layout determination module 171 compares the failure occurrence risk level Def _all with the layout allowable value to determine whether the layout failure occurrence risk level Def _all satisfies the allowable condition. If the defect occurrence risk level Def _all is less than or equal to a predetermined layout allowable value, the process ends. If the defect occurrence risk level Def _all does not satisfy the allowable condition, the process proceeds to step S790.

(N) In step S790, the layout is corrected so that the degree of failure occurrence Def _all satisfies the allowable condition. Specifically, for example, the replacement module 172 reads the layout information and the cell defect occurrence risk Def _CELL from the layout information storage area 212 and the risk library 302. Substitution module 172, based on the failure risk Def _CELL of cells included in the layout information, a large cell failure risk Def _CELL and the like replace yield priority cell, reduce the failure risk Def _CELL. Further, substitution module 172, a large wiring failure risk DefW or DefV extracted from the layout information, and change the extracted lines to reduce the failure risk Def _WIRE wiring. However, the layout is corrected so as to satisfy the cell and wiring arrangement constraint conditions. New layout information after the cell and wiring are changed is stored in the layout information storage area 212. After the layout is corrected, the process returns to step S750.

  As described above, in the design system according to the second embodiment of the present invention, the cell layout and the wiring layout of the LSI to be designed are performed so as to satisfy the layout constraint conditions set for the cells and the wiring. Therefore, the layout after the cell arrangement does not include the dangerous cell arrangement. Further, the layout after the wiring arrangement does not include a dangerous wiring pattern. As a result, there is no need to detect a dangerous cell arrangement or a dangerous wiring pattern after creating layout information. That is, in the design system shown in FIG. 58, the design time can be shortened as compared with the case where the LSI is designed using the design system shown in FIG. Others are substantially the same as those in the first embodiment, and redundant description is omitted.

  It is to be noted that the dangerous cell arrangement or the dangerous wiring pattern can be detected from the layout information using the arrangement constraint condition. For example, the dangerous arrangement detection module 173 can detect the dangerous cell arrangement by detecting a cell arrangement in which the cell interval included in the layout information after the cell arrangement is smaller than the allowable value between cells. Alternatively, the dangerous placement detection module 173 can detect the placement prohibited pattern included in the layout information after the wiring placement as a dangerous wiring pattern.

(Other embodiments)
As described above, the present invention has been described according to the first and second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the first and second embodiments already described, the example in which the delay characteristic table is created using the systematic variation of the transistors included in the cell has been described. However, the systematic variation of other circuit elements such as resistors is described. May be used to create a delay characteristic table.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

1 is a schematic diagram showing a configuration of a semiconductor integrated circuit design system according to a first embodiment of the present invention; FIG. 2 is a schematic diagram showing a configuration of a semiconductor integrated circuit design system according to the first embodiment of the present invention, FIG. 2A is a schematic diagram showing a configuration of a delay characteristic calculation module, and FIG. FIG. 2C is a schematic diagram illustrating the configuration of the change module, and FIG. 2D is a schematic diagram illustrating the configuration of the arrangement module. It is a typical top view of a basic pattern concerning a 1st embodiment of the present invention. It is the typical top view which expanded a part of FIG. It is a graph for demonstrating the tolerance | permissible_range of the manufacturing conditions of a semiconductor integrated circuit. It is a schematic top view of the basic circuit of a semiconductor integrated circuit for explaining an example of systematic manufacturing variation. It is a table | surface which shows the example of a systematic manufacturing dispersion | variation. FIG. 8A is a schematic top view showing an example of a pattern for explaining a method of extracting systematic manufacturing variation information from manufacturing variation information. FIG. 8A is a pattern of a gate electrode distance S1, and FIG. b) shows a pattern of the distance S2 between the gate electrodes. FIG. 9A is a schematic top view showing a shape after the pattern shown in FIG. 8 is formed, FIG. 9A is a shape after the pattern shown in FIG. 8A is formed, and FIG. The shape after formation of the pattern shown in (b) is shown. FIG. 10A is a graph showing a shape distribution after the pattern shown in FIG. 8 is formed, FIG. 10A is a shape distribution after the pattern shown in FIG. 8A is formed, and FIG. The distribution of the shape after the pattern shown in (b) is formed is shown. FIG. 9 is a graph showing an example of fitting a shape distribution and a polynomial function after the pattern shown in FIG. 8 is formed. It is a graph which shows the example of the distribution of the systematic dispersion | variation of the basic pattern which concerns on the 1st Embodiment of this invention. FIGS. 13A and 13B are graphs showing examples of process simulation results for each manufacturing process. FIG. 13A is an exposure simulation, FIG. 13B is a focus simulation, and FIG. 13C is a channel length distribution calculated by an etching simulation. It is. It is a graph which shows the example which made the systematic variation and the process simulation result fit by the design system which concerns on the 1st Embodiment of this invention. It is a typical top view of the cell for demonstrating the design method by the design system which concerns on the 1st Embodiment of this invention. FIG. 16 is a schematic top view in which a part of FIG. 15 is enlarged. It is a graph which shows the example of distribution of the analysis pattern shape computed by the design system concerning a 1st embodiment of the present invention. It is a typical top view which shows the example of the cell arrangement | positioning for demonstrating the design method by the design system which concerns on the 1st Embodiment of this invention. It is a graph which shows the example of the discrete probability calculated by the design system which concerns on the 1st Embodiment of this invention. It is a table | surface which shows the example of the signal delay time of the cell calculated by the design system which concerns on the 1st Embodiment of this invention. It is an example of the cell for demonstrating the signal delay characteristic of the cell calculated by the design system which concerns on the 1st Embodiment of this invention. It is a graph which shows the example of distribution of the signal delay time of the cell calculated by the design system concerning a 1st embodiment of the present invention. It is a graph which shows the example of the discrete probability of the signal delay time of the cell calculated by the design system which concerns on the 1st Embodiment of this invention. It is a table | surface which shows the example of the delay characteristic table produced by the design system which concerns on the 1st Embodiment of this invention. It is a graph which shows the example of distribution of the analysis pattern shape computed by the design system concerning a 1st embodiment of the present invention. It is a graph which shows the example of the discrete probability calculated by the design system which concerns on the 1st Embodiment of this invention. It is a table | surface which shows the example of the signal delay time of the cell calculated by the design system which concerns on the 1st Embodiment of this invention. It is a typical top view of the cell which shows the example which has arrange | positioned wiring to the wiring grid in a cell. It is a typical top view which shows the example of the basic pattern of the wiring pattern which concerns on the 1st Embodiment of this invention. It is a typical top view which shows the example of the basic pattern of the wiring pattern which concerns on the 1st Embodiment of this invention. It is a typical top view which shows the example of the wiring pattern for demonstrating the setting method of the wiring delay information which concerns on the 1st Embodiment of this invention. It is a table | surface which shows the example of the wiring delay information which concerns on the 1st Embodiment of this invention. It is a typical top view of the cell for demonstrating the replacement | exchange method of the cell by the design system which concerns on the 1st Embodiment of this invention. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. FIG. 34 is a schematic top view showing an example of the yield priority cell of the cell shown in FIG. 33. It is a typical top view of the cell arrangement for explaining the change method of the cell arrangement by the design system concerning a 1st embodiment of the present invention. FIG. 44 is a schematic top view of a cell arrangement showing an example in which the cell arrangement shown in FIG. 43 is changed by the design system according to the first embodiment of the present invention. FIG. 44 is a schematic top view of a cell arrangement showing an example in which the cell arrangement shown in FIG. 43 is changed by the design system according to the first embodiment of the present invention. FIG. 44 is a schematic top view of a cell arrangement showing an example in which the cell arrangement shown in FIG. 43 is changed by the design system according to the first embodiment of the present invention. FIG. 44 is a schematic top view of a cell arrangement showing an example in which the cell arrangement shown in FIG. 43 is changed by the design system according to the first embodiment of the present invention. It is a typical top view of a wiring pattern for demonstrating the correction method of the wiring pattern by the design system which concerns on the 1st Embodiment of this invention. It is a typical top view which shows the example which the systematic dispersion | variation generate | occur | produced in the wiring pattern. FIG. 49 is a schematic top view of a wiring pattern showing an example in which the wiring pattern shown in FIG. 48 is modified by related technology. FIG. 49 is a schematic top view of a wiring pattern showing an example in which the wiring pattern shown in FIG. 48 is modified by the design system according to the first embodiment of the present invention. It is a schematic diagram which shows the example of the signal path | route for demonstrating the change method of the signal path | route by the design system which concerns on the 1st Embodiment of this invention. It is a table | surface which shows the example of the signal delay characteristic of the signal path | route calculated by the design system which concerns on the 1st Embodiment of this invention. FIG. 53 is a schematic diagram showing an example in which the signal path shown in FIG. 52 is modified by the design system according to the first embodiment of the present invention. FIG. 53 is a schematic diagram showing an example in which the signal path shown in FIG. 52 is modified by the design system according to the first embodiment of the present invention. 5 is a flowchart for explaining a method of designing an LSI by the design system according to the first embodiment of the present invention. (Part 1) 5 is a flowchart for explaining a method of designing an LSI by the design system according to the first embodiment of the present invention. (Part 2) It is a schematic diagram which shows the structure of the design system of the semiconductor integrated circuit which concerns on the 2nd Embodiment of this invention. It is a flowchart for demonstrating the method to set the arrangement | positioning restrictions of a cell by the design system which concerns on the 2nd Embodiment of this invention. It is a flowchart for demonstrating the method of setting the wiring restrictions in a cell by the design system which concerns on the 2nd Embodiment of this invention. It is a flowchart for demonstrating the method to set wiring arrangement | positioning restrictions by the design system which concerns on the 2nd Embodiment of this invention. It is a flowchart for demonstrating the method to design LSI by the design system which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Design unit 2 ... Measurement unit 11 ... Information acquisition module 12 ... Extraction module 13 ... Parameter setting module 14 ... Analysis pattern acquisition module 15 ... Delay characteristic calculation module 16 ... Risk calculation module 17 ... Change module 18 ... Logic synthesis module 19 ... Placement module 20 ... Placement restriction setting module 200 ... Storage device 301 ... Delay characteristic library 302 ... Risk level library 303 ... Cell library 304 ... Dangerous wiring library 305 ... Restriction condition library

Claims (5)

An extraction module that extracts systematic manufacturing variation from manufacturing variation information acquired from the shape measurement result of the basic pattern,
An analysis pattern acquisition module for acquiring an analysis pattern shape of a basic circuit including the basic pattern by a process simulation using parameters obtained from the systematic manufacturing variation and a process simulation execution result;
A delay characteristic calculation module for calculating a signal delay characteristic of the basic circuit using the analysis pattern shape;
A risk calculation module that compares the design pattern shape of the basic circuit with the analysis pattern shape and calculates a failure occurrence risk that a failure due to the systematic manufacturing variation occurs in the basic circuit. A semiconductor integrated circuit design system.   2. The semiconductor integrated circuit design system according to claim 1, wherein the failure occurrence risk is a ratio of the analysis pattern shape dimension to the design pattern shape dimension. The delay characteristic calculation module is
A delay time calculation module that calculates the signal delay time of the basic circuit and the occurrence probability of the signal delay time using the analysis pattern shape;
A table creation module that creates a delay characteristic table indicating a relationship between the input signal to the basic circuit and the characteristics of the output load of the basic circuit and the signal delay characteristic including the signal delay time and the occurrence probability. The semiconductor integrated circuit design system according to claim 1 or 2. A layout determination module that determines whether the sum of the risk of occurrence of defects of all the basic circuits included in the layout information satisfies an allowable condition;
A change module including a replacement module that replaces a basic circuit included in the layout information with a basic circuit having a lower risk of occurrence of defects than the basic circuit when the sum of the risk of failure occurrence does not satisfy an allowable condition. The semiconductor integrated circuit design system according to claim 1, wherein the system is a semiconductor integrated circuit design system. Using the signal delay time included in the signal delay characteristic of the basic circuit and the occurrence probability of the signal delay time, the signal delay time of the signal path configured by combining a plurality of the basic circuits and the occurrence probability of the signal delay time A path delay calculation module for calculating a signal delay characteristic of the signal path including:
A path determination module that determines whether a signal delay time of the signal path satisfies an allowable condition; and
And a path modification module that replaces a basic circuit included in the signal path with a basic circuit having a smaller delay variation than the basic circuit when the signal delay time of the signal path does not satisfy an allowable condition. The semiconductor integrated circuit design system according to claim 1, wherein the system is a semiconductor integrated circuit design system.

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