JP2002131882A - Method for correcting mask pattern, device for correcting mask pattern, recording medium storing mask pattern correcting program, and method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for correcting a mask pattern which forms a pattern that has high process likelihood and correction accuracy on a semiconductive wafer. SOLUTION: The method is at least provided with the first step which extracts patterns of which process likelihood to the fluctuation of an exposure quantity and a focal distance does not reach a prescribed reference value from patterns of mask used in an optical exposure process of a semiconductive device designed according to prescribed design rules, and the second step which corrects the patterns to satisfy the process likelihood with the reference value. To the pattern, which is producible on the design rules, of which fluctuation quantity of the pattern dimension becomes bigger by the fluctuation of the exposure quantity and the focal distance in the optical exposure process, it can improve its process likelihood.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask pattern correcting method for correcting a mask used in a light exposure process of a semiconductor device, a mask pattern correcting apparatus, a recording medium storing a mask pattern correcting program, and a method using the mask. The present invention relates to a method for manufacturing a semiconductor device including a light exposure step.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit, the design rule indicating the minimum line width that can be designed / manufactured has been reduced with the improvement of the fine processing technology. (E.g., length). The designer
Any pattern can be formed / arranged within a range satisfying the design rule, and a high-density integrated circuit can be designed.

[0005] However, the proximity effect (OPE: Optical Proximity) that occurs when a mask pattern is optically transferred onto a wafer due to a reduction in design rules and miniaturization of elements.
ityEffect) has come to influence device characteristics. For example, even if the pattern satisfies the design rule, the sharp portion in the pattern is rounded without being transferred, or the line width changes due to the density distribution of the line pattern. With the miniaturization of devices, the ratio of the proximity effect to the size of the device increases, which affects device characteristics.

Conventionally, as a method of correcting this OPE,
Various proximity effect correction (OPC: Optical Proximity Corr
Section) Techniques have been proposed. For example, by performing proximity effect correction for applying a predetermined correction (OPC) pattern to a pattern portion that is not transferred, the influence of the OPE is avoided, and the error between the design pattern and the transfer pattern on the wafer is reduced.

[0005]

However, with further miniaturization of semiconductor devices in recent years, depending on design rules and pattern arrangement, even if the design rules are satisfied, the process margin of the arranged pattern becomes a reference value. On the other hand, it may be small.

For example, in a light exposure (light lithography) process for a large-diameter wafer, it becomes difficult to keep the exposure amount (dose amount) and the focal length (focus) constant over the entire surface of the wafer. There are some errors in the exposure amount and the focal length between the center and the outer periphery of the wafer. When the exposure amount and the focal length change, the pattern transferred onto the wafer deviates from the design pattern.

As described above, even in a pattern arrangement that satisfies the design rule, a situation may occur in which the process margin for the variation of the exposure amount and the focal length cannot satisfy the reference value. In this case, the design rules must be limited so that the process margin satisfies the reference value, which is a great constraint on the design of the semiconductor device.

The conventional OPC technique corrects a mask dimension so that a pattern on a semiconductor wafer conforms to a design dimension, but does not increase a process margin of a designed design. Therefore, in the related art, it is not possible to correct a pattern whose process margin is less than the reference value.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a method of correcting a mask pattern for forming a pattern having a high process margin and a high correction accuracy on a semiconductor wafer. Another object of the present invention is to provide a mask pattern correcting apparatus and a recording medium storing a mask pattern correcting program.

Another object of the present invention is to provide a method of manufacturing a semiconductor device for manufacturing a semiconductor chip having a high degree of integration with a high yield.

[0011]

In order to achieve the above object, a first feature of the present invention is to provide a method for exposing a semiconductor device from a design pattern of a mask used in a light exposure process of a semiconductor device, which is designed according to a predetermined design rule. The method includes at least a first step of extracting a pattern whose process allowance with respect to variations in the amount and the focal length does not reach a predetermined reference value, and a second step of correcting the pattern so that the process allowance satisfies the reference value. This is a mask pattern correction method.

Here, the design rule is a design criterion for designing a mask pattern, and is a minimum line size and space size that can be manufactured by so-called fine processing technology such as light exposure technology and etching technology. And so forth. According to this design rule, even if the pattern can be manufactured, there is a pattern in which the pattern size greatly fluctuates due to the fluctuation of the exposure amount or the focal length in the light exposure process. If the variation of the pattern dimension due to the variation of the exposure amount or the focal length is large, it is determined that the “process margin” has not reached the reference value, and the design pattern is corrected.
The reference value of the process allowance is determined in consideration of design rules, fine processing accuracy, element electrical characteristics, and the like.

According to the first aspect of the present invention, it is possible to correct a process margin for a mask design pattern. The mask design pattern to be corrected is created in accordance with the design rules. Therefore, it is possible to correct a pattern whose process margin is less than the reference value without adding a rule regarding the process margin to the design rule or restricting the design rule. Further, it is possible to form a pattern whose process margin always satisfies the reference value on a semiconductor wafer and to form a mask pattern with high correction accuracy.

In the first aspect of the present invention, it is preferable that the method further includes a third step of determining whether or not the pattern pitch of the pattern is kept constant before and after the correction. It is conceivable that the pattern pitch changes before and after the correction by performing the process margin correction on the pattern. Therefore, the presence or absence of a change in the pattern pitch is determined for the corrected pattern, and if the pattern pitch is changed, the process margin is corrected again for the corresponding pattern. That is, if it is determined in the third step that the design rule is not satisfied, the process returns to the second step, and the correction is repeatedly performed until the process margin is satisfied and the pattern pitch is kept constant.
The correction accuracy can be further improved.

In the first aspect of the present invention, it is preferable that the method further includes a fourth step of determining whether the corrected pattern satisfies a design rule. By performing the process margin correction on the pattern, the process margin may be satisfied but the design rule may not be satisfied. Therefore, it is determined whether or not the corrected pattern satisfies the minimum line size and the minimum space size defined in the design rule. Make a degree correction. That is, if it is determined in the fourth step that the design rule is not satisfied, the second
Returning to the step, by repeatedly performing the correction until the process margin and the design rule are simultaneously satisfied, the correction accuracy can be further improved. The fourth step is the second step
It may be performed after the step, and the order of the third step is not particularly limited.

In the first aspect of the present invention, when the pattern corrected in the second step is a line pattern, the fourth step is to determine whether the line pattern is larger than a minimum line size and a minimum space size defined in a design rule. Preferably, the step is a step of determining whether the pattern has a line dimension and a space dimension. Further, when the pattern corrected in the second step is a wiring pattern, it is preferable to include a fifth step of determining whether or not the line size of the corrected wiring pattern is within an allowable range of the wiring capacitance. . By correcting the process margin on the wiring pattern, the case where the process margin is satisfied but the wiring capacitance becomes larger than the reference value may be considered. Therefore, it is determined whether or not the line size of the corrected wiring pattern is within the allowable range of the wiring capacitance. If the line size exceeds the allowable range, the process margin of the corresponding design pattern is again reduced. Make corrections. That is, when it is determined in the fifth step that the wiring capacitance is not within the allowable range, the process returns to the second step, and
By performing the correction repeatedly until the process tolerance and the capacity standard are simultaneously satisfied, the correction accuracy can be further improved. The fifth step may be performed after the second step, and the order of the third step or the fourth step is not particularly limited.

In the first feature of the present invention, the first step is: (1) simulating a light exposure process using a design pattern, and calculating a transfer pattern when the conditions of the exposure amount and the focal length are varied. A first operation, (2) a second operation of calculating a pattern dimension variation when the exposure amount and the focal length are changed using the transfer pattern, and (3) a pattern dimension variation of not less than a reference value. It is desirable that the method be configured to include a third operation of determining the process margin by determining whether or not there is a process margin.

In the first aspect of the present invention, when a desired pattern size or a desired pattern shape cannot be formed when the corrected design pattern is transferred and processed on a wafer after the second step, a desired pattern is formed. It is desirable to further perform proximity effect correction on the design pattern corrected in order to obtain the dimensions or the desired pattern shape. By performing the necessary proximity effect correction on the corrected design pattern, more accurate mask pattern correction can be performed.

The mask to be corrected is preferably of a line type such as a wiring pattern or a contact hole type. In the case of the line system, the process margin can be determined from the relationship between the line and the space adjacent thereto, and in the case of the contact hole system, the process margin can be determined from the relationship between the contact diameter and the distance between adjacent contacts. be able to. Further, it is desirable that the correction rule created in the contact hole system is independently applied to each side of the contact hole.

A second feature of the present invention is that a process margin for a change in exposure amount and a focal length is a predetermined value based on a design pattern of a mask used in a light exposure process of a semiconductor device designed according to a predetermined design rule. A mask pattern correction apparatus includes at least a pattern extraction unit that extracts a pattern that does not reach a reference value and a pattern correction unit that corrects the pattern so that the process margin satisfies the reference value.

A third feature of the present invention is that a process margin for a variation in exposure amount and focal length is determined by a predetermined pattern from a mask design pattern used in a light exposure process of a semiconductor device designed according to a predetermined design rule. A recording medium storing a mask pattern correction program including at least a first step of extracting a pattern that does not reach the reference value and a second step of correcting the pattern so that the process margin satisfies the reference value. is there.

A fourth feature of the present invention is that (1) a first step of designing a mask to be used in a light exposure process of a semiconductor device according to a predetermined design rule, and (2) an exposure amount based on a mask design pattern. A second step of extracting a pattern in which the process allowance for the change in the focal length does not reach a predetermined reference value; and (3) a third step of correcting the pattern so that the process allowance satisfies the reference value.
(4) a fourth step of performing proximity effect correction on the corrected design pattern, (5) a fifth step of manufacturing a mask based on the design pattern, and (6) a light exposure process using the mask. And a sixth step of manufacturing a semiconductor wafer by a predetermined semiconductor manufacturing process.

According to the fourth feature of the present invention, it is possible to manufacture a mask pattern with high accuracy of correction for variations in exposure amount or focal length in the light exposure step and for proximity effects without limiting the design rules. it can. Then, the pattern is transferred onto the semiconductor wafer using this mask,
By manufacturing a semiconductor integrated circuit, a semiconductor wafer with a low defect rate can be manufactured. Accordingly, it is possible to provide a method for manufacturing a semiconductor device with high production efficiency (manufacturing yield).

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a mask pattern correction device according to the first embodiment of the present invention. The mask pattern correction device 26 according to the first embodiment of the present invention includes a data storage unit 1 storing design pattern data and the like necessary for a mask pattern correction process, and a program storage unit 2 storing a mask pattern correction program and the like. And a processing control unit 3 having a function unit for executing a series of mask pattern correction processing. Processing control unit 3
Is a central processing unit (CP) of a normal computer system.
U). The data storage unit 1 and the program storage unit 2 may be constituted by a main storage device inside a CPU, and a semiconductor ROM or a semiconductor ROM connected to the CPU.
It may be constituted by a semiconductor memory such as an AM or a storage device such as a magnetic disk device.

The processing control unit 3 extracts, from the design pattern, a pattern whose process allowance with respect to the exposure amount (dose amount) and the focal length (focus) does not reach a predetermined reference value. And a pattern correction unit 7 that corrects the extracted pattern so that the process margin satisfies the reference value, and checks whether the corrected pattern pitch is kept constant with respect to the uncorrected pattern pitch. Pattern pitch checking unit 8 to perform, wiring capacity checking unit 9 for checking whether the wiring capacity of the corrected pattern is within an allowable range, and checking whether the corrected pattern satisfies the design rule. Proximity effect correction (OP
And C) a proximity effect correction (OPC) unit 11 for performing a proximity effect correction with a pattern.
These pattern extraction unit 6, pattern correction unit 7, pattern pitch check unit 8, wiring capacity check unit 9, design rule check unit 10, and OPC unit 11 may be configured by dedicated hardware, respectively. Each may be configured as functional means having substantially equivalent functions by software using the CPU of the system.

The pattern extracting section 6 sets a process margin for a change in exposure amount and a focal length to a predetermined reference value from a mask design pattern used in a light exposure process of a semiconductor device designed according to a predetermined design rule. It has a function to extract patterns that have not been reached.

The pattern extracting section 6 performs (1) a simulation of the light exposure step using the design pattern,
Means for calculating the transfer pattern when the conditions of the exposure amount and the focal length are varied; and (2) means for calculating the variation amount of the pattern dimensions when the conditions of the exposure amount and the focal length are varied using the transfer pattern. And (3) means for determining whether or not the amount of change in the pattern dimension is greater than a reference value, thereby determining the process margin. These functional units may be configured by dedicated hardware, respectively, or may be configured as functional units having substantially equivalent functions by software using a CPU of an ordinary computer system.

An input device 4 for receiving an input of data and instructions from an operator and an output device 5 for outputting a pattern correction result are connected to the processing control unit 3 via an input / output control unit 25. . The input device 4 is a keyboard, a mouse, a light pen or a floppy (registered trademark).
It is composed of a disk device and the like. The output device 5 includes a display device, a printer device, and the like.

The mask pattern correcting device 26 is connected to the mask pattern designing device 12. The mask pattern designing apparatus 12 has a function of designing a mask used in a light exposure process of a semiconductor device. The design pattern data is transmitted to the mask pattern correction device 26 and stored in the data storage unit 1.

Input data for each process executed by the process control unit 3 shown in FIG. 1 is stored in the data storage unit 1, and program instructions are stored in the program storage unit 2. These data and program instructions are transferred to CP
U, the control processing is performed by the processing control unit 3 inside the CPU, and data such as numerical information generated in each step is stored in the data storage unit 1 such as a RAM or a magnetic disk.

Next, referring to FIGS. 2 to 4, a processing procedure of mask pattern correction executed by the processing control section 3 will be described. The important points here are as follows. That is, in the prior art, the mask pattern is corrected by a technique such as OPC when the mask pattern is not transferred onto the wafer without changing the design pattern. On the other hand, the present invention extracts a pattern whose process margin does not satisfy the reference value from the design pattern, corrects the design pattern so that the process margin of the extracted pattern satisfies the reference value, and corrects the corrected pattern. If the design pattern is not transferred onto the wafer, the mask pattern is further corrected by a method such as OPC.

FIG. 2 is a flowchart showing the overall configuration of the mask pattern correction method according to the first embodiment of the present invention. In the first embodiment, attention is paid to the relationship between a line and a space adjacent thereto in a wiring pattern composed of a line and a space.
Then, a method of extracting a wiring pattern whose process margin obtained from the relationship between the line and the space does not satisfy the reference value and correcting the extracted wiring pattern so that the process margin of the extracted wiring pattern satisfies the reference value will be described.

(A) First, in step S01, a mask design pattern is read into the CPU, and a wiring pattern whose process margin obtained from the relationship between lines and spaces does not reach a reference value is extracted from the design pattern. According to design rules, there are wiring patterns that can be manufactured, but the pattern dimensions actually fluctuate greatly due to fluctuations in the exposure amount or focal length in the light exposure step. The wiring pattern having a large variation in the pattern dimension due to the variation in the exposure amount or the focal length is determined to be a wiring pattern whose process margin does not reach the reference value, and is extracted from the design pattern. Here, step S01 includes steps S011 to S016. FIG. 3 is a flowchart showing a detailed configuration of step S01.

First, in step S011, an arbitrary wiring pattern is selected from the design patterns. The number of wiring patterns to be selected may be singular, but is preferably plural. FIG. 4A illustrates the operation in step S01.
The three wiring patterns (13 to 1) selected in
5) shows an example. Selected wiring patterns (13-1
The line dimensions (L1, L2, L3) and space dimensions (S1, S2) of 5) are read from the design pattern data.

Next, in step S012, the conditions of the exposure amount and the focal length are varied to simulate the exposure process. FIG. 4B shows a simulation result (transfer pattern) of the wiring patterns (13 to 15) shown in FIG. The solid line indicates the design pattern shown in FIG. The broken lines show the transfer pattern of the maximum line size and the minimum line size when the conditions of the exposure amount and the focal length are varied within a predetermined range. Here, it is desirable that the predetermined range is a range in which the exposure amount and the focal length can be assumed in an actual light exposure process.

Next, in step S013, for each of the wiring patterns (13 to 15), an interval 16 between the maximum line size and the minimum line size (a variation amount of the pattern size) is calculated. As shown in FIG. 4B, the variation 16 of the wiring patterns 14 and 15 is larger than the variation 16 of the wiring pattern 13.

Next, in step S014, it is determined whether or not the variation 16 is greater than or equal to a reference value for each of the wiring patterns (13 to 15). If the variation 16 is equal to or larger than the reference value (YES in step S014), the process proceeds to step S015, where it is determined that the process margin is a wiring pattern that has not reached the reference value (process margin non-attainment pattern), and the design pattern Extracted from Fluctuation width 16
Is smaller than the reference value (NO in step S014), the process skips step S015 and proceeds to step 016. That is, it is determined that the wiring pattern has the process margin satisfying the reference value, and is excluded from the process margin correction target. Here, the variation of the wiring pattern 13 shown in FIG. 4B is determined to be smaller than the reference value, and the variation 16 of the patterns 14 and 15 is determined to be greater than or equal to the reference value. .

Next, in step S016, it is determined whether or not there is a wiring pattern which has not yet been selected (S011) among the design patterns. If all the wiring patterns in the design pattern have already been selected (YES in step S016), step S02
Proceed to. If all the wiring patterns in the design pattern have not been selected yet (N in step S016)
O), returning to step S011, and performing the above steps on the wiring pattern that has not been selected yet. And
This loop is repeated until all the wiring patterns in the design pattern are selected.

(B) Next, in step S02, a correction is performed on the wiring pattern extracted as the pattern not reaching the process margin so that the process margin satisfies the reference value. The wiring pattern 14 in which the variation 16 is equal to or more than the reference value
As shown in FIG. 4C, the line size and the space size are corrected so that the variation 16 becomes smaller than the reference value for the wiring pattern 15. For example, the line size of the wiring pattern 14 is increased from L2 to L2 ′, and the space size with the wiring pattern 13 is reduced from S1 to S1 ′. Similarly, the line size and the space size of the wiring pattern 15 are corrected. In order to correct the variation 16 so as to be smaller than the reference value, the simulation of the exposure process and the pattern correction work are linked, and the simulation and the correction work are repeatedly performed until the variation 16 becomes smaller than the reference value. Just do it.

(C) Next, in step S03, it is checked whether the pattern pitch is kept constant before and after the correction. Before and after the correction, the pattern size and the space size change, but it is desirable that the pattern pitch does not change. However, depending on the way of correction, it may be possible to change up to the pattern pitch. Therefore, after the pattern is corrected, the pattern pitch is checked, and the pattern pitch is kept constant before and after the correction.

In FIG. 4C, the line size L2 'of the wiring pattern 14 after correction and the line size L3' of the wiring pattern 15 after correction are respectively wider than the line size L2 and the line size L3 before correction. ing. However, the space dimensions S1 and S2 before correction are reduced to the space dimensions S1 ′ and S2 ′ after correction, respectively.
Therefore, before and after the correction, three wiring patterns (13 to 1)
The pattern pitch of 5) is kept constant.

If the pattern pitch is held constant before and after the correction (YES in step S03), the process proceeds to step S04. If the pattern pitch is not held constant (NO in step S03), the process proceeds to step S04.
02, the pattern is corrected again so that the pattern pitch is kept constant.

(D) Next, in step S04, it is determined whether or not the wiring capacitance of the corrected wiring pattern is within an allowable range. Usually, in designing a wiring pattern, an allowable range is provided for a parasitic capacitance (wiring capacitance) generated between upper and lower wiring layers. If the wiring capacitance exceeds the allowable range, there is a possibility that problems such as a decrease in operation speed and signal delay may occur. In addition, when correcting the process margin of the wiring pattern, it is conceivable that the allowable range may be exceeded by increasing the line size. Therefore, after correcting the process margin, it is determined whether or not the wiring capacitance is within an allowable range. If the wiring capacity of the corrected wiring patterns (13 to 15) is within the allowable range (YES in step S04), the process proceeds to step S05. Corrected wiring pattern (13-1
If the wiring capacity of 5) is not within the allowable range (NO in step S04), the process returns to step S02,
The pattern correction is performed again so that the wiring capacitance falls within the allowable range.

(E) Next, in step S05, it is determined whether or not the corrected wiring pattern satisfies the design rule. That is, it is determined whether the line size and the space size of the corrected wiring pattern are equal to or larger than the minimum line size and the minimum space size defined by the design rule. Similar to the pattern pitch or the wiring capacitance, the corrected wiring pattern may violate the design rule due to the correction of the process margin. Therefore, a design rule check is performed after the process margin is corrected. If the corrected wiring pattern satisfies the design rule (YES in step S05), the process proceeds to step S06. If the corrected wiring pattern does not satisfy the design rule (N in step S05)
O), returning to step S02, performing pattern correction again so as to satisfy the design rule.

(F) Next, in step S06, an OPC pattern is applied to a necessary portion of the corrected wiring pattern, and proximity effect correction (OPC) is performed.

(G) Finally, in step S07,
A mask is manufactured based on the design pattern data.

A program for implementing the mask pattern correcting method according to the first embodiment of the present invention can be stored in a computer-readable recording medium. This recording medium is the program storage unit 2 shown in FIG.
, Or read into the program storage unit 2, and various operations in the processing control unit 3 can be executed according to a predetermined processing procedure by this program.
Here, the recording medium includes a recording medium that can record a program such as a semiconductor memory such as a ROM and a RAM, a magnetic disk, an optical disk, and a magnetic tape.

FIG. 6 shows programs read from these recording media, and according to the procedures described therein.
FIG. 3 is an external view illustrating an example of a mask pattern correction device 90 including a computer system that implements a mask pattern correction program. A floppy disk drive 91 and a CD-ROM drive 92 are provided on the front of the main body of the mask pattern correcting device 90. A floppy disk 93 as a magnetic disk or a CD-ROM 94 as an optical disk is inserted from each drive entrance. By performing a predetermined read operation, the programs stored in these recording media can be installed in the system. Also, a predetermined drive device 97
Can be used, for example, a ROM 95 as a semiconductor memory used for a game pack or the like or a cassette tape 96 as a magnetic tape can be used. Further, the mask pattern designing device 12 is connected in contact with the back surface of the main body of the mask pattern correcting device 90, and the process margin can be corrected on the design pattern data on the spot where the mask design is performed.

According to the first embodiment of the present invention, when the design pattern is a wiring pattern, a wiring pattern whose process margin does not reach the reference value is extracted from the design pattern to correct the process margin. Can be applied. Therefore, it can be formed on a mask of a wiring pattern whose process margin always satisfies the reference value. Also, by checking the wiring capacity, pattern pitch, design rules, etc. and OPC correction simultaneously with the process margin,
A mask pattern with high correction accuracy can be formed. Further, it is possible to correct a pattern having a process margin less than a reference value without adding a rule regarding the process margin to the design rule or restricting the design rule.

(Second Embodiment) In the first embodiment, the case where the pattern to be corrected is a wiring pattern (line pattern) composed of lines and spaces has been described. However, the present invention is not limited to this, and can be applied to a pattern of an arbitrary layer other than a line pattern such as a contact hole and a gate electrode. In the second embodiment, a mask pattern correction method will be described using a contact hole pattern as an example. In the second embodiment, attention is paid to the relationship between the contact hole pattern and the space between adjacent contact hole patterns, and a pattern arrangement in which the process margin of the contact hole pattern does not satisfy the reference value is extracted. A method for correcting such that it satisfies the process margin will be described.

(A) First, an arbitrary contact hole pattern is selected from the design patterns. FIG. 5A is a layout diagram showing contact hole patterns arbitrarily selected from design patterns. Contact hole 1
7 and other contact holes (18, 20-22) at predetermined intervals, one at a time, one at each of the top, bottom, left and right
Is arranged. Here, the pattern dimensions of the vertically arranged contact holes (17, 18, 20) are HV1, HV2, HV3, the space dimension between the contact holes 17 and 18 is DV1, and the space dimension between the contact holes 17 and 20 is DV1. The dimensions are DV2.

(B) Next, a simulation of the exposure process is performed by changing the conditions of the exposure amount and the focal length. FIG.
FIG. 5B shows a simulation result (transfer pattern) of the contact hole pattern shown in FIG. The solid line indicates the design pattern shown in FIG. The dashed lines indicate the transfer pattern of the maximum pattern size and the minimum pattern size when the conditions of the exposure amount and the focal length are varied within a predetermined range.

(C) Next, a variation 23 between the maximum pattern size and the minimum pattern size is calculated for each contact hole pattern. As shown in FIG. 5B, the amount of fluctuation 23 in the vertical direction of the contact holes 17, 18, and 20 is increased.
Is larger than the variation 23 of other contact holes and the variation 23 in other directions.

(D) Next, for each contact hole pattern, it is determined whether or not the variation 23 is equal to or greater than a reference value. Here, it is assumed that the amount of change 23 in the vertical direction of the contact holes 17, 18, and 20 is equal to or greater than the reference value, and the amount of change 23 in the other portions is smaller than the reference value. Therefore, it is determined that the contact holes 17, 18, and 20 are patterns in which the process margin does not reach the reference value (process margin non-attainment pattern), and are extracted from the design pattern.

(E) Next, for the contact hole patterns 17, 18, and 20 in which the fluctuation amount 23 is equal to or larger than the reference value, correction is made so that the fluctuation amount 23 becomes smaller than the reference value. However, a correction is applied to the vertical dimension of the contact hole patterns 17, 18, and 20 in which the fluctuation amount is equal to or more than the reference value. More specifically, as shown in FIG. 5C, the vertical pattern dimensions HV1, HV2, HV3
To HV1 ′, HV2 ′ and HV3 ′, respectively, and increase the space dimensions DV1 and DV2 to DV1 ′ and DV2 ′, respectively.
Narrow down. Also, contact hole patterns 17, 1
No correction is made to the horizontal and vertical pattern dimensions of 8, 20 and the contact hole patterns 21, 22 in the vertical and horizontal directions. When the above correction is performed, the created correction rule is independently applied to each side of the contact hole pattern.

(F) Next, the first embodiment shows whether the pattern pitch is kept constant before and after the correction and whether the corrected wiring pattern satisfies the design rule. Perform various rule checks. However,
For the contact hole pattern, the rule check of the wiring capacitance may be omitted. The contact hole pattern after the correction shown in FIG.
Since the space dimensions DV1 'and DV2' are narrowed by the width of V1 ', HV2' and HV3 ', the pattern pitch before and after correction is kept constant. Also,
The corrected space dimensions DV1 'and DV2' are equal to or larger than the minimum space dimension defined by the design rule, and thus satisfy the design rule. Next, an OPC pattern is applied to a necessary portion of the corrected contact hole pattern to perform proximity effect correction (OPC). Finally, a mask is manufactured based on the design pattern data.

According to the second embodiment of the present invention, even when the design pattern is a contact hole pattern, the same operation and effect as in the case of the wiring pattern shown in the first embodiment can be obtained. it can.

As described above, by performing the mask pattern correction according to the present invention, the process margin of the mask pattern such as the wiring pattern and the contact hole pattern can be increased. The mask to be corrected is not limited to a wiring pattern or a contact hole pattern, but may be a mask pattern such as an element region pattern, or an electrode pattern of a transistor such as a source, a drain, or a gate. By applying this Pasque pattern correction to a mask used in a semiconductor device manufacturing process, a semiconductor device with high correction accuracy can be manufactured. A method for manufacturing a semiconductor device will be described in a third embodiment.

(Third Embodiment) In a third embodiment of the present invention, a method of manufacturing a semiconductor device using the mask pattern correction method shown in the first and second embodiments will be described. I do. FIG. 7 is a flowchart showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

First, in step S21, what kind of function is necessary for the purpose and the effect of the semiconductor device to be manufactured is clarified, and various parts such as a logic memory and an input / output circuit for producing the function are clarified. Designing the functions and connections with each other, so-called function design. Next, in step S22, a so-called logic / circuit design is performed in which a specific electronic circuit is designed based on the functions and interrelationships of the respective units.

Next, in step S23, a layout design is performed on how the electronic circuit is arranged on the semiconductor chip, and a mask pattern of a plurality of layers used in a series of manufacturing steps of the semiconductor wafer is designed. The design pattern data created by the layout / mask pattern design is sent to the mask pattern correction device 26 described in the first embodiment, and the mask pattern correction method described in the first or second embodiment is used. Thus, correction of the process margin is performed.

More specifically, in step S24, a pattern whose process margin has not reached the reference value is extracted from the design pattern. In step S25, a correction is made to the process margin unachieved pattern so that the process margin satisfies the reference value. Step S
26, whether the pattern pitch is kept constant before and after correction, whether the wiring capacitance of the corrected wiring pattern is within an allowable range, or whether the corrected pattern satisfies the design rule Performs various rule checks such as After confirming that the design pattern satisfies the various rules, in step S27, OPC is performed on a necessary portion of the corrected pattern.
Proximity effect correction (OPC) is performed by adding a pattern.

Next, in step S28, a mask is manufactured based on the design pattern data to which the process margin has been corrected. In step S29, a series of wafer processes (pre-process) in which a photo-exposure process using this mask, a process of forming an insulating film, a semiconductor film, a metal film, and the like on a semiconductor substrate, and an etching process are repeated, are performed on the semiconductor wafer. A plurality of semiconductor integrated circuits are collectively formed. In step S30, the method of manufacturing the semiconductor device according to the third embodiment ends after a post-process (packaging process) including a dicing process, a bonding process, an inspection process, and the like.

As described above, according to the third embodiment of the present invention, a variation in the exposure amount or the focal length in the light exposure step and a high correction accuracy with respect to the proximity effect can be achieved without restricting the design rule. A mask pattern can be manufactured. Then, by transferring a pattern onto a semiconductor wafer using this mask to form a semiconductor integrated circuit, a semiconductor wafer with a low defect rate can be manufactured.

[0065]

As described above, according to the present invention, a mask pattern correcting method, a mask pattern correcting apparatus, and a recording device storing a mask pattern correcting program for forming a pattern having a high process margin and high correction accuracy on a semiconductor wafer. A medium can be provided.

Further, according to the present invention, it is possible to provide a method of manufacturing a semiconductor device for manufacturing a semiconductor chip having a high degree of integration with a high yield.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a mask pattern correction apparatus according to an embodiment of the present invention.

FIG. 2 is a flowchart illustrating an overall configuration of a mask pattern correction method according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a detailed configuration of step S01 shown in FIG.

FIG. 4A is a layout diagram illustrating a state before correction of a wiring pattern according to the first embodiment of the present invention. FIG. 4B is a layout diagram showing a transfer pattern of the maximum line size and the minimum line size when the exposure amount and the focal length conditions are varied with respect to the wiring pattern shown in FIG. FIG. 4C is a layout diagram showing a state after correction of the wiring pattern shown in FIG.

FIG. 5A is a layout diagram showing a state before correction of a contact hole pattern according to a second embodiment of the present invention. FIG. 5B is a layout diagram showing a transfer pattern of the maximum pattern size and the minimum pattern size when the conditions of the exposure amount and the focal length are varied with respect to the contact hole pattern shown in FIG. FIG.
FIG. 5C is a layout diagram illustrating a state after correction of the wiring pattern illustrated in FIG.

FIG. 6 is an external view showing an example of a mask pattern correction apparatus including a computer system that reads a mask pattern correction program stored in a recording medium and implements a mask pattern correction system in accordance with a procedure described therein.

FIG. 7 is a flowchart illustrating a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 data storage unit 2 program storage unit 3 processing control unit 4 input device 5 output device 6 pattern extraction unit 7 pattern correction unit 8 pattern pitch check unit 9 wiring capacitance check unit 10 design rule check unit 11 proximity effect correction (OPC) unit 12 Mask pattern design device 25 Input / output control unit 26 Mask pattern correction device 13, 14, 15 Wiring pattern 16, 23 Variation 17, 18, 20, 21, 22 Contact hole pattern

Claims (9)

[Claims] 1. A method according to claim 1, wherein a design margin of a mask used in a light exposure process of a semiconductor device, which is designed in accordance with a predetermined design rule, does not reach a predetermined reference value with respect to a variation in exposure amount and focal length. And a second step of correcting the pattern so that the process margin satisfies the reference value. 2. The method according to claim 1, further comprising a third step of determining whether a pattern pitch of the pattern is kept constant before and after the correction. 3. The method according to claim 1, further comprising a fourth step of determining whether the corrected pattern satisfies the design rule. 4. When the pattern corrected in the second step is a line pattern, the fourth step is that the line pattern has a line size that is equal to or larger than a minimum line size and a minimum space size defined in the design rule. 4. The method according to claim 3, further comprising the step of determining whether the pattern has a space dimension. 5. When the pattern corrected in the second step is a wiring pattern, determining whether or not the line size of the corrected wiring pattern is within an allowable range of the wiring capacitance. 4. The method according to claim 1, further comprising the step of: 6. The first step includes: performing a simulation of a light exposure process using the design pattern, and calculating a transfer pattern when a condition of an exposure amount and a focal length is varied; A second operation of calculating the amount of change in the pattern dimension when the exposure amount and the focal length are changed, and determining whether the amount of change in the pattern dimension is equal to or more than a reference value, thereby obtaining the process. Third to determine the margin
2. The method according to claim 1, wherein the method comprises the steps of: 7. A pattern in which a process margin with respect to a variation of an exposure amount and a focal length does not reach a predetermined reference value from a mask design pattern used in a light exposure process of a semiconductor device designed according to a predetermined design rule. And a pattern correction unit that corrects the pattern so that the process margin satisfies the reference value. 8. A pattern in which a process margin with respect to a change in an exposure amount and a focal length does not reach a predetermined reference value from a mask design pattern used in a light exposure process of a semiconductor device designed according to a predetermined design rule. And a second step of correcting the pattern so that the process margin satisfies the reference value. A recording medium storing a mask pattern correction program. 9. A first step of designing a mask to be used in a light exposure step of a semiconductor device according to a predetermined design rule, and a process margin for a variation in an exposure amount and a focal length is determined based on a design pattern of the mask. A second step of extracting a pattern that does not reach a reference value; a third step of correcting the pattern so that the process margin satisfies the reference value; and performing proximity effect correction on the corrected design pattern. 4th
And a fifth step of manufacturing a mask based on the design pattern; and a sixth step of manufacturing a semiconductor wafer by a predetermined semiconductor manufacturing process including a light exposure process using the mask. A method for manufacturing a semiconductor device.