JP2009231565A - Method of manufacturing nonvolatile semiconductor memory device, and nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the reliability by retaining the protective performance of a gate insulating film through a sidewall insulating film when self align-contact structure is applied between lamination gate electrodes. <P>SOLUTION: An RTO (rapid thermal oxidation) film 11 is formed along a control gate electrode CG, insulating film 7 between gates and the sidewall of a floating gate electrode FG. A silicon nitride film 13 is formed so as to cover the upper surface as well as the side surface of gate electrodes MG1, MG2 and the upper end 11a as well as the side surface of the RTO film 11. A contact hole DH is formed along the outer surface of a silicon nitride film 13 to the upper part of the upper surface of the silicon substrate 2. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a nonvolatile semiconductor memory device having a stacked gate electrode structure in which a floating gate electrode and a control gate electrode are sandwiched between gate insulating films, and a nonvolatile semiconductor memory device.

  In the technical field of non-volatile semiconductor memory devices, the trend of design rule reduction and element miniaturization has become more prominent. In general, a nonvolatile semiconductor memory device is a stack in which a floating gate electrode and a control gate electrode are sandwiched between a second gate insulating film and a cap insulating film is further stacked on a semiconductor substrate via a first gate insulating film. The gate electrodes are arranged in a matrix, and the source / drain regions are formed on the surface layer of the semiconductor substrate on both sides of the stacked gate electrodes (see, for example, Patent Document 1). According to the technique described in Patent Document 1, in a NOR type flash memory device, a gate barrier film made of a silicon dioxide film is formed along the side wall of the laminated gate electrode. Also disclosed is a form in which the contact barrier film is formed directly on the sidewall of the laminated gate electrode by a nitride insulating film.

  As shown in the technical idea described in Patent Document 1, in order to obtain electrical coupling with the source / drain regions formed in the surface layer of the semiconductor substrate, between the stacked gate electrodes, for example, between the electrodes by BPSG After embedding the insulating film, a contact plug is formed between the plurality of stacked gate electrodes. With the recent reduction in design rules, the width of a plurality of adjacent memory cell gate electrodes and the interval between the gate electrodes have been remarkably narrowed. In order to form this contact plug, a self-aligned contact (SAC) structure is used. It is good to apply.

However, as disclosed in Patent Document 1, when the contact barrier film is formed directly along the sidewall of the gate insulating film by the nitride insulating film in the region to which the self-aligned contact structure is applied, the gate Since the reliability of an insulating film is inferior, it is not preferable.
JP 2002-57230 A (0081 paragraph)

  It is an object of the present invention to provide a nonvolatile semiconductor memory device and a method for manufacturing the same that can improve the reliability of a gate insulating film when a self-aligned contact structure is applied between stacked gate electrodes. .

  One embodiment of the present invention includes a step of forming a first gate insulating film over a semiconductor substrate, and a plurality of floating gate electrodes, a plurality of second gate insulating films, a plurality of gates on the first gate insulating film. A step of forming a plurality of stacked gate electrodes by sequentially stacking a control gate electrode and a plurality of cap insulating films; and a plurality of control gate electrodes and a plurality of floating gates by performing an RTO (Rapid Thermal Oxide) process on the plurality of stacked gate electrodes. Forming a first insulating film by the RTO along side walls of the gate electrode and the plurality of second gate insulating films; and the same kind as the cap insulating film so as to cover the first insulating film and the plurality of stacked gate electrodes A step of forming a second insulating film of a material, the step of forming a second insulating film with a highly selectable material during etching with the first insulating film; the cap insulating film; and First and A step of forming an inter-electrode insulating film with a highly selectable material at the time of etching with the cap insulating film located inside the two insulating films, and a condition having high selectivity with respect to the cap insulating film The etching process is performed on the inter-electrode insulating film, so that the second insulating film covering the stacked gate electrode covers the upper end of the first insulating film while leaving the second insulating film in a self-aligned contact hole. And a step of forming a contact plug in the contact hole.

  One embodiment of the present invention includes a semiconductor substrate, a first gate insulating film formed over the semiconductor substrate, a plurality of floating gate electrodes formed over the first gate insulating film, and the plurality of floating floating electrodes. A plurality of second gate insulating films respectively formed on the gate electrodes, a plurality of control gate electrodes respectively formed on the plurality of second gate insulating films, and a part on the plurality of control gate electrodes A plurality of stacked gate electrodes each formed of a plurality of cap insulating films formed by removing upper shoulder portions in a cross section; a plurality of floating gate electrodes and a plurality of second gate insulators constituting the plurality of stacked gate electrodes; A sidewall insulating film made of an RTO film formed along the sidewall of the film, the upper end height being located below the upper surface of the control gate electrode and above the lower surface of the control gate electrode A barrier film formed between the sidewall insulating films of the plurality of stacked gate electrodes and formed to cover the sidewall insulating film, and a barrier film between the sidewall insulating films of the plurality of stacked gate electrodes A contact plug formed on the inside of the semiconductor device, the lower surface of which is formed along the missing surface of the cap insulating film and the outer surface of the barrier film, and is curved in a self-aligned manner until reaching the upper surface of the semiconductor substrate. It has a contact plug.

  According to one embodiment of the present invention, when a self-aligned contact structure is applied between stacked gate electrodes, the reliability of the gate insulating film can be improved.

(First embodiment)
Hereinafter, a first embodiment in which a nonvolatile semiconductor memory device of the present invention is applied to a NOR type flash memory device will be described with reference to the drawings. In the description of the drawings referred to below, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic, and the plane dimension ratio of each layer, the relationship between the thickness and the plane dimension, the ratio of the thickness of each layer, and the like are different from the actual ones.

  FIG. 1 shows an equivalent circuit diagram of a part of an electrical configuration of a cell array constituting a NOR type flash memory device, and FIG. 2 is a plan view of a portion corresponding to the electrical configuration shown in FIG. Show. The NOR type flash memory device 1 is divided into a memory cell region M and a peripheral circuit region (not shown), and a memory cell array (hereinafter referred to as cell array) Ar formed in the memory cell region M is arranged around the peripheral circuit region. It is configured to be driven by a circuit.

  As shown in FIG. 1, in the cell array Ar, memory cell transistors Tm1 and Tm2 (hereinafter abbreviated as transistors Tm1 and Tm2 respectively) are arranged in a matrix with respect to the XY direction (in-surface direction of the silicon substrate 2). Consists of. The transistors Tm1 and Tm2 are given the same reference numerals for the sake of explanation, but have almost the same structure. Here, the X direction and the Y direction are directions orthogonal to each other within the surface of the silicon substrate 2 (see FIG. 2).

  As shown in FIG. 1, two (a set) of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the Y direction, and the set of transistors Tm1 and Tm2 share a drain region. ing. The drain region is electrically connected to a bit line BL extending in the Y direction.

  A pair of these transistors Tm1 and Tm2 are arranged in the Y direction. The drain regions of the plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are commonly connected to one bit line (data line) BL. Two pairs of transistors Tm1 and Tm2 adjacent in the Y direction are arranged symmetrically with respect to the local source line LSL1 or LSL2.

  A plurality of pairs of transistors Tm1 and Tm2 arranged in the Y direction are arranged in a plurality of rows with a separation in the X direction. As a result, the transistors Tm1 and Tm2 are arranged in a matrix in the XY direction, and constitute a cell array Ar in the memory cell region M.

  A plurality of bit lines BL are juxtaposed in correspondence with the transistors Tm1 and Tm2 arranged in a plurality of columns separated in the X direction. The plurality of bit lines BL are formed at the same interval in the X direction, and a plurality of main source lines MSL are arranged between the plurality of bit lines BL for each of a plurality of predetermined numbers. The main source line MSL is a source line that becomes a source potential.

  Transistors Tm1 arranged in the X direction have their gates (control gate electrode CG (see FIG. 3) commonly connected by a word line WL1. Transistors Tm2 arranged in the X direction have their gates (control gate electrode CG). (See FIG. 3) is commonly connected by a word line WL2, which extends in the X direction in parallel with each other.

  The transistors Tm1 arranged in the X direction are commonly connected to a local source line (common source line) LSL2 whose source (source region 2b (see FIG. 3)) extends in the X direction. The plurality of local source lines LSL1 and LSL2 are spaced apart from each other in the Y direction, extend in the X direction, and are commonly connected to the main source line MSL extending in the Y direction.

  As shown in FIG. 2, the gate electrode MG1 of the transistor Tm1 is configured in the intersection region between the word line WL1 and the bit line BL, and the transistor Tm2 is disposed in the intersection region between the word line WL2 and the bit line BL. A gate electrode MG2 is configured. The gate electrodes MG1 and MG2 of these transistors Tm1 and Tm2 are arranged in the XY direction.

  As shown in FIGS. 1 and 2, transistors Tm1 and Tm1 adjacent in the Y direction share one local source line LSL1 disposed in the center in the Y direction between the gate electrodes MG1-MG1. . Similarly, the transistors Tm2 and Tm2 adjacent in the Y direction share one local source line LSL2 disposed at the center in the Y direction between the gate electrodes MG2 and MG2.

  FIG. 3 schematically shows a longitudinal sectional view taken along line AA of FIG. As shown in FIGS. 2 and 3, a drain contact DC and a drain via plug DV are stacked so as to be located, for example, in the center between adjacent word lines WL1 and WL2 and immediately below the bit line BL. These drain contacts DC and drain via plugs DV are configured to extend in the vertical direction (Z direction orthogonal to the XY plane) from directly above the silicon substrate 2, and are formed in the drain regions 2a of the transistors Tm1 and Tm2 (FIG. 3). And a bit line BL disposed above in the vertical direction are provided for electrical and structural connection.

  In the memory cell region M, a multilayer structure is formed in the Z direction with respect to the silicon substrate 2, and (1) the surface layer LY1 of the silicon substrate 2 from the lower layer side to the upper layer side, (2) the contact plug formation layer LY2, (3) A via plug formation layer LY3 and (4) a wiring layer LY4 are provided.

  Note that (2) the stacked gate electrode layer LY2a is provided in a part of the same layer as the (2) contact plug formation layer LY2. In these layers (1) to (4), the following electrically conductive elements are formed.

(1) Surface layer LY1
Drain region 2a, source region 2b
(2) Contact plug formation layer LY2
Drain contact DC, local source line LSL1, local source line LSL2 (not shown in FIG. 3)
(2a) Stacked gate electrode layer LY2a
Memory cell transistor gate electrode MG1 (floating gate electrode FG, intergate insulating film 7, control gate electrode CG, silicon nitride film 10), memory cell transistor gate electrode MG2 (floating gate electrode FG, intergate insulating film 7, control) Gate electrode CG, silicon nitride film 10)
(3) Via plug formation layer LY3
Drain via plug DV
(4) Wiring layer LY4
Bit line BL, main source line MSL (not shown in FIG. 3)
Hereinafter, a cross-sectional structure of the transistor Tm1 will be described. 2 and 3, the transistor Tm2 has a symmetrical structure in the Y direction across the transistor Tm1 and the drain contact DC, and the transistor Tm2 is almost the same as the structure of the transistor Tm1. The specific structure of the transistors Tm1 and Tm2 will be described in parallel.

  FIG. 4 schematically shows a cross section of the gate electrode, particularly along the line BB in FIG. As shown in FIG. 4, a plurality of element isolation grooves 3 are formed in a p-type silicon substrate 2 as a semiconductor substrate so as to be separated from each other in the X direction. These element isolation trenches 3 are formed along the Y direction, and divide the element region (active area) Sa of the silicon substrate 2 in the X direction. As shown in FIG. 3, these element regions Sa are regions including the drain region 2a and the source region 2b of the transistors Tm1 and Tm2 and the channel region sandwiched between them, and are located immediately below the bit line BL. It is formed.

  As shown in FIG. 4, an element isolation insulating film 4 is buried in each of the plurality of element isolation trenches 3 to form an element isolation region Sb. The element isolation insulating film 4 is configured to protrude upward from the surface of the silicon substrate 2. A gate insulating film 5 is formed on the element region Sa of the silicon substrate 2 partitioned by the element isolation trench 3. The gate insulating film 5 is a film formed of a silicon oxide film having a predetermined thickness and functions as a tunnel insulating film.

  A polycrystalline silicon layer 6 is formed on the gate insulating film 5. The polycrystalline silicon layer 6 is formed by polycrystallizing amorphous silicon doped with impurities due to phosphorus, and a predetermined film so that the upper surface thereof is positioned higher than the upper surface of the element isolation insulating film 4. Consists of thickness. The polycrystalline silicon layer 6 is formed in a self-aligned manner with the side surface of the element isolation insulating film 4 in the cross section in the X direction, and is configured as the floating gate electrode FG of the transistor Tm1.

  An intergate insulating film 7 is formed continuously along the upper and upper side surfaces of the polycrystalline silicon layer 6 and the upper surface of the element isolation insulating film 4. The inter-gate insulating film 7 is composed of, for example, an ONO film (a three-layer structure film of silicon oxide film-silicon nitride film-silicon oxide film), etc., and includes a second gate insulating film, an interpoly insulating film, and a conductive interlayer insulating film. Configured as

  A polycrystalline silicon layer 8 is formed on the intergate insulating film 7. The polycrystalline silicon layer 8 is configured as a layer formed by polycrystallizing amorphous silicon doped with impurities due to phosphorus.

  A silicide film 9 made of a metal such as tungsten is formed on the polycrystalline silicon layer 8, and the control gate electrode CG is constituted by the layers 8 and 9. A silicon nitride film 10 is formed as a cap insulating film on the control gate electrode CG. In the cross section shown in FIG. 3, the silicon nitride film 10 has a so-called “convex shape” in which the upper shoulder portion 10 a serving as the upper end in the Y direction is missing.

  In this way, the laminated gate electrode MG1 is formed on the silicon substrate 2 with the laminated structure of the floating gate electrode FG, the intergate insulating film 7, the control gate electrode CG, and the silicon nitride film 10 via the gate insulating film 5. Yes. A silicon nitride film 13, a silicon oxide film 14, and a bit line BL are stacked on the stacked gate electrode MG1.

  As shown in FIG. 3, RTO (Rapid Thermal Oxidation) is provided on the side walls of the floating gate electrode FG (6), the inter-gate insulating film 7, and the control gate electrode CG (8, 9) constituting the stacked gate electrode MG1. The RTO film 11 formed by the processing is configured as a silicon oxide film and a sidewall insulating film. The RTO film 11 is provided for protecting the side wall of the stacked gate electrode MG1. The RTO film 11 is configured such that its upper end 11 a is located above the upper surface of the intergate insulating film 7 and below the upper surface of the silicide film 9.

  In the surface layer of the silicon substrate 2, on both sides of the gate electrode MG1 in the Y direction, a drain region 2a is formed on one side, and a source region 2b is formed on the other side. A silicon oxide film 12 is formed on these drain / source regions 2a and 2b with a gate insulating film 5 interposed therebetween. The silicon oxide film 12 is formed so as to cover the outer surface of the RTO film 11 along the outer surface and the upper surface of the RTO film 11 formed on the sidewall of the gate electrode MG1, and on the upper surface of the gate insulating film 5. It is formed along.

  A silicon nitride film 13 is formed on the upper and side surfaces of the silicon oxide film 12 so as to cover the silicon oxide film 12. The silicon nitride film 13 is formed along the upper surface and the outer surface of the silicon oxide film 12. The silicon nitride film 13 is also formed on the convex central upper surface of the silicon nitride film 10. Since these silicon nitride films 13 are formed in the same process, they are given the same reference numerals. A silicon oxide film 14 formed by a plasma CVD method using TEOS gas is formed on the silicon nitride film 13 formed on the convex central upper surface of the silicon nitride film 10. This silicon oxide film 14 constitutes an interlayer insulating film and an inter-plug insulating film in the upper layer region of the gate electrode MG1.

  On the drain side shown in FIG. 3, a drain contact DC is formed inside the silicon nitride film 13 between the gate electrodes MG1 and MG1. The drain contact DC is formed so as to be located immediately above the drain region 2 a of the silicon substrate 2. The drain contact DC is formed along the inner side of the silicon nitride film 13 formed along the side surface and the upper surface of the silicon oxide film 12. The drain contact DC is formed along the side surface of the silicon oxide film 14, the side surface of the silicon nitride film 13 on the silicon nitride film 10, and the upper side surface (missing surface) of the silicon nitride film 10.

  As shown in FIG. 2, these drain contacts DC are juxtaposed in the X direction. As shown in FIG. 3, these drain contacts DC are made of metal by a tungsten (W) layer 16 and a barrier metal film 17 made of titanium (Ti) or the like formed so as to cover the lower surface and side surfaces of the tungsten layer 16. Configured as a wiring layer.

  Although not shown, on the source side, a plurality of source regions 2b are arranged in parallel in the X direction with the element isolation insulating film 4 interposed therebetween. As shown in FIG. 3, a local source line LSL1 is formed on these source regions 2b. This local source line LSL1 is extended from directly above the source region 2b to the height of the upper surface of the silicon oxide film 14 along the Z direction, and is extended along the X direction which is perpendicular to the posting surface of FIG. ing.

  As shown in FIG. 2, the local source line LSL1 is connected across a plurality of source regions 2b provided in the X direction and is structurally and electrically connected to the plurality of source regions 2b. It is configured. This local source line LSL1 is formed along the X direction across the plurality of element regions Sa and element isolation regions Sb.

  A silicon oxide film 15 is formed as an interlayer insulating film on the upper surface of the silicon oxide film 14 and on the upper surface of the local source line LSL1. A via hole is formed in the silicon oxide film 15 so as to communicate with the upper surface of the drain contact DC. A barrier metal film 18 is formed along the inner surface of the via hole, and a metal layer 19 is formed inside the barrier metal film 18. As a result, a drain via plug DV is formed. A bit line BL is formed along the Y direction on the drain via plug DV.

  FIG. 5 schematically shows a perspective view of the R region (region where the drain contact DC is formed and its periphery) in FIG. In FIG. 5, the silicon nitride film 12, the silicon oxide film 13 and the like provided around the drain contact DC are not shown in order to simplify the description. A BPSG (Boro-phosphosilicate glass) film 21 is buried as an interelectrode insulating film around the drain contact DC (side of the X direction in FIG. 2). In FIG. 5, the BPSG film 21 is represented only by the reference numerals in the formation region, and is not shown. The BPSG film 21 is a film with better embedding than a silicon oxide film made of TEOS, and is formed on the side of the gate electrode MG1.

  As shown in FIG. 2, the drain contact DC has an elliptical shape that protrudes on the gate electrodes MG <b> 1 and MG <b> 2 adjacent in the Y direction and has an upper surface having a major axis in the Y direction and a minor axis in the X direction. As shown in FIG. 5, the drain contact DC is formed between the adjacent gate electrodes MG <b> 1-MG <b> 2 in the BPSG film 21, and the lower side thereof is a missing portion of the upper shoulder 10 a of the silicon nitride film 10. 3 and along the outer surface of the upper end 12a of the silicon nitride film 12 formed so as to cover the upper end 11a of the RTO film 11, as shown in FIG.

  Further, the drain contact DC is curved so that the lower side surface thereof extends from the missing portion to the upper surface of the silicon substrate 2. 2 and 5, the drain contact DC has a lower end surface configured in a rectangular frame shape, and a part in the X direction is mounted on a part of the upper surface of the upper part 4 a of the element isolation insulating film 4. It is configured to be placed. In this way, the drain contact DC is formed in a self-aligned manner.

  The manufacturing method of the said structure is demonstrated. 6 to 9 schematically show cross sections in one manufacturing process along the line BB in FIG. In addition, if there is a process necessary for forming other regions not shown, they may be added.

  As shown in FIG. 6, after ion implantation for forming a well and a channel is performed on a p-type silicon substrate 2, a gate insulating film 5 is formed by thermally oxidizing the silicon substrate 2, and low pressure CVD is performed. Amorphous silicon is deposited by the method. Since this amorphous silicon is polycrystallized by a subsequent heat treatment, it is shown as a polycrystal silicon layer 6 in the figure. Next, a silicon nitride film 23 and a silicon oxide film 24 are sequentially deposited by a low pressure CVD method.

Next, a photoresist (not shown) is applied, and the photoresist is patterned into a desired shape by a normal photo-etching method. Using the photoresist as a mask, as shown in FIG. The nitride film 23 is processed by anisotropic etching (for example, RIE (Reactive Ion Etching) method), exposed to oxygen (O ₂ ) plasma to remove the photoresist, and the polycrystalline silicon layer using the silicon oxide film 24 as a mask 6. An element isolation trench 3 is formed on the gate insulating film 5 and the silicon substrate 2.

  Next, as shown in FIG. 8, an element isolation insulating film 4 is formed from a silicon oxide film in the element isolation trench 3, and the element isolation insulating film 4 is formed by CMP (Chemical Mechanical Polish) using the silicon nitride film 23 as a stopper. Planarization is performed, and the height is adjusted by etching so that the upper surface height of the element isolation insulating film 4 is located above the upper surface of the gate insulating film 5 and below the upper surface of the polycrystalline silicon layer 6, and phosphoric acid treatment is performed. Thus, the silicon nitride film 23 is removed.

  Next, as shown in FIG. 9, an ONO film (a three-layer film of silicon oxide film-silicon nitride film-silicon oxide film) is deposited as an inter-gate insulating film 7 by CVD, and doped with impurities such as phosphorus. Amorphous silicon is deposited. This amorphous silicon is transformed into a polycrystalline silicon layer 8 by a subsequent heat treatment. Next, the upper part of the polycrystalline silicon layer 8 is silicided with a metal such as tungsten to form a silicide film 9, and a silicon nitride film 10 is further deposited thereon. Next, a silicon oxide film 25 is deposited on the silicon nitride film 10 by a CVD method.

  The silicon oxide film 25 is used as a protective film for the upper shoulder portion 10a (see FIG. 3) of the silicon nitride film 10, and is subjected to various etching processes (before the contact holes DH are formed in a self-aligning manner). For example, it is provided to protect the upper shoulder portion 10a of the silicon nitride film 10 from the later-described FIGS.

  FIG. 10 schematically shows a perspective view of the R region in FIG. 2 and its surroundings at this time. At this point, the above-described stacked structure shown in FIG. 10 is formed in the same structure along the Y direction. Next, a photoresist (not shown) is applied onto the silicon oxide film 25, the photoresist is patterned, and the silicon oxide film 25 is removed by RIE using the mask pattern of the resist as a mask. Remove the pattern.

  Next, as shown in FIG. 11, the silicon oxide film 25, the silicide film 9, the polycrystalline silicon layer 8, the intergate insulating film 7, and the polycrystalline silicon layer 6 are sequentially removed by the RIE method using the silicon oxide film 25 as a mask. Then, a groove is formed along the X direction, and the gate electrodes MG1 and MG2 are separated from each other.

12 to 21 schematically show a cross section taken along line AA of FIG. 2 in one manufacturing stage. 12 to 21 are views showing processes following the process cross section of FIG.
As shown in FIG. 12, the divided gate electrodes MG1 and MG2 are oxidized by RTO (Rapid Thermal Oxide) treatment to form an RTO film 11. This RTO process is a process for preventing abnormal oxidation of the sidewall of the silicide film 9. By forming this RTO film 11, the side walls of the gate electrodes MG1 and MG2 (particularly the side walls of the silicide film 9 and the side walls of the intergate insulating film 7) can be protected while preventing the oxidation of the side walls of the silicon nitride film 10 as much as possible. it can. The RTO film 11 formed by this RTO process is formed so that the upper end 11 a is located in the vicinity of the interface between the upper surface of the silicide film 9 and the silicon nitride film 10.

  Next, as shown in FIG. 13, a silicon oxide film 12 is formed by a low pressure CVD method using TEOS gas. The silicon oxide film 12 is formed so as to cover the gate electrodes MG1 and MG2, the RTO film 11, and the upper end 11a thereof. The silicon oxide film 12 is provided as a stopper insulating film at the time of spacer processing for LDD (Lightly Doped Drain) formation of each transistor formed on the semiconductor wafer surface. In the process explanatory diagram, the spacer insulating film is not shown because it is removed in the memory cell region M. Before and after the step shown in FIG. 13, low concentration and high concentration n-type impurity ions are implanted to form source / drain regions 2a and 2b. These impurities are activated by a subsequent heat treatment.

  Next, as shown in FIG. 14, a sacrificial layer 26 such as a resist is applied on the entire surface of the silicon substrate 2 on the silicon oxide film 12. The sacrificial layer 26 may be made of any material as long as it has a high selectivity with respect to the silicon oxide film 25 and can be peeled off later.

  Next, as shown in FIG. 15, the upper surface position of the sacrificial layer 26 is adjusted so as to be located above the upper surface of the silicide film 9 and below the upper surface of the silicon nitride film 10. This adjustment method is performed by etching such as CDE.

  Next, as shown in FIG. 16, the silicon oxide film 12 formed along the sidewall surface of the silicon nitride film 10 by hydrofluoric acid-based wet etching or the like under a condition having high selectivity with respect to the sacrificial layer 26. The upper portion 12b and the silicon oxide film 25 formed on the silicon nitride film 10 are selectively removed simultaneously.

  By removing the silicon oxide film 12 by adjusting the etching processing time, the height of the upper end 12 a of the silicon oxide film 12 is higher than the upper surface of the silicide film 9 (lower surface of the silicon nitride film 10) and from the upper surface of the silicon nitride film 10. It is adjusted so that it is located below. More specifically, the height of the upper end 12a is adjusted to a lower position below the central portion of the silicon nitride film 10 in the height direction. This height may be adjusted as appropriate within the design range as long as it is above the upper surface of the inter-gate insulating film 7 and near the lower end of the silicon nitride film 10. In the present embodiment, adjustment is made near the interface between the silicon nitride film 10 and the silicide film 9.

  In this way, the silicon oxide film 25 formed on the upper side surface of the silicon nitride film 10 can be peeled off at the same time as the silicon oxide film 25 on the silicon nitride film 10 is peeled off. Thereby, it is possible to obtain a structure in which the RTO film 11 is left along the side walls of the respective layers 6 to 9 constituting the gate electrodes MG1 and MG2.

  Next, as shown in FIG. 17, the resist constituting the sacrificial layer 26 is removed by an ashing process. Next, as shown in FIG. 18, a silicon nitride film 13 is formed by a low pressure CVD method so as to cover the upper surface and side surfaces of the silicon oxide film 12 and the side surfaces and upper surface of the silicon nitride film 10.

  Next, as shown in FIG. 19, a BPSG film 21 is formed, and then planarization is performed using the silicon nitride film 13 as a stopper by CMP, and then silicon oxide is oxidized by plasma CVD using TEOS gas. A film 14 is deposited.

  Next, a photoresist 27 is applied, and the resist 27 is patterned by a photolithography method in a region where the drain contact DC is formed. At this time, in the cross section shown in FIG. 20, the resist 27 is patterned so as to be peeled off at the end of the silicon nitride film 13 on the drain contact DC side while remaining on the center of each of the plurality of silicon nitride films 10 and 13. It is done. The opening width Rd of the resist 27 is set wider than the interval between a plurality of adjacent gate electrodes MG1-MG1 and between MG1-MG2.

  Next, using the patterned resist 27 as a mask, the silicon oxide film 14 and the BPSG film 21 are processed by anisotropic etching (RIE method) under conditions having high selectivity with respect to the silicon nitride film. At this time, the resist 27 remains on the center of each of the plurality of silicon nitride films 10 and 13, and the opening width Rd of the resist 27 is between the plurality of gate electrodes MG1-MG1 and between MG1-MG2. Therefore, when the silicon oxide film 14 and the BPSG film 21 are etched, the silicon oxide films 14 and 20 are mainly processed, but the upper shoulder portion (upper corner portion) of the silicon nitride film 10 is processed. 10a is also etched at a low speed.

  When the etching process is performed by adjusting the time with various conditions such as the film thickness of each of the films 5 to 10, 25, 13, and 14, the position of the upper end 12a of the silicon oxide film 12, and the selectivity of etching being adjusted. When the contact hole DH is formed so as to reach the upper surface of the silicon substrate 2, the upper shoulder portion 10a of the silicon nitride film 10 and the side portion of the silicon nitride film 13 shown in the cross section of FIG.

  In this case, the lower upper end 13 a of the silicon nitride film 13 is formed so as to cover the upper end 12 a of the silicon oxide film 12 and remain. That is, even if the anisotropic etching process is performed, the RTO film 11 and the silicon oxide film 12 formed along the side wall of the gate electrode MG1 can be protected. Since the silicon nitride film 13 extends vertically along the side walls of the gate electrodes MG1 and MG2 on the lower side surface of the contact hole DH, the contact hole DH extends along the outer surface of the silicon nitride film 13 with the silicon substrate. 2 and the diameter of the contact hole DH gradually decreases from the upper layer side to the upper surface of the silicon substrate 2, and the influence of the etching process does not erode the silicon oxide films 11 and 12. .

  In this manner, the contact hole DH having a so-called self-aligned upper part on the drain contact DC side having an elliptical shape in plan is formed with high reliability while maintaining the film formation state of the silicon oxide films 11 and 12. can do.

  As shown in the perspective view of FIG. 5, on the drain contact DC side, the silicon nitride film 10 and the silicon nitride film 13 are missing in the side wall portion along the other X direction other than the formation region of the contact hole DH. Never formed.

  By repeating the process of forming the hole DH on the drain contact DC side on the local source line contacts LSL1 and LSL2 side in the same manner, the same self-aligned planar straight line (upper side) is also formed on the source line contacts LSL1 and LSL2 side. It is possible to form a contact hole SH to be a groove having a substantially rectangular parallelepiped side and a lower side having a curved surface shape between the gate electrodes.

  Next, as shown in FIG. 21, a barrier metal film 17 made of titanium (Ti) is formed along the holes DH and SH by sputtering, a tungsten layer 16 is deposited by CVD, and a silicon oxide film 14 is formed. As a stopper, the tungsten layer 16 and the barrier metal film 17 are planarized by CMP. Then, the drain contact DC and the local source line contacts LSL1, LSL2 can be formed in a state of being separated from the gate electrodes MG1 and MG2.

  Next, as shown in FIG. 3, a silicon oxide film 15 is deposited by a CVD method, a resist (not shown) is patterned on the silicon oxide film 15, and the drain is drained using the patterned resist as a mask. A via hole reaching just above the contact DC is formed, a barrier metal film 18 is formed in the hole by sputtering, a metal layer 19 is deposited inside the barrier metal film 18 with tungsten or the like, and the silicon oxide film 15 is stoppered. As a result, the drain side via plug DV is formed. Next, the structure of the memory cell region M of the flash memory device 1 can be formed by forming the bit line BL structure or the like in the upper layer of the via plug DV. The subsequent steps are the same as the features of this embodiment. Since is not directly related, its description is omitted.

  According to the present embodiment, the RTO process is performed on the gate electrodes MG1 and MG2 to form the RTO film 11 along the side walls of the control gate electrode CG, the intergate insulating film 7 and the floating gate electrode FG, and cover the upper surface thereof. A silicon oxide film 12 is formed, a silicon nitride film 13 is formed so as to cover the upper and side surfaces of the gate electrodes MG1 and MG2, the upper end 11a and the side surface of the RTO film 11, and a BPSG film 21 is formed inside the silicon nitride film 13. Then, the BPSG film 21 is etched under conditions that have high selectivity with respect to the silicon nitride film.

  In this case, the RTO film 11 and the BPSG film 21 are formed of a highly selectable material during the etching process with the silicon nitride films 10 and 13, respectively, and the lower upper end 13a of the silicon nitride film 13 forms the contact hole DH. Later, the film thickness and etching conditions of each layer are adjusted in advance so as to cover the upper end 11a of the RTO film 11.

  Then, when the contact hole DH is formed, the oxide film material is not interposed between the side walls of the silicon nitride film 10 and the silicon nitride film 13, so that the influence of the etching process at the time of forming the contact hole DH is affected by the oxide film system. It can be configured not to erode to the control gate CG side through the insulating film, and the contact hole DH can be formed in a self-aligning manner.

  Accordingly, the contact hole DH can be formed in a self-aligning manner while protecting the side walls of the gate electrodes MG1 and MG2, in particular, the sidewalls of the inter-gate insulating film 7 with the RTO film 11, and then the material of the drain contact DC is formed in the contact hole DH Even if it is buried, it is possible to prevent the material of the contact DC from coming into contact with the control gate electrode CG of the gate electrodes MG1 and MG2, etc., thereby improving the reliability.

  Further, after forming the RTO film 11, a silicon oxide film 12 is formed so as to cover the gate electrodes MG1 and MG2, and a sacrificial layer 26 is formed inside the silicon oxide film 12 between the plurality of gate electrodes MG1-MG1, Etching is performed so that the upper end 12a of the silicon oxide film 12 covers the upper end 11a of the RTO film 11, and when the contact hole DH is formed, the upper end 12a of the silicon oxide film 12 covering the upper end 11a of the RTO film 11 is covered. Since the contact hole DH is formed while remaining in the gate electrode, the inter-gate insulating film 7 and the gate insulating film 5 are not exposed to the etching process, and the reliability can be improved.

  Since the upper end 12a of the silicon oxide film 12 is adjusted so as to be positioned near the interface between the silicon nitride film 10 and the silicide film 9 (near the upper surface of the control gate electrode CG), the control gate electrode CG, the gate The side walls of the inter-layer insulating film 7 and the floating gate electrode FG can be protected, and the reliability can be improved.

  Since the RTO film 11 is adjusted so that its upper end 11a is located near the interface between the silicon nitride film 10 and the silicide film 9 (near the upper surface of the control gate electrode CG), the gap between the control gate electrode CG and the gate is adjusted. The sidewalls of the insulating film 7 and the floating gate electrode FG can be protected, and the reliability can be improved.

  Before the contact hole DH is formed in a self-aligning manner (especially before the plurality of gate electrodes MG1 and MG2 are formed by dividing the layers 6 to 10), the upper shoulder portion 10a of the silicon nitride film 10 is protected. Since the silicon oxide film 25 is formed on the silicon nitride film 10, the removal process by various etchings before the contact hole DH is formed in a self-aligned manner (the dividing process of each layer 6 to 10, the dropping of the sacrificial layer 26) The upper shoulder portion 10a of the silicon nitride film 10 can be protected from the dust removal process, the upper removal process of the silicon oxide film 12, and the like. It can prevent as much as possible.

  Since the silicon oxide film 12 provided as a stopper film for forming the LDD structure and the silicon oxide film 25 for protecting the silicon nitride film 10 are formed of the same material, the upper portion 12b of the silicon oxide film 12 and silicon The oxide film 25 can be etched at the same time, and the aspect ratio when processing the contact hole DH for the drain contact DC and the contact holes SH for the local source lines LSL1 and LSL2 can be reduced.

  Since the sacrificial layer 26 remains on the lower side between the gate electrodes MG1 and MG1 and between the MG1 and MG2, the upper portion 12b of the silicon oxide film 12 is wet-etched. The gate insulating film 5 is not exposed to the etching process, and the gate insulating film can be configured with high reliability.

  The RTO film 11 is formed along the side walls of the plurality of floating gate electrodes FG and the inter-gate insulating film 7 such that the upper end 11 a is located near the upper surface of the control gate electrode CG, and the drain contact DC is formed in the BPSG film 21. The lower side surface of the silicon nitride film 10 is curved in a self-aligned manner along the missing surface of the upper shoulder 10a of the silicon nitride film 10 and the outer surface of the silicon nitride film 13 covering the upper end 12a of the silicon oxide film 12. Therefore, the reliability of the RTO film 11 can be maintained, and the side walls of the gate electrodes MG1 and MG2 can be appropriately protected.

  As shown in FIG. 3, since only the RTO film 11, the silicon oxide film 12, and the silicon nitride film 13 are formed on the side walls of the gate electrodes MG1 and MG2, the drain is compared with, for example, the structure of a single silicon nitride film. Electrical interference with the contact DC is reduced, and the write / erase characteristics are improved.

(Second Embodiment)
FIG. 22 shows a second embodiment of the present invention, which is different from the previous embodiment in the set positions of the upper end 11a of the RTO film 11 and the upper end 12a of the silicon oxide film 12. The same parts as those of the above-described embodiment are denoted by the same reference numerals and description thereof is omitted, and only different parts will be described below.

FIG. 22 schematically shows a Y-direction cross-section that replaces FIG.
In the above-described embodiment, the upper end 11a of the RTO film 11 and the upper end 12a of the silicon oxide film 12 are set near the interface between the control gate electrode CG and the silicon nitride film 10, but instead of this, FIG. As shown, the upper end 11 a of the RTO film 11 and the upper end 12 a of the silicon oxide film 12 may be formed slightly above the upper surface of the inter-gate insulating film 7. In other words, the silicon oxide film 12 is formed so as to cover only the lower part which becomes a part of the side wall of the control gate electrode CG. In the case of forming this structure, the upper surface position of the sacrificial layer 26 is preferably adjusted to the vicinity of the interface position between the polycrystalline silicon layer 8 and the silicide film 9 at the time of the step shown in FIG. Even in such an embodiment, substantially the same operational effects as in the above-described embodiment can be obtained.

  As shown in the first and second embodiments, the upper end 11a of the RTO film 11 and the upper end 12a of the silicon oxide film 12 are respectively above the upper surface of the inter-gate insulating film 7 and of the control gate electrode CG. It may be adjusted to any position as long as it is formed so as to be positioned below the upper surface.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the above-described embodiment, the P-type silicon substrate 2 in which the well is appropriately formed on the surface layer is applied, and the structure on the silicon substrate 2 is mainly described. However, the P-well is formed on the surface layer of the N-type silicon substrate 2. The present invention may be applied to the structure of the region, and in the present invention, a semiconductor substrate of another material may be applied.

Although the embodiment has been described in which the contact hole DH is formed such that the upper end thereof is planarly elliptical, the present invention can be applied to a case where a contact hole whose upper end is planarly shaped is formed instead.
Although the ONO film is applied as the inter-gate insulating film 7, a stacked film of an oxide film and a nitride film having a different structure from the ONO film, such as an ONON film, or a high dielectric film such as alumina may be applied.
The present invention can also be applied to a T-shaped structure in which the polycrystalline silicon layer 6 (floating gate electrode FG) projects on the element isolation insulating film 4 adjacent in the X direction.

The silicide film 9 made of tungsten is applied as the lower resistance metal layer on the control gate electrode CG. However, in the present invention, a silicide layer made of another metal may be applied, and the control gate electrode CG may be a poly gate. .
The silicon nitride film 13 may be formed directly on the RTO film 11 without forming the silicon oxide film 12.
Although the present invention is applied to a NOR type flash memory device, the present invention may be applied to a NAND type flash memory device or another nonvolatile semiconductor memory device such as an EEPROM.

  Even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the object described in the column of the problem to be solved by the invention can be achieved, and is described in the column of the effect of the invention. If the effect is obtained, the configuration requirement from which this configuration requirement is deleted can be applied as an invention.

FIG. 1 is an equivalent circuit diagram of an electrical configuration of a cell array according to the first embodiment of the present invention. Plan view schematically FIG. 2 is a vertical cross-sectional view schematically shown along line AA in FIG. FIG. 2 is a vertical cross-sectional view schematically shown along line BB in FIG. The perspective view which shows typically about R area | region of FIG. FIG. 4 equivalent view schematically showing one manufacturing stage (part 1) FIG. 4 equivalent view schematically showing one manufacturing stage (No. 2) FIG. 4 equivalent view schematically showing one manufacturing stage (No. 3) FIG. 4 equivalent view schematically showing one manufacturing stage (No. 4) FIG. 5 equivalent view schematically showing one manufacturing stage (part 1) FIG. 5 equivalent view schematically showing one manufacturing stage (part 2) FIG. 3 equivalent view schematically showing one manufacturing stage (part 1) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 2) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 3) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 4) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 5) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 6) FIG. 3 equivalent view (No. 7) schematically showing one manufacturing stage FIG. 3 equivalent view schematically showing one manufacturing stage (No. 8) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 9) FIG. 3 equivalent view schematically showing one manufacturing stage (No. 10) FIG. 3 equivalent view schematically showing the second embodiment of the present invention.

Explanation of symbols

  In the drawings, 1 is a flash memory device (nonvolatile semiconductor memory device), 5 is a gate insulating film (first gate insulating film), 6 is a polycrystalline silicon layer (floating gate electrode), and 7 is an inter-gate insulating film (first gate insulating film). 2 is a silicon nitride film (cap insulating film), 11 is an RTO film (first insulating film, sidewall insulating film), 13 is a silicon nitride film (second insulating film, barrier film), and 21 is BPSG film (interelectrode insulating film), 26 is a sacrificial layer, DH is a drain contact hole (contact hole), SH is a source contact hole (contact hole), DC is a drain contact (contact plug), and LSL1 and LSL2 are source line contacts , FG are floating gate electrodes, CG is a control gate electrode, and MG1 and MG2 are gate electrodes (stacked gate electrodes).

Claims (5)

Forming a first gate insulating film on the semiconductor substrate;
Forming a plurality of stacked gate electrodes on the first gate insulating film by sequentially stacking a plurality of floating gate electrodes, a plurality of second gate insulating films, a plurality of control gate electrodes, and a plurality of cap insulating films; ,
The plurality of stacked gate electrodes are subjected to RTO (Rapid Thermal Oxide) treatment to form a first insulating film made of the RTO along the side walls of the plurality of control gate electrodes, the plurality of floating gate electrodes, and the plurality of second gate insulating films. Forming, and
Forming a second insulating film of the same kind of material as the cap insulating film so as to cover the first insulating film and the plurality of stacked gate electrodes, and enabling high selection during etching with the first insulating film Forming the second insulating film with a suitable material;
Forming an inter-electrode insulating film with a highly selectable material at the time of etching between the cap insulating film and the cap insulating film located inside the first and second insulating films;
The inter-electrode insulating film is etched under a condition having high selectivity with respect to the cap insulating film, so that the second insulating film covering the stacked gate electrode covers the upper end of the first insulating film. Forming a contact hole in a self-aligning manner while leaving the second insulating film;
Forming a contact plug in the contact hole. A method for manufacturing a nonvolatile semiconductor memory device.   2. The nonvolatile memory according to claim 1, wherein the first insulating film is formed so that an upper end thereof is located above an upper surface of the second gate insulating film and below an upper surface of the control gate electrode. For manufacturing a conductive semiconductor memory device. Between the step of forming the first insulating film and the step of forming the second insulating film, the first insulating film formed along the sidewalls of the stacked gate electrode and the stacked gate electrode is covered. Forming a third insulating film of the same material as the first insulating film;
Forming a sacrificial layer inside a third insulating film between the plurality of stacked gate electrodes;
Etching the upper part of the third insulating film so that the upper end of the third insulating film covers the upper end of the first insulating film using the sacrificial layer as a mask,
3. The step of forming a contact hole in a self-aligning manner is characterized in that the second insulating film covering the stacked gate electrode is formed while remaining so as to cover the upper end of the third insulating film. The manufacturing method of the non-volatile semiconductor memory device of description. A semiconductor substrate;
A first gate insulating film formed on the semiconductor substrate; a plurality of floating gate electrodes formed on the first gate insulating film; and a plurality of first gate electrodes formed on the plurality of floating gate electrodes, respectively. 2 gate insulating films, a plurality of control gate electrodes formed on the plurality of second gate insulating films, respectively, and upper shoulder portions are missing in a partial cross section on the plurality of control gate electrodes. A plurality of laminated gate electrodes composed of a plurality of cap insulating films formed;
A sidewall insulating film comprising a plurality of floating gate electrodes constituting the plurality of stacked gate electrodes and an RTO film formed along the sidewalls of the plurality of second gate insulating films, wherein the upper end height is the control gate electrode A sidewall insulating film formed below and near the upper surface of the control gate electrode and above the lower surface of the control gate electrode;
A barrier film formed between sidewall insulating films of the plurality of stacked gate electrodes and formed to cover the sidewall insulating film;
A contact plug formed inside a barrier film between sidewall insulating films of the plurality of stacked gate electrodes, the lower surface of which is formed along the missing surface of the cap insulating film and the outer surface of the barrier film A non-volatile semiconductor memory device comprising: a contact plug curved in a self-aligning manner up to the upper surface of the substrate. The barrier film is composed of a silicon nitride film,
5. The nonvolatile semiconductor memory device according to claim 4, wherein only the side wall insulating film and the barrier film are formed between the side walls of the contact plug and the plurality of stacked gate electrodes.

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