JP2009225164A - Decoding device and television receiver having decoding device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain a high performance decoding device of data, which performs high speed processing and has high error correction capability, and also to provide a television receiver having the decoding device. <P>SOLUTION: The decoding device includes: an LLR generator 21; a hard decision value generator 22 which generates a hard decision value based on LLR; a BCH parity check unit 23 which performs parity check of a BCH code based on the hard decision value; an LLR update unit 24 which updates log likelihood ratio according to a result of the parity check of the BCH parity check unit 23; an LDPC decoder 25 which updates the log likelihood ratio from the LLR update unit 24 by decoding processing of an LDPC code; an LPDC parity check unit 26 which generates the hard decision value based on the log likelihood ratio from the LDPC decoder 25 and performs the parity check; and a BCH decoder 27 which performs decoding processing of the BCH code based on the hard decision value generated by the LDPC code parity check unit 26. The television receiver has the decoding device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a concatenated code decoding apparatus and a television receiver, and in particular, uses a first error correction code capable of hard decision decoding as an outer code, and a second error correction code capable of soft decision decoding as an inner code. The present invention relates to a decoding apparatus for concatenated codes used as a television receiver and a television receiver having the decoding apparatus.

  For the high-speed data transmission and reception in the field of communication such as mobile communication and WLAN, the field of broadcasting such as terrestrial or satellite digital broadcasting, and the high density recording in the field of storage such as semiconductor memory, development related to error correction codes of digital data has been active. Has been done.

  Among correction codes, a low density parity check code (hereinafter referred to as “LDPC code”), which is an encoding method that has been known for a long time, has attracted particular attention in recent years. The LDPC code was first proposed in 1963 by R. G. Gallager. Thereafter, as the code length is increased, excellent performance approaching the Shannon limit given by the so-called Shannon's channel coding theorem, which is the theoretical limit of code performance, has been reported.

  In addition, since the LDPC code has the property that the minimum distance is proportional to the code length, the characteristic is that the block error probability characteristic is good, and further, the so-called error floor phenomenon observed in the decoding characteristic such as turbo code is observed. It is also known as an advantage that it hardly occurs.

  Here, an algebraic error correction method such as a BCH code and a Reed-Solomon (RS) code, which has been widely used in the past, increases the parity part or increases the bit error rate that can be corrected. Although there are problems such as an increase in the number of correction circuits, it has been mathematically proved that an error of a predetermined number or less can be reliably corrected.

  On the other hand, LDPC codes and turbo codes, which are error correction methods based on probability-based iterative calculation, are difficult to clearly define the correction capability itself, and even for ECC frames that do not have so many bit errors. There is a rare occurrence of an inability to correct, that is, the appearance of an error frame. Thus, the rate at which error correction fails is called the frame error rate. In the encoding and decoding of data by the error correction method by iterative calculation based on probability, it is possible to reduce the frame error rate, but the frame error rate is zero and the frame error rate is mathematically proved It is very difficult.

  As described above, the frame error rate of the LDPC code, which is an error correction method based on probability-based iterative calculation, is difficult to predict analytically. Therefore, the confirmation is mainly performed by computer simulation or actual machine evaluation. Yes. However, for example, even in a normal application, an LDPC code may require a frame error rate of 10 minus 10 or less, and it takes an enormous amount of time to obtain the frame error rate by computer simulation. The design of the code and its verification has been very difficult.

  In order to solve the problem of the LDPC code, an error correction method using a concatenated code using an LDPC code and a BCH code is known. For example, based on the provisions of Article 38 of the Radio Law (Act No. 131 of 1951), the standard method of transmission related to digital broadcasting among standard television broadcasting, etc. An error correction method using a concatenated code using a BCH code as an outer code and an LDPC code as an inner code is defined as an error correction method for narrowband transmission digital broadcasting (related to Article 49, paragraph 3).

  However, as will be described later, in the iterative decoding method of the LDPC code in the decoding apparatus, the iteration process is performed repeatedly, and it is necessary to perform the iteration process many times before the parity check becomes OK. That is, the processing time of the decoding process becomes long, and the power consumption of the decoding device may increase.

  In particular, in a television receiver that receives digital television broadcasts, the time that can be used for processing one frame is fixed at, for example, 1/60 second or less, and therefore decoding processing is included within the predetermined time. When the signal processing is not completed, a so-called frame drop occurs, and the display image may be deteriorated.

Japanese Patent Laid-Open No. 2006-33720 discloses a decoding apparatus having a correction unit that corrects a log likelihood ratio in accordance with an error detection result in a turbo decoding apparatus that interleaves.
JP 2006-33720 A Standard method of transmission related to digital broadcasting among standard television broadcasting etc. based on the provisions of Article 38 of the Radio Law (Act No. 131 of 1951), Schedule No. 39

  The present invention has been made in view of the above circumstances, and the present invention realizes a high-performance decoding device capable of high-speed processing and high error correction capability, and a television receiver having the decoding device. With the goal.

  The decoding device according to one aspect of the present invention uses a first error correction code for hard decision decoding as an outer code, a second error correction code for soft decision decoding as an inner code, and 1 in the inner code. A decoding apparatus for decoding data encoded by a concatenated code including one or more outer codes, a log likelihood ratio generator that generates an initial value of a log likelihood ratio from the data, and a log likelihood A hard decision value generator that generates a hard decision value based on the ratio, a first error correction code parity checker that performs a parity check of the first error correction code based on the hard decision value, and a first error The log likelihood ratio updater that updates the log likelihood ratio according to the result of the parity check of the correction code parity checker, and the log likelihood from the log likelihood ratio updater by decoding the second error correction code A second error correction code decoder for updating the ratio; Based on the log likelihood ratio from the error correction code decoder, a second error correction code parity checker that generates a hard decision value and performs a parity check, and a second error correction code parity checker are generated. A decoding apparatus comprising: a first error correction code decoder that performs decoding processing of a first error correction code based on a hard decision value.

  The television receiver of one embodiment of the present invention uses a first error correction code for hard decision decoding as an outer code, a second error correction code for soft decision decoding as an inner code, and an inner code. A decoding apparatus that performs decoding processing of data encoded by a concatenated code including one or more outer codes, and a log likelihood ratio generator that generates an initial value of the log likelihood ratio from the data; A hard decision value generator that generates a hard decision value based on the log likelihood ratio, a first error correction code parity checker that performs a parity check of the first error correction code based on the hard decision value, and From the log likelihood ratio updater that updates the log likelihood ratio according to the result of the parity check of the first error correction code parity checker, and the log likelihood ratio updater by decoding the second error correction code Second error correction to update the log likelihood ratio of A second error correction code parity checker for generating a hard decision value and performing a parity check based on the log likelihood ratio from the signal decoder and the second error correction code decoder; and a second error correction The television receiver includes a decoding device including a first error correction code decoder that performs a decoding process on the first error correction code based on the hard decision value generated by the code parity checker.

  According to the present invention, it is possible to realize a high-performance decoding device capable of high-speed processing and high error correction capability and a television receiver having the decoding device.

Embodiments of the present invention will be described below with reference to the drawings.
<About LDPC code>
First, iterative decoding in an LDPC code will be briefly described with reference to FIGS. 1, 2, and 3. FIG. 1 is a diagram for explaining iterative decoding in an LDPC code. FIG. 1 (A) shows an example of a parity check matrix H, and FIG. 1 (B) shows a Tanner corresponding to the parity check matrix H. FIG. 2 is a graph G, and FIG. 2 is a diagram showing a part of the Tanner graph G.

  As shown in FIG. 1, iterative decoding in an LDPC code is easy to understand by using a Tanner graph that is a bipartite graph corresponding to a parity check matrix H. In FIG. 1, the nodes of the Tanner graph G are classified into two types, variable nodes and check nodes. The variable node corresponds to the column of the matrix H, and the check node corresponds to the row of the matrix H. A Tanner graph G is constructed by connecting the nodes “1” with edges in the elements of the matrix H.

  The decoding process of the LDPC code is executed by repetitively updating the log likelihood ratio information assigned to the edges of the Tanner graph at the nodes. The log likelihood ratio information includes log likelihood ratio information from the check node to the variable node (hereinafter referred to as symbol “α”) and log likelihood ratio information from the variable node to the check node (hereinafter referred to as “ There are two types of ")". In the decoding process of the LDPC code, a unit in which the variable node process and the check node process are executed once is referred to as one iteration process, and the decoding process is performed by repeating the iteration process.

  As the log likelihood ratio information update algorithm in the variable node and the check node, that is, the message transmission algorithm, methods such as the Sum-Product algorithm and the Min-Sum algorithm are known. Here, a Min-Sum algorithm with a relatively small amount of calculation will be described as a log likelihood ratio information update algorithm.

  First, variable node processing will be described with reference to FIGS. 2 (A) and 2 (B). 2A and 2B are diagrams in which portions related to the variable node 3 are extracted from the Tanner graph of FIG.

  A log likelihood ratio (Log Likelihood Ratio: hereinafter referred to as “LLR”, represented by the symbol “λ”) when receiving a codeword bit corresponding to a certain variable node, for example, variable node 3, is represented by λ (3 ), And log likelihood ratio information from the check node to the variable node 3 is α (j, 3). Here, j indicates the check node number connected to the variable node 3, and corresponds to “1” and “2” in the Tanner graph G shown in FIG.

  The variable node 3 performs the calculation represented by the following (formula 1) on the check node of the edge corresponding to α (1, 3), that is, the check node 1.

β (3,1) = λ (3) + α (2,3) (Formula 1)
Similarly, the calculation represented by the following (Equation 2) is performed on the check node with the node number j.

β (3, j) = λ (3) + Σα (k, 3) (Formula 2)
Here, Σ means the sum other than k = j among the check nodes connected to the variable node 3.

  The above calculation is performed for all the variable nodes, and β (i, j) represented by the following (formula 3) is calculated. Here, assuming that the code length is N and the node number is i, i = 1 to N. Further, Σ means a sum other than k = j among the check nodes connected to the variable node i.

β (i, j) = λ (i) + Σα (k, i) (Formula 3)
Next, the check node process will be described with reference to FIGS. 2C and 2D. FIGS. 2C and 2D are diagrams in which portions related to the check node 1 are extracted from the Tanner graph of FIG.
When log likelihood ratio information, which is a message to a certain check node, for example, check node 1, is β (k, 1), this check node is an edge variable node corresponding to β (1, 1). Α (1, 1) represented by the following (formula 4) is calculated for the variable node 1.

α (1,1) = sign (Πβ (m, 1)) × min (| β (m, 1) |) (Formula 4)
However, k is a variable node number connected to the check node 1, and is “1”, “2”, and “3” in the example of FIG. Then, m is selected from “2” to “3”. Here, sign (Πβ (m, 1)) means a sign (“+1” or “−1”) as a result of multiplying β (m, 1) from m = 2 to 3. | Β (m, 1) | is an absolute value of β (m, 1), and min is a function for selecting a minimum value from a plurality of | β (m, 1) |.

  Similarly, α (1, i) is calculated using the following (Formula 5).

α (1, i) = sign (Πβ (m, 1)) × min {| β (m, 1) |} (Formula 5)
However, i is a variable node number connected to the check node 1, and is “1”, “2”, and “3” in the example of the Tanner graph of FIG. Further, m is a variable node connected to the check node 1 except m = i.

  The above calculation is performed for all check nodes, and α (j, i) is calculated using the following (formula 6).

α (j, i) = sign (Πβ (m, j)) × min (| β (m, j) |) (Expression 6)
However, m is a variable node connected to the check node j, except m = i.

  In the iterative decoding, the posterior probability Pb (i) is obtained by the following (Equation 7) for each iteration process in which the variable node process and the check node process shown above are executed once.

Pb (i) = λ (i) + Σα (k, i) (Expression 7)
Here, i = 1 to N, and N is a code length. Σ is all the sums connected to the variable node i.

  Based on the posterior probability value Pb, bit determination, that is, whether the bit is “0” or “1” is determined. Then, this hard decision result is used to perform a parity check of the LDPC code, and when it is confirmed that there is no error, the iterative process is terminated. The above is the iterative decoding method of the LDPC code.

  Hereinafter, the fact that no error is detected as a result of the parity check is referred to as “parity check OK”, and the fact that an error is detected as the result of the parity check is referred to as “parity check NG”. “Parity check” means “error detection” in decoding, and “decoding including error correction” or “error correction” is simply referred to as “decoding”.

  Here, FIG. 3 is a block diagram showing a configuration of a known LDPC code decoding device 1P. As illustrated in FIG. 3, the decoding device 1 </ b> P includes an LLR generator 31, an LDPC decoder 32, an LDPC parity checker 33, and a hard decision decoder 34.

<First Embodiment>
A television receiver 10 having the decoding device 1 according to the first embodiment of the present invention will be described with reference to FIGS. 4, 5, and 6. FIG. 4 is a block diagram showing a schematic configuration of the television receiver 10 having the decoding device 10 of the present embodiment, and FIG. 5 is an explanatory diagram for explaining the encoding process of the transmission device. 6 is an explanatory diagram for explaining a concatenated code. In the following, an OFDM (orthogonal frequency division multiplexing) method used in a digital terrestrial broadcasting system will be described as an example of a modulation method.

  As shown in FIG. 4, the television receiver 10 having the error decoding device 1 of the present embodiment transmits a radio wave (transmission path) transmitted from the transmission device 5 via the transmission antenna 6 via the reception antenna 11. Receive. The transmission device 5 is, for example, a broadcasting station facility, and the transmission antenna corresponds to Tokyo Tower or the like. The transmission data transmitted by the transmission device 5 is encoded by a predetermined encoding device 7 (see FIG. 5).

  The television receiver 10 converts a signal received by the receiving unit 12 via the receiving antenna 11 into a digital signal by the A / D conversion device 13, and then removes the guard interval in the signal by the GI removal device 14. . Then, the data subjected to the fast Fourier transform by the FFT 15 is obtained by dividing the received data distorted in the transmission line by the transmission line estimation value by the transmission line equalizer 16 which is an equalizer corresponding to indoor propagation characteristics such as frequency selective fading. Compensate with. The received data subjected to compensation processing is subjected to error correction decoding processing (hereinafter referred to as “decoding processing”) in the decoding device 1, and is output to the monitor 18 and the speaker 19 via the post-processing device 17. .

  As shown in FIG. 5, in encoding apparatus 7 of transmitting apparatus 5 of the present embodiment, LDPC code is performed after BCH encoding processing by BCH encoder 7A is performed on data to be transmitted. An LDPC encoding process is performed by the encoder 7B. That is, the reception information decoded by the decoding device 1 is encoded by a concatenated code having an LDPC code as an inner code and a BCH code as an outer code.

  Furthermore, as shown in FIG. 6, the concatenated code of the present embodiment has a configuration in which four BCH codes are included in the information part of the LDPC code. That is, when the code length of the LDPC code is N, the parity length of the LDPC code is M, the code length of the BCH code is Nb, and the parity length of the BCH code is Mb, a relationship of NM = 4Nb is established.

  Next, the configuration and operation of decoding apparatus 1 according to the present embodiment will be described with reference to FIGS. FIG. 7 is a configuration diagram for explaining the configuration of the decoding device 1, and FIG. 8 is an explanatory diagram for explaining the log likelihood ratio.

As illustrated in FIG. 7, the decoding device 1 according to the present embodiment includes a log likelihood ratio (hereinafter, also referred to as “LLR” and represented by the symbol “λ”) generator 21 and a hard decision value generator 22. A BCH parity check unit 23, an LLR update unit 24, an LDPC decoder 25, an LDPC parity check unit 26, and a BCH decoder 27. The data modulation method of the received data is BPSK (Binary Phase Shift Keying).
The LLR generator 21 shown in FIG. 7 generates an LLR initial value for each bit from the received data.
Here, the log likelihood ratio (LLR) will be described with reference to FIG. As shown in FIG. 8, when the mapping point corresponding to the bit “0” is “D” and the mapping point corresponding to the bit “1” is “−D” on the number line, the received data Is the position “X”. The log likelihood ratio λ at this time is calculated by the LLR generator 21 using the following (Equation 8).

λ = − (D−X) ² + (− D−X) ² (Expression 8)
However, an upper limit value, Mx, is provided for the absolute value of the log likelihood ratio λ. That is, if | λ |> = Mx, the clipping process is performed to | λ | = Mx.

  Here, as is clear from (Equation 8), the absolute value | λ | of the log-likelihood ratio λ is referred to as the reliability, and the reliability is higher as the reliability is closer to Mx. The closer to 0, the lower the reliability. The LLR generator 21 calculates (Equation 8) for all N bits of the LDPC code to obtain λ (j): j = 1 to N. λ (j) is the LLR initial value calculated from the received data.

Next, the hard decision value generator 22 creates a hard decision value from the LLR initial value λ (j) generated by the LLR generator 21. Here, the hard decision value generator 22 determines that the bit is “1” when λ (j) <0, and determines that the bit is “0” when λ (j)> = 0.
Let the hard decision value generated by the hard decision value generator 22 be Hd (j): j = 1 to N.

  Then, the BCH parity check unit 23 performs error detection of the BCH code, that is, parity check, using the hard decision value Hd. As described above, in the present embodiment, since four BCH codes are included in one LDPC code, the BCH parity check unit 23 performs parity check four times.

  The BCH parity checker 23 first performs a parity check of the first BCH code. Here, the hard decision values corresponding to the first BCH code are Hd (k): k = (M + 1) to (M + Nb). The BCH parity checker 23 performs an algebraic decoding process of the first BCH code using the hard decision value Hd. Further, the BCH parity checker 23 sequentially performs parity checks on the second BCH code, the third BCH code, and the fourth BCH code.

  In the algebraic decoding of the BCH code, an error position polynomial is output as a decoding result. The error position polynomial only detects whether an error exists, in other words, the presence or absence of an error. Then, by solving the error position polynomial, it is possible to specify up to the error bit position in the BCH code and correct the error. If there is no error, the output error position polynomial is “0”.

  The BCH parity checker 23 of the decoding apparatus 1 attempts algebraic decoding on the hard decision value Hd (j) and detects only whether an error exists. That is, if the output error position polynomial is “0”, the BCH parity check unit 23 detects that the parity check is OK, that is, there is no error. On the other hand, if the error position polynomial is not “0”, the BCH parity check unit 23 detects that the parity check result is NG, that is, the presence of an error.

Then, the BCH parity checker 23 notifies the LLR updater 24 of Pr (j): j = 1 to 4 as a result of the parity check for each of the four BCH codes.
Here, the parity check result Pr is “0” for the parity check OK and “1” for the parity check NG.

  The LLR updater 24 updates the LLR initial value λ (j) generated by the LLR generator 21 according to the parity check result Pr (j) from the BCH parity checker 23.

  The LLR update method performed by the LLR updater 24 is a parity check OK, that is, when Pr (j) = 0, the log likelihood ratio λ of the corresponding bit is the maximum value of λ, sign (λ) Update to xMx. Here, sign (λ) means the sign of λ, “+1” or “−1”. On the other hand, the LLR updater 24 keeps the log likelihood ratio at λ for the bit corresponding to the parity check NG and does not update it.

  Here, the update of the LLR will be described in more detail with reference to FIGS. 9 and 10. FIG. 9 is an explanatory diagram for explaining a bit in which the LLR is updated in the concatenated code, and FIG. 10 is a schematic diagram for explaining a bit in which the LLR is updated in the concatenated code.

  9 and 10, in the concatenated code of the present embodiment configured to include four BCH codes in the information part of the LDPC code, only the third BCH code is checked for parity, that is, Pr (3) = 0, The case where Pr (1) = Pr (2) = Pr (4) = 1 is shown.

  In this case, as shown in FIG. 9, the position of the log likelihood ratio λ (j) to be updated is j = (M + 1 + 2Nb) to (M + 3Nb), and λ is updated to sign (λ) × Mx. Is done.

  This will be described with reference to the schematic diagram of FIG. FIG. 10A shows the absolute value of the initial value of the log likelihood ratio λ for each bit of the LDPC code created by the LLR generator 21, in other words, the initial value of the reliability. FIG. 10 also shows an LDPC code so that the bit position corresponding to the BCH code can be understood. Next, FIG. 10B shows the absolute value of the LLR after being updated in accordance with the parity result of the BCH code in the LLR updater 24. That is, in FIG. 10B, the absolute value of the LLR of the bit corresponding to the parity check OK by the BCH parity checker 23 is updated to the maximum value Mx.

  Then, the LDPC decoder 25 uses the log likelihood ratio from the LLR updater 24 to perform the above-described iterative decoding process including variable node processing and check node processing. The LDPC decoder 25 first performs variable node processing using the log likelihood ratio λ (j): j = 1 to N notified from the LLR updater 24 to generate log likelihood ratio information β. . However, the initial value of α in the first iteration process is “0”. In the second and subsequent iteration processes, the log likelihood ratio information α calculated in the previous iteration process is used.

  That is, log likelihood ratio information, β (j, k) at the time of the first iteration processing is λ (j). Here, k is a check node number connected to the variable node j.

The log likelihood ratio information β (j, k) at the second and subsequent iterations is λ (j) + Σα (m, j). Here, Σ is a sum other than m = k among the check nodes connected to the variable node j.

  Next, the LDPC decoder 25 generates log-likelihood ratio information α by performing check node processing. This uses the log likelihood ratio information β to perform the following calculation. However, here, a case where the Min-Sum algorithm is used for the check node processing is shown. At this time, α is expressed by (Equation 9).

α (j, k) = sign (Πβ (m, j)) × min (| β (m, j) |) (Equation 9)
Here, m is assumed to be other than m = k among the variable nodes connected to the check node j.

  Further, the LDPC decoder 25 calculates a posterior probability value Pb. Pb (j) for each bit is λ (j) + Σα (k, j). Here, j = 1 to N, and Σ is the sum of all connected to the variable node j.

  Then, the LDPC parity check unit 26 generates a hard decision value using the posterior probability value Pb that is the log likelihood ratio output from the LDPC decoder 25. An LDPC hard decision value generator (not shown) creates a hard decision value from Pb (j). This is determined as Hd = 1 when Pb (j) <0, and Hd = 0 when Pb (j)> = 0. The hard decision result is Hd (j): j = 1 to N.

Then, the LDPC parity check unit 26 performs a parity check of the LDPC code based on the hard decision value.
If the parity check is OK, the decoding device 1 outputs a hard decision value corresponding to the information part of the LDPC, Hd (j): j = (M + 1) to N, to the subsequent processing device 17.

When the parity check of the LDPC code is NG, Hd (j): j = 1 to N is notified to the BCH parity checker 23 for the next iteration process.
Even if the predetermined maximum number of iterations elapses, if the parity check of the LDPC code is NG, decoding processing by the BCH decoder 27 is performed. In many cases, some error portions have already been corrected by the decoding process of the LDPC code. For this reason, if the number of error bits after the decoding process of the LDPC code is less than or equal to the error correction capability of the BCH code, the BCH decoder 27 can correct the error bits correctly.

  Next, the decoding algorithm of the decoding device 1 will be described again using FIG. FIG. 11 is a flowchart for explaining the flow of the decoding process of the decoding device 1. Note that the maximum number of iterations is MItr.

  Hereinafter, the flow of the decoding process will be described with reference to the flowchart of FIG.

<Step S11>
First, the maximum number of iterations MItr is set, and a parameter indicating the number of iterations, Itr, is set to “0”. It is not necessary to set the maximum number of iterations every time, and a preset value may be used.

<Step S12>
The LLR generator 21 generates an initial value λ (j) of the log likelihood ratio λ of each bit from the received data.

<Step S13>
The hard decision value generator 22 creates a hard decision value from LLRλ (j).

<Step S14>
The BCH parity check unit 23 performs error detection, that is, parity check of each of the four BCH codes using the hard decision value Hd.

<Step S15, Step S16>
If there is a parity check OK BCH code among the four BCH codes, the LLR updater 24 updates the log likelihood ratio of the bit corresponding to the BCH code to the maximum value in step S16. On the other hand, the LLR updater 24 keeps the log likelihood ratio of bits corresponding to the BCH code of the parity check NG as the initial value λ and does not update it.

<Step S17>
The LDPC decoder 25 performs the first LDPC decoding using the log likelihood ratio updated by the LLR updater <step S18>.
The LDPC parity checker 26 performs a parity check, and at the same time, increments the value of Itr by “1” and increments it by 1.

<Step S19>
If the parity check of the LDPC parity checker 26 is OK (Yes), the data is output to the post-processing device 17 in step S20, and the decoding device 1 ends the processing.

  When the parity check of the LDPC parity checker 26 is NG (No), the decoding device 1 performs the processing from step S21.

<Step S21>
The decoding device 1 checks the number of iteration processes and the value of Itr.

<Step S22>
The decoding device 1 repeats the iteration process from step S13 when the value of the iteration process count and Itr is smaller than the maximum iteration count MItr.

  When the number of iteration processes and the value of Itr are larger than the maximum number of iterations MItr, the decoding device 1 starts the process of step S23 without performing any further iteration process.

<Step S23>
If an error remains after the iteration process for the maximum number of iterations, the decoding apparatus 1 performs a decoding process by the BCH decoder 27. That is, if the number of error bits after the LDPC code decoding process is less than or equal to the error correction capability of the BCH code, the BCH decoder 27 can correct the error bits correctly. The decrypted data is output to the post-processing device 17 in step S20, and the decrypting device 1 ends the process.

  As described above, the decoding apparatus 1 uses the BCH code, which is the first error correction code for hard decision decoding, as the outer code, and the LDPC code, which is the second error correction code for soft decision decoding, as the inner code. A decoding apparatus for decoding data encoded by a concatenated code including one or more outer codes in the inner code, and generating an initial value of the log likelihood ratio from the data A likelihood ratio (LLR) generator 21, a hard decision value generator 22 that generates a hard decision value based on the log likelihood ratio, and a first error correction code parity check based on the hard decision value. A log likelihood ratio (LLR) update that updates the log likelihood ratio according to the result of the parity check of the first error correction code parity checker and the BCH parity checker 23 that is an error correction code parity checker of 1 Container 24 and second An LDPC decoder 25 that is a second error correction code decoder that updates the log likelihood ratio from the log likelihood ratio updater by decoding the error correction code, and a log likelihood from the second error correction code decoder. Based on the degree ratio, a hard decision value is generated and a hard decision value generated by the LDPC parity check unit 26, which is a second error correction code parity checker for performing parity check, and the second error correction code parity check unit. And a BCH decoder 27 which is a first error correction code decoder for performing a decoding process of the first error correction code.

  The decoding device 1 updates the log likelihood ratio of the corresponding bit based on the result of parity check of the BCH code that is the inner code. For this reason, since the decoding apparatus 1 can accelerate the update of the log likelihood ratio in LDPC decoding, that is, can reduce the number of iterations of the iteration process until decoding is completed, the decoding apparatus 1 can perform high-speed processing. In addition to being possible, this is a high-performance decoding device with higher error correction capability due to decoding processing by the BCH decoder 27. Further, since the decoding device 1 can reduce the number of iterations of the iteration process, power saving can be realized.

  In addition, since the television receiver 10 has the decoding device 1, the processing time of the decoding process can be completed within a predetermined time, and since it has the high-performance decoding device 1, the reception state is bad However, a beautiful screen, that is, a screen with no frame drop can be displayed on the monitor 18.

  In the decoding apparatus 1, the maximum number of iterations may be determined by a number such as 50, or may be limited by a time such as 1/90 seconds. When the maximum number of iterations is limited by time, the decoding device 1 sets the longest iteration processing time in advance using a timer in consideration of the frame time of the television receiver 10 and other signal processing times. To do.

<Variation 1 of the first embodiment>
Hereinafter, a decoding device 1B (not shown) of Modification 1 of the first embodiment will be described. Since the configuration and operation of the decoding device 1B are similar to those of the decoding device 1 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  In the decoding device 1 according to the first embodiment, the LLR updater 24 sets the absolute value of the log likelihood ratio λ of the bit corresponding to the BCH code for which the parity check is OK, that is, the reliability, to the maximum value Mx. Was. On the other hand, in the decoding device 1B, the LLR updater 24 adds a predetermined value S1 to the reliability of the bit corresponding to the BCH code whose parity check is OK. Here, the predetermined value S1 is a positive value determined in advance, but may be a value that changes according to the reception state or the like.

  That is, the updated LLR value, λ (j), is calculated by the following (Equation 10).

λ (j) = sign (λ (j)) × (| λ (j) | + S1) (Equation 10)
j = (M + 1 + 2Nb) to (M + 3Nb)
However, when the reliability value calculated by (Equation 10) is larger than “Mx”, the reliability value is set to “Mx”.

  FIG. 12 is a schematic diagram for explaining the update of the log likelihood ratio λ, and FIG. 12 (A) is the same diagram as FIG. 10 (A). FIG. 12B is a schematic diagram for explaining the reliability update in the decoding device 1B. That is, the decoding apparatus 1B increases the reliability by adding the predetermined value S1 to the reliability of the bit corresponding to the BCH code for which the parity check is OK.

  The decoding device 1B can make a relative difference in reliability between the parity check OK portion and the NG portion by updating the LLR as described above. Furthermore, the decoding apparatus 1B can hold a difference in reliability between bits in a portion where the parity of the BCH is OK. For this reason, the decoding apparatus 1B can reduce the number of repetitions until the decoding of LDPC decoding is completed as compared with the decoding apparatus 1. That is, the decoding device 1B can perform higher-speed processing in addition to the effects of the decoding device 1. In addition to the effects of the television receiver 10 having the decoding device 1, the television receiver having the decoding device 1 </ b> B can display a beautiful screen on the monitor even when the reception state is bad. Also, the decoding device 1B is more sensitive to the corresponding bit determined during the subsequent iteration process than the decoding device 1 that updates the reliability of the corresponding bit to Mx when the parity check result is incorrect. Is easy to repair.

<Modification 2 of the first embodiment>
Hereinafter, a decoding apparatus 1C (not shown) of Modification 2 of the first embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1C are similar to those of the decoding device 1 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  In the decoding device 1 according to the first embodiment, the LLR updater 24 sets the absolute value of the log likelihood ratio λ of the bit corresponding to the BCH code for which parity check is OK, that is, the reliability, to the maximum value Mx. It was. On the other hand, the LLR updater 24 of the decoding device 1C lowers the absolute value of the log likelihood ratio λ of the bit corresponding to the BCH code that was the parity check NG, that is, the reliability.

  For example, in the decoding apparatus 1C, when the third BCH code is OK and the first, second, and fourth BCH codes are NG, the bits corresponding to the first, second, and fourth BCH codes For the log likelihood ratio λ, the updated LLR value, λ (j), is calculated by (Equation 11) below. Here, S2 is a predetermined positive value.

λ (j) = sign (λ (j)) × (| λ (j) | −S2) (Equation 11)
j = (M + 1) to (M + 2Nb), (M + 1 + 3Nb) to N
However, when (| λ (j) | −S2) becomes a negative value, λ (j) is set to “0”.

  FIG. 12C is a schematic diagram for explaining the update of reliability in the decoding apparatus 1C. As shown in FIG. 12C, the LLR updater 24 of the decoding device 1C lowers the reliability of the bit corresponding to the parity check NG by S2.

  The decoding apparatus 1C that updates the LLR value as described above can make a relative difference between the reliability of the parity check OK part and the part that is NG. For this reason, the decoding apparatus 1C can reduce the number of repetitions of LDPC decoding. Furthermore, the decoding apparatus 1C can maintain the same state of the difference in reliability between bits in the portion where the parity of the BCH is OK as before the update processing. For this reason, the decoding apparatus 1 </ b> C can reduce the number of repetitions until the LDPC decoding is completed, as compared with the decoding apparatus 1. Also, the decoding device 1C is easier to repair the error during the subsequent iteration process than the decoding device 1 that updates the reliability to Mx when the parity check result is incorrect. .

<Modification 3 of the first embodiment>
Hereinafter, a decoding device 1D (not shown) of Modification 3 of the first embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1D are similar to those of the decoding device 1 of the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  The LLR updater 24 of the decoding device 1D sets the reliability of the bit corresponding to the parity check OK to the same magnitude as the LLR value having the maximum absolute value in the LDPC code, as shown in FIG. That is, if the largest absolute value in the log likelihood ratio λ (j) before update is Lx, the updated LLR value, λ (j), for the portion corresponding to the parity check OK is It is calculated by (Equation 12).

λ (j) = sign (λ (j)) × Lx (12)
j = (M + 1 + 2Nb) to (M + 3Nb)
However, Lx = Max (| λ (j) |): j = 1 to N
By updating the LLR value as described above, the decoding apparatus 1D can make a relative difference in the reliability between the parity check OK part and the NG part, and the number of repetitions until the LDPC decoding is completed. Can be reduced. In addition, when the parity check result is incorrect, the decoding device 1D is easier to repair the error during the subsequent iteration process than the decoding device 1 that updates the reliability to Mx.

<Modification 4 of the first embodiment>
Hereinafter, a decoding device 1E (not shown) according to the sixth embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1E are similar to those of the decoding device 1 according to the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  As shown in FIG. 12E, the LLR updater 24 of the decoding device 1E matches the reliability of the bit corresponding to the parity check OK with the highest reliability in the LLR of the bit corresponding to the parity check OK. .

  That is, in the log likelihood ratio λ (j) before the update, if the largest absolute value is L2x in the part corresponding to the parity check OK, the LLR value after the update for the part corresponding to the parity check OK , Λ (j) is calculated by the following (Equation 13).

λ (j) = sign (λ (j)) × L2x (Expression 13)
j = (M + 1 + 2Nb) to (M + 3Nb)
However, L2x = Max (| λ (j) |): j = (M + 1 + 2Nb) to (M + 3Nb).

  By updating the above description, the decoding apparatus 1E can make a relative difference between the reliability of the parity check OK portion and the NG portion, and reduces the number of repetitions until the LDPC decoding is completed. Can be made. Also, the decoding device 1E is easier to repair the error during the subsequent iteration process than the decoding device 1 that updates the reliability to Mx when the parity check result is incorrect. .

<Second Embodiment>
Hereinafter, a decoding device 1F (not shown) according to the second embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1F are similar to those of the decoding device 1 according to the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  Here, FIG. 13 is a flowchart for explaining the flow of the decoding process in the decoding apparatus 1F. Steps S31 to S43 in the flowchart in FIG. 13 are the same as steps S11 to S23 in the flowchart in FIG.

  In the decoding device 1F, the LLR updater 24 performs an update process according to the number of iterations Itr, that is, an update process for λ (j) according to information from the BCH parity checker 23, Pr (j). . More specifically, when the number of iterations Itr is equal to or less than the predetermined number V, the LLR updater 24 does not perform update processing based on the result of the BCH parity check. That is, step S35A in FIG. 13 corresponds to the above process. The operation of the LLR updater 24 when the number of iterations exceeds V is the same as that of the decoding device 1 of the first embodiment, but may be the same as that of the decoding devices 1B to 1E. good. Of course, V satisfies the relationship 1 <V <MItr.

  The decoding apparatus 1F of the second embodiment can be applied to the case where the error correction capability of the BCH code is substantially low in order to perform the above processing. That is, when there are many errors in the transmission path, there is a case where it is determined that there is no error even though there is an error in the received word in practice when the BCH code is decoded. If the reliability is updated to Mx based on the result of this erroneous parity check, the decoding process takes time.

  The decoding device 1F uses the result of the parity check of the BCH parity check unit 23 after the error is corrected to some extent by the V iteration processes. For this reason, the decoding apparatus 1F can prevent erroneous detection in decoding of the BCH code even when there are many errors in the transmission path, so that the number of iterations until the LDPC decoding is completed can be reduced. Can do.

  The predetermined number of times V may be set in advance as a predetermined number, for example, 10 times, or may be set relatively, such as the maximum number of iterations, 25% of MItr, or received. It may be a value that changes according to the state or the like. Furthermore, the number of times V may be set substantially in the longest processing time of the iteration process.

<Third Embodiment>
Next, a decoding device 1G according to the third embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1G are similar to those of the decoding device 1 according to the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

FIG. 14 is a block diagram of the decoder of the decoding device 1G, and FIG. 15 is a flowchart for explaining the flow of decoding processing of the decoding device 1G. Steps S51 to S63 in the flowchart in FIG. 15 are the same as steps S11 to S23 in the flowchart in FIG.
As illustrated in FIG. 14, the decoding apparatus 1 </ b> G notifies the LLR updater 24 of information from the LDPC decoder 25. Then, after obtaining the posterior probability, the LDPC decoder 25 calculates the average posterior probability value APb by the following (formula 14).

APb = ΣPb (j) / N: j = 1 to N (Expression 14)
The LLR updater 24 does not perform the LLR value update process during the first (first) iteration process. Furthermore, the LLR updater 24 updates λ (j) according to the average posterior probability value APb obtained from the LDPC decoder 25 and the information from the BCH parity checker 23, Pr (j): j = 1 to 4. .

  That is, as shown in FIG. 15, the decoding apparatus 1G determines whether or not the number of iterations is two or more and APb is equal to or less than a certain threshold Th in step S55A. The LLR updater 24 performs reliability update processing when APb is equal to or less than the threshold Th and the number of iterations is 2 or more and APb is greater than Th. The LLR value update method at this time is the same as that of the decoding device 1 or the like.

  The decoding device 1G can also be applied to a case where the error correction capability of the BCH code is substantially low as in the decoding device 1F. Furthermore, since the reliability update process is started based on the average posterior probability value APb information, in addition to the effect of the decoding apparatus 1F, the number of iterations until the completion of decoding of LDPC decoding can be further reduced.

<Fourth embodiment>
Next, a decoding device 1H according to the fourth embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1H are similar to those of the decoding device 1 according to the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted. FIG. 16 is a block diagram of a decoding device 1H according to the fourth embodiment, and FIG. 17 is a flowchart for explaining the flow of decoding processing of the decoding device 1H according to the fourth embodiment. Note that each process in the flowchart of FIG. 17 is the same as each process in FIG.

  Here, depending on the transmission device 5, the transmission signal may be punctured to reduce the transmission bit amount. Puncture processing is processing that regularly removes bits based on a bit erasure pattern determined by a predetermined punctured coding rate.

  When the punctured signal is received, the LLR generator 21 fills “0” in the position corresponding to the puncture, that is, inserts “0” as the data of the position corresponding to the puncture. For this reason, when the puncture processing is performed on the BCH encoded portion, it is meaningless to perform the parity check of the BCH code with the punctured portion being filled with “0”.

  For this reason, the decoding apparatus 1H performs an LDPC decoding process before the BCH parity check, as shown in FIGS. Then, the LLR updater 24 performs an LLR value update process according to the result of the BCH parity check. The LLR value update process performed by the LLR updater 24 is the same as that of the decoding device 1 or the like.

  The decoding device 1H can achieve the same effects as the decoding device 1 and the like even when the transmission signal is punctured.

<Fifth embodiment>
Next, a decoding device 1I according to the fifth embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1I are similar to those of the decoding device 1 according to the first embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  FIG. 18 is a block diagram of a decoding apparatus 1I according to the fifth embodiment, FIG. 19 is an explanatory diagram showing error bits in the LDPC code in the decoding apparatus 1I, and FIG. 20 shows the decoding apparatus 1I. It is a schematic diagram for demonstrating the update of log likelihood ratio (lambda).

  In the decoding apparatus 1I, first, error detection of the BCH code, that is, parity check is performed by the BCH decoder 27A using the hard decision value Hd. In an algebraic decoding process of a BCH code, an error position polynomial is first output as a decoding result. The BCH decoder 27A can specify not only the presence / absence of an error in the BCH code but also the error bit position by solving this polynomial.

  In the decoding device 1I, the BCH decoder 27A attempts algebraic decoding from the hard decision value and notifies the LLR updater 24 of the information of the bit j determined to be the error position. The LLR updater 24 updates λ (j) corresponding to the bit j determined as the error position in the BCH decoder 27A. FIG. 19 shows a case where the third bit of the BCH code is determined as an error by the BCH decoder 27A as an example. When the reliability shown in FIG. 20A is updated before the update, the LLR updater 24 updates the reliability shown in FIG. 20B.

  That is, the LLR updater 24 sets the LLR value, λ (M + 3), corresponding to the third bit of the BCH code to “0” and updates it. On the other hand, the LLR value remains λ for bits that are not determined to be errors by the BCH decoder 27A.

  Next, the flow of the decoding process of the decoding device 1I will be described with reference to FIG. FIG. 21 is a flowchart for explaining the flow of the decoding process of the decoding apparatus 1I. Note that the maximum number of iterations is MItr. Of the processes in the flowchart of FIG. 21, descriptions of processes similar to the processes in FIG. 11 are omitted.

  Hereinafter, the flow of the decoding process will be described with reference to the flowchart of FIG.

<Step S94>
BCH decoder 27A attempts algebraic decoding of the four BCH codes.

<Step S95>
If the BCH decoder 27A can identify the error bit position in the BCH code (Yes), the LLR value is updated in step S96. On the other hand, if the BCH decoder 27A cannot identify the error bit position in the BCH code (No), the LLR value is not updated.

<Step S96>
The LLR updater 24 sets and updates the LLR value of the bit corresponding to the error bit to “0”. On the other hand, the LLR values of the other bits are left as they are and are not updated.

  In the decoding apparatus 1I, as described above, the error correction result of the BCH code, that is, the LLR value corresponding to the error bit is updated to “0”. For this reason, the decoding apparatus 1I can further accelerate the update of the LLR value in the LDPC decoding than the decoding apparatus 1, and as a result, the number of iterations of the iteration process in the LDPC decoding is more than the decoding apparatus 1. Can be reduced.

  In the decoding device 1I of the fifth embodiment, the LLR value of the bit corresponding to the error is set to “0”, but the sign of the LLR value may be inverted. That is, λ (j) = − λ (j): j = M + 3 is updated.

<Modification 1 of Fifth Embodiment>
Next, a decoding device 1J according to Modification 1 of the fifth embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1J are similar to those of the decoding device 1J according to the fifth embodiment, the same components are denoted by the same reference numerals and description thereof is omitted.

  FIG. 22 is a block diagram of a decoding device 1J according to the first modification of the fifth embodiment. As illustrated in FIG. 22, the decoding device 1J includes a BCH decoder 27 in addition to the BCH decoder 27A.

  In the decoding apparatus 1J, even if the predetermined maximum number of iterations has elapsed, if the parity check of the LDPC code is NG, the decoding process by the BCH decoder 27 is performed. If the number of error bits after the LDPC code decoding process is equal to or less than the error correction capability of the BCH code, the decoding device 1J can correct the error bits correctly.

  Therefore, the decoding device 1J is a high-performance decoding device that has the same effects as the decoding device 1I and has a higher error correction capability.

  In FIG. 22, for ease of explanation, the BCH decoder 27 is illustrated as a decoder different from the BCH decoder 27A, but one decoder may also be used.

<Sixth Embodiment>
Next, a decoding device 1K (not shown) according to the sixth embodiment of the present invention will be described. Since the configuration and operation of the decoding device 1K are similar to those of the decoding device 1 of the first embodiment and the decoding device 1I of the fifth embodiment, the same components are denoted by the same reference numerals and description thereof is omitted. To do.

  FIG. 23 is a flowchart for explaining the flow of the decoding process of the decoding device 1K according to the sixth embodiment. In addition, description about the process similar to each process already demonstrated among the processes in the flowchart of FIG. 23 is abbreviate | omitted.

  In the decoding apparatus 1K, in the iteration process, first, the BCH decoder 27 detects only the presence or absence of an error, and from a certain stage, the BCH decoder 27 specifies the error position.

  For example, when the number of iterations is equal to or less than ½ of the maximum number of iterations MItr, the decoding device 1K shown in the flowchart of FIG. 23 performs processing in the decoding process of the decoding device 1, that is, the BCH decoder 27 Only the presence or absence of an error is detected, and LLR update A is performed based on it. When the number of iterations exceeds 1/2 of the maximum number of iterations MItr, the decoding apparatus 1K specifies the decoding process of the decoding apparatus 1I, that is, the BCH decoder 27 specifies the error position, and based on that, the LLR Update B is performed.

  That is, in step S114, the number of iterations is confirmed. If the number of iterations is equal to or less than ½ of the maximum number of iterations MItr, the LLR value is updated to the log likelihood ratio update A by the processing from step S115. Update by processing. In the log likelihood ratio update A process, the BCH decoder 27 detects only whether or not an error exists, similarly to the BCH error detector. Then, the LLR updater 24 updates λ (j) according to the result of parity check Pr (j): J = 1 to 4 for each of the four BCH codes.

  In the log likelihood ratio update A process, in the case of the parity check OK, the LLR updater 24 sets the absolute value of the LLR value λ of the corresponding bit to the maximum value Mx. On the other hand, the LLR updater 24 does not update the bit corresponding to the parity check NG with the initial value λ.

  In step S114, if the number of iterations exceeds 1/2 of the maximum number of iterations MItr (No), the BCH decoder 27 identifies up to the error position by the processing from step S118, and the LLR The updater 24 sets the LLR value λ corresponding to the bit determined to be error to “0”. On the other hand, bits that the BCH decoder 27 has not determined to be in error are not updated with the initial value λ.

  Note that the “certain stage” at which the decoding process is switched may be determined based on the maximum number of iterations MItr as described above, may be based on the number of errors detected by the BCH decoder 27, or may be determined in time. May be based.

  By performing the above-described control, the decoding device 1K can prevent a bad effect due to erroneous correction by the BCH code. That is, the present invention can also be applied when the error correction capability of the BCH code is substantially low. That is, if there are many errors in the transmission path, erroneous detection may occur at the error position of the BCH code. If the reliability is updated to Mx based on the erroneous error position detection result, the decoding process may take time. However, in the iteration process, the decoding apparatus 1K first detects only the presence or absence of an error in the BCH decoder 27, and after the error in the data is corrected to some extent by repetition of the iteration process, the BCH decoder 27 specifies the error position. For this reason, even when there are many errors in the transmission path, it is possible to prevent erroneous detection during decoding of the BCH code, so that the number of repetitions until the LDPC decoding is completed can be reduced.

    In the decoding apparatus 1K, the case where the BCH decoder 27 also functions as a BCH error detector has been described as an example, but a dedicated BCH error detector may be used.

  Also in the decoding apparatus 1K, as in the decoding apparatus 1J, even if the predetermined maximum number of iterations has elapsed, if the parity check of the LDPC code is NG, the decoding process by the BCH decoder 27 is performed. Data may be output.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the components without departing from the scope of the invention in the implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, constituent elements over different embodiments may be appropriately combined.

  Moreover, in the said embodiment, the example which used Min-Sum algorithm for the check node process was shown. This is because the Min-Sum algorithm is simple and easy to explain as an LDPC code decoding method. However, the same effect as the decoding device of the above embodiment can be obtained even if other methods such as the Sum-Product algorithm, Shuffled BP decoding method, and Offset BP-based decoding method are used for the check node processing. . For example, the method using the Sum-Product algorithm has the best decoding characteristics, but the calculation in the check node process is complicated.

  In the above embodiment, the LDPC code is used as the inner code. However, other soft-decodable error correction codes may be used. Furthermore, although the LBCH code is used for the outer code in the above embodiment, other codes, for example, a code such as a Reed-Solomon code may be used. Furthermore, in the above-described embodiment, four BCH codes are applied to the information portion of the LDPC code. However, the number of BCH codes does not have to be four and may be any number of one or more.

  In the above embodiment, BPSK is shown as an example of the data modulation scheme, but other modulation schemes, for example, a modulation scheme such as QPSK, 8PSK, 16QAM, 32QAM, or 64QAM may be used.

  As described above, the decoding device of the present invention has the following characteristics.

  1. The log-likelihood ratio updater updates only the log-likelihood ratio at the position corresponding to the first error-correcting code in which no error is detected in the parity check of the first error-correcting code parity checker. A decoding device.

  2. 2. The decoding apparatus according to claim 1, wherein the log likelihood ratio updater updates the log likelihood ratio to be updated to a value representing the maximum reliability.

  3. 2. The decoding apparatus according to claim 1, wherein the log-likelihood ratio updater updates the log-likelihood ratio to be updated to a log-likelihood ratio whose reliability is increased by a predetermined value.

  4). The log likelihood ratio updater detects the highest reliability Lx among all log likelihood ratios, and updates the log likelihood ratio to be updated to a log likelihood ratio with reliability Lx. 2. The decoding device according to 1.

  5). The log likelihood ratio updater detects the highest reliability in the log likelihood ratio to be updated, and updates the log likelihood ratio to be updated to the highest reliability detected. 2. The decoding device according to 1 above.

  6). The log likelihood ratio updater updates only the log likelihood ratio of the position corresponding to the first error correction code in which an error is detected by the first parity check.

  7. 7. The decoding apparatus according to claim 6, wherein the log likelihood ratio updater updates the reliability of the log likelihood ratio to be updated to a value reduced by a predetermined value.

  8). The log likelihood ratio updater measures the number of iterations of the decoding process, and performs a log likelihood ratio update process when the number of iterations exceeds a predetermined number.

  9. The average value of the log likelihood ratio after the decoding process is measured, and the log likelihood ratio updater performs the update process of the log likelihood ratio when the average value of the log likelihood ratio becomes larger than a predetermined value. A decoding device characterized by the above.

  10. A decoding apparatus, wherein the first error correction code is a BCH code, and the second error correction code is an LDPC code.

  11. 11. The decoding device as described in 10 above, wherein the second error correction code decoder is a decoder based on a Sum-Prodcut algorithm.

  12 11. The decoding device as described in 10 above, wherein the second error correction code decoder is a decoder based on a min-sum algorithm.

  As described above, the present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the scope of the present invention.

It is a figure for demonstrating iterative decoding in a LDPC code. FIG. 4 is a diagram showing a part of a Tanner graph G. It is a block diagram which shows the structure of the decoding apparatus of a well-known LDPC code. It is a block diagram which shows the schematic structure of the television receiver which has a decoding apparatus of the 1st Embodiment of this invention. It is a block diagram which shows the structure of the transmitter for demonstrating the 1st Embodiment of this invention. It is explanatory drawing for demonstrating the connection code | symbol of the 1st Embodiment of this invention. It is a block diagram for demonstrating the structure of the decoding apparatus of the 1st Embodiment of this invention. It is explanatory drawing for demonstrating a log likelihood ratio. It is explanatory drawing for demonstrating the bit by which LLR is updated among the concatenated codes of the 1st Embodiment of this invention. It is a schematic diagram for demonstrating the bit by which LLR is updated in the concatenated code of the 1st Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process of the decoding apparatus of the 1st Embodiment of this invention. It is a schematic diagram for demonstrating the bit by which LLR is updated among the concatenated codes | symbols of the modification of the 1st Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process in the decoding apparatus of the 2nd Embodiment of this invention. It is a block diagram of the decoder of the decoding apparatus of the 3rd Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process in the decoding apparatus of the 3rd Embodiment of this invention. It is a block diagram of the decoder of the decoding apparatus of the 4th Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process in the decoding apparatus of the 4th Embodiment of this invention. It is a block diagram of the decoder of the decoding apparatus of the 5th Embodiment of this invention. It is a schematic diagram for demonstrating the bit by which LLR is updated in the concatenated code of the modification of the 5th Embodiment of this invention. It is a schematic diagram for demonstrating the bit by which LLR is updated in the concatenated code of the modification of the 5th Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process in the decoding apparatus of the 5th Embodiment of this invention. It is a block diagram of the decoder of the decoding apparatus of the modification of the 5th Embodiment of this invention. It is a flowchart for demonstrating the flow of the decoding process in the decoding apparatus of the 6th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Decoding device, 1G ... Decoding device, 1H ... Decoding device, 1I ... Decoding device, 1J ... Decoding device, 1P ... Decoding device, 3 ... Transmission device, 6 ... Transmission antenna, 7 ... Encoding device, 7A ... BCH code 7 ... LDPC encoder, 10 ... TV receiver, 11 ... receive antenna, 12 ... receiver, 13 ... A / D converter, 14 ... GI remover, 15 ... FFT, 16 ... transmission path, etc. 17: Post-processing device, 18 ... Monitor, 19 ... Speaker, 21 ... LLR generator, 22 ... Hard decision value generator, 23 ... BCH parity checker, 24 ... LLR updater, 25 ... LDPC decoder, 26 ... LDPC parity checker, 27 ... BCH decoder, 27A ... BCH decoder, 31 ... LLR generator, 32 ... LDPC decoder, 33 ... LDPC parity checker, 34 ... hard decision decoder

Claims (5)

Using the first error correction code for hard decision decoding as the outer code;
Using the second error correction code for soft decision decoding as the inner code,
A decoding device that performs decoding processing of data encoded by a concatenated code including one or more outer codes in the inner code,
A log likelihood ratio generator that generates an initial value of the log likelihood ratio from the data;
Based on the log likelihood ratio, a hard decision value generator that generates a hard decision value;
A first error correction code parity checker for performing a parity check of the first error correction code based on the hard decision value;
A log likelihood ratio updater that updates the log likelihood ratio according to a result of the parity check of the first error correction code parity checker;
A second error correction code decoder for updating the log likelihood ratio from the log likelihood ratio updater by decoding the second error correction code; and the logarithm from the second error correction code decoder A second error correction code parity checker that generates a hard decision value based on the likelihood ratio and performs a parity check;
A decoding apparatus comprising: a first error correction code decoder that performs a decoding process of a first error correction code based on a hard decision value generated by the second error correction code parity checker . Using the first error correction code for hard decision decoding as the outer code;
Using the second error correction code for soft decision decoding as the inner code,
A decoding device that performs decoding processing of data encoded by a concatenated code including one or more outer codes in the inner code,
A log likelihood ratio generator that generates an initial value of the log likelihood ratio from the data;
Based on the log likelihood ratio, a hard decision value generator that generates a hard decision value;
A first error correction code decoder for decoding the first error correction code based on the hard decision value;
A log-likelihood ratio updater that sets the log-likelihood ratio to 0 corresponding to a bit in which an error is detected by a decoding result of the first error-correcting code decoder;
A second error correction code decoder for updating the log likelihood ratio from the log likelihood ratio updater by decoding the second error correction code; and the logarithm from the second error correction code decoder A second error correction code parity checker that generates a hard decision value based on the likelihood ratio and performs a parity check;
Decoding comprising: the first error correction code decoder for decoding the first error correction code based on the hard decision value generated by the second error correction code parity checker apparatus. When an error is detected as a result of the parity check of the second error correction code parity checker,
The hard decision value generator generates the hard decision value based on the log likelihood ratio updated by the second error correction code decoder;
The first error correction code parity checker performs the parity check of the first error correction code based on the hard decision value;
The log likelihood ratio updater updates the log likelihood ratio according to a decoding result of the first error correction code decoder;
The second error correction code decoder updates the log likelihood ratio from the log likelihood ratio updater by decoding the second error correction code;
An iteration process in which the second error correction code parity checker generates the hard decision value based on the log likelihood ratio from the second error correction code decoder and performs the parity check;
Repeated below the preset maximum number of iterations,
After the iteration process for the maximum number of iterations, the first error correction code decoder uses the hard decision value generated by the second error correction code parity checker to generate the first error correction. The decoding apparatus according to claim 1 or 2, wherein a decoding process of a code is performed. Comprising the constituent elements of the decoding device according to claim 1 and the decoding device according to claim 2;
Based on a predetermined number of iterations,
A decoding apparatus, wherein the decoding process performed by the decoding apparatus according to claim 1 is switched to the decoding process performed by the decoding apparatus according to claim 2.   A television receiver comprising the decoding device according to any one of claims 1 to 4.

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