JP4603518B2 - Encoding device and decoding device - Google Patents

Description

  The present invention relates to an encoding apparatus that encodes data such as video and audio, and a decoding apparatus that decodes data encoded by the encoding apparatus.

  Conventionally, for example, an FEC (Forward Error Correction) method is known as a method used to ensure reliability when transmitting data such as video and audio (hereinafter referred to as “video data”). ing. The FEC method is an error correction method that makes it possible to restore data lost during transmission on the receiving device side by adding a redundant code for error correction to the data to be transmitted. A typical example of the FEC method is a Reed-Solomon (hereinafter referred to as “RS”) code. RS codes are widely used in various fields, and an encoding device and a decoding device corresponding to the RS codes can be obtained relatively inexpensively.

  There is no exception in the broadcasting field, and RS codes are adopted in each standard. For example, ISDB-S (Integrated Services Digital Broadcasting-Satelite), which is a standard for satellite digital broadcasting, ISDB-T (Terrestrial), which is a terrestrial digital broadcasting standard, and DVB-S (Digital Video Broadcasting Standard, which is a European satellite broadcasting standard). ) Etc., a concatenated code of a convolutional code and an RS code is used. In these standards, a 204-byte RS code (hereinafter referred to as “RS (204, 188) code”) in which a 188-byte information is added to a 188-byte information is used, and RS (204, 188) The code can correct up to any 8-byte code error.

By using the RS (204, 188) code, a very excellent error rate characteristic can be obtained as shown in FIG. FIG. 15 is a graph showing the bit error rate before and after error correction by the RS (204, 188) code. For example, at a bit error rate of 2 × 10 ⁻⁴ before error correction, the RS (204, 188) code is used. The bit error rate after error correction is lower than 1 × 10 ⁻¹² , indicating that a very low error rate characteristic can be obtained by using the RS (204, 188) code.

  By the way, the so-called Shannon limit is known as the theoretical limit of the code performance, and research on the code theory is conducted for the purpose of developing a code exhibiting performance close to the Shannon limit. Among them, the LDPC (Low Density Parity Check) code proposed by Gallagher in 1962 is one of powerful error correction codes having performance approaching the Shannon limit (for example, Non-Patent Document 1). reference). Hereinafter, the LDPC code will be described.

The LDPC code is a linear code, and the relationship of Expression (1) is established between the information vector and the generator matrix. C represents a code word, m represents an information vector, and G represents a generator matrix.

In general, in a linear code, the relationship of Equation (2) is established between a generator matrix and a check matrix. H represents a check matrix and T represents a transposed matrix.

  A very sparse check matrix is prepared in advance, a generator matrix G is obtained from Equation (2), and an LDPC-encoded codeword can be obtained by using Equation (1). The parity check matrix for the LDPC code is configured as shown in FIG. 16, for example. The parity check matrix for the LDPC code illustrated in FIG. 16 has a row weight of 4 and a column weight of 3, and there are four and three “1” s in the row direction and the column direction, respectively.

  LDPC codes are classified into regular LDPC codes in which the row weights and column weights in the check matrix are constant, and non-regular LDPC codes in which the row weights and column weights are not constant. Various methods have been proposed for constructing a parity check matrix used in an LDPC code. A regular LDPC code with a column weight of 3 has relatively good decoding performance, and a non-regular LDPC code with optimized row weight and column weight is It has been reported that decoding performance is better than regular LDPC codes (see, for example, Non-Patent Document 2).

  In addition, a parity check matrix for an LDPC code can be composed of two partial matrices, and a code word can be directly obtained from the parity check matrix by making one partial matrix have a lower triangular structure, so that an LDGM (Low Density Generator) can be obtained. Matrix) structure has been proposed (see, for example, Non-Patent Document 3).

  As described above, the LDPC code is a powerful error correction code approaching the Shannon limit, and is attracting attention in the broadcasting field. For example, DVB-S2, which is a new European satellite broadcasting standard, employs a concatenated code of an irregular LDPC code and a BCH (Bose Chaudhuri Hocquenhem) code.

  By the way, recently, there has been an increasing demand for broadband transmission signals such as next-generation broadcasting media such as Super Hi-Vision and stereoscopic HDTV (High Definition Television), and non-compressed transmission of high-definition program materials using wireless cameras. Specifically, broadband transmission of several hundred Mbps to several Gbps class is required.

  As described above, the LDPC code is a powerful error correction code that approaches the Shannon limit. However, when applied to wideband transmission of several hundred Mbps to several Gbps class, the bit error rate is required to a very low value. In order to satisfy a predetermined error rate, a portion (residual bit error) that cannot be corrected only by the LDPC code needs to be corrected by another error correction code. Therefore, as a code for correcting a residual bit error that cannot be corrected only by an LDPC code, an RS code is used rather than a less versatile BCH code in consideration of compatibility, compatibility, cost, etc. with an existing broadcasting transmission system. Is desirable. In particular, among RS codes, it is desirable that RS (204, 188) codes frequently used in the transmission system for broadcasting be concatenated with LDPC codes.

R. G. Gallager, "Low density parity check codes," in Research Monograph series Cambridge, MIT Press (1963) D. J. et al. C. MacKay, “good error-correcting codes based on very sparse metrics,” IEEE Trans. Inform. Theory, vol. 45, pp. 399-431 (1999) M.M. Rashidpur and S.R. H. Jamali, "Low-Density Parity-Check codes with Simple Irregular Semi-Random Parity Check Matrix for Finite-Length Applications," pp. 439-443, in proc. IEEE PIMRC 2003

  However, in the conventional technique, if an RS (204, 188) code and an LDPC code are simply concatenated and encoded, a new apparatus is required, which causes complication of encoding processing and decoding processing, and increases manufacturing costs. There was a problem of rising.

  Specifically, since an LDPC code determines a coding rate based on a predetermined bit length, when an RS (204, 188) code and an LDPC code are simply concatenated and coded, , RS (204, 188) -encoded packet is divided in units of predetermined bits, and apparatus for generating division position information indicating the division position of the packet at the time of LDPC code encoding and transmitting it to the decoding apparatus And a device that receives the division position information and applies it to the decoding process.

  Therefore, in the conventional technique, unless a new device for transmitting and receiving the division position information is added, the characteristic of the LDPC code cannot be used while maintaining the characteristic of the RS (204, 188) code. there were.

  The present invention has been made to solve the conventional problems, and an encoding device capable of concatenating an LDPC code and an RS code without adding a new device, and the encoding device. It is an object of the present invention to provide a decoding device capable of decoding encoded data.

  The encoding apparatus of the present invention includes a first encoding unit that encodes an input packet with a Reed-Solomon code and outputs a first encoded packet, and a code that is an integral multiple of the packet length of the first encoded packet. Check matrix generation means for generating a check matrix having a length; and second encoding means for encoding the first encoded packet with a low-density parity check code based on the check matrix and outputting a second encoded packet; It has the composition provided with.

  With this configuration, in the encoding device of the present invention, the check matrix generation unit generates a check matrix having a code length that is an integral multiple of the packet length of the first encoded packet, and the second encoding unit generates Since the first encoded packet is encoded with the low-density parity check code based on the parity check matrix, the low-density parity check code for each packet is divided without dividing the packet into predetermined bits as in the conventional technique. Can be Therefore, the encoding apparatus of the present invention can perform concatenated encoding of the low density parity check code and the Reed-Solomon code without adding a new apparatus.

  In the encoding device of the present invention, the first encoded packet includes an information unit that is an encoding target of the Reed-Solomon code and a parity unit generated by encoding the Reed-Solomon code, The bit length of 188 bytes is 188 bytes, and the bit length of the parity part is 16 bytes.

  With this configuration, the encoding apparatus according to the present invention, among Reed-Solomon codes, uses a Reed-Solomon code in which the bit length of the information part, which is frequently used in the transmission system for broadcasting, is 188 bytes and the bit length of the parity part is 16 bytes. It can be concatenated with a low density parity check code.

  Further, in the encoding device of the present invention, the second encoded packet includes an information unit that is an encoding target of the low density parity check code and a parity unit generated by encoding the low density parity check code. The bit length of each of the information part and the parity part has a configuration that is a predetermined integer multiple of the packet length of the first encoded packet.

  With this configuration, the encoding apparatus of the present invention can set the encoding rate by the number of packets, and thus can easily generate a check matrix according to the encoding rate.

  The decoding device of the present invention is a decoding device for decoding data concatenated and encoded with a Reed-Solomon code and a low-density parity check code, and has a packet length of a packet encoded with the Reed-Solomon code. Information related to a check matrix having a code length that is an integer multiple, information related to a coding rate in encoding using the low-density parity check code, and information related to the number of packets of the packet having a length corresponding to the code length Encoding information storage means for storing, first decoding means for performing decoding by the low-density parity check code based on information on the check matrix and information on the coding rate, and the packet And a second decoding means for performing decoding by the Reed-Solomon code based on the information relating to the number.

  With this configuration, since the decoding apparatus of the present invention can perform decoding by the low density parity check code on a packet basis, the low density parity check code and the Reed-Solomon code can be obtained without adding a new apparatus. The concatenated encoded data can be decoded.

  The present invention provides an encoding device capable of concatenating LDPC code and RS code without adding a new device, and a decoding device for decoding data encoded by the encoding device. Is something that can be done.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
First, the configuration of the encoding apparatus according to the present invention will be described. Note that the encoding apparatus according to the present invention includes a transport stream (hereinafter referred to as “MPEG2-TS”) including data such as video data encoded in accordance with the MPEG (Moving Picture Experts Group) -2 standard. An example applied to a transmitting apparatus that transmits

  As shown in FIG. 1, transmitting apparatus 100 according to the present embodiment modulates encoded data, TS input section 101 that inputs MPEG2-TS, encoding apparatus 110 that encodes MPEG2-TS, and encoded data. A modulation unit 102 and a transmission unit 103 that transmits the modulated data are provided.

  The TS input unit 101 has an input interface corresponding to MPEG2-TS, and outputs the input MPEG2-TS to the encoding device 110. Here, the input MPEG2-TS has a plurality of packets including data such as video, and corresponds to a packet input to the first encoding means described in the claims.

  Encoding apparatus 110 includes RS encoding section 111 that encodes with an RS code, buffer section 112 that temporarily stores RS encoded data, and parity check matrix generation section 113 that generates a parity check matrix for LDPC codes. And an LDPC encoding unit 114 that encodes with an LDPC code. Note that the encoding device 110 can be realized by a configuration that performs software computation using, for example, a DSP (Digital Signal Processor) or a hardware circuit that uses, for example, an LSI (Large Scale Integrated circuit).

  The RS encoding unit 111 encodes a packet of video data included in the MPEG2-TS input by the TS input unit 101 with an RS (204, 188) code, and outputs the encoded packet to the buffer unit 112. It has become. The RS encoding unit 111 constitutes a first encoding unit of the present invention. The packet encoded with the RS (204, 188) code corresponds to the first encoded packet described in the claims.

  The buffer unit 112 is composed of, for example, a semiconductor memory, and temporarily stores a packet of data such as video encoded by the RS encoding unit 111.

  The parity check matrix generation unit 113 generates, for example, a parity check matrix including a partial matrix configured using the LDGM structure based on a predetermined code length N and coding rate R, and generates data of the generated parity check matrix. It is held in a memory (not shown). Note that the parity check matrix generation unit 113 constitutes a parity check matrix generation unit of the present invention.

Specifically, as shown in FIG. 2, the parity check matrix H generated by the parity check matrix generation unit 113 is an arbitrary matrix (hereinafter referred to as “information submatrix _HA ”) and an LDGM structure matrix (hereinafter referred to as “parity”). Sub-matrix H _T ”) and can be expressed as a check matrix H = [H _A | H _T ]. Here, the information sub-matrix H _A and the parity sub-matrix H _T respectively correspond to the information bit string and the parity bit string after LDPC encoding, and the number of columns of the information sub-matrix H _A and the parity sub-matrix H _T Hereinafter, the number of columns is referred to as an information length and a parity length of the check matrix H, respectively.

The code length N of the parity check matrix H is the sum of the information length and the parity length, and is a length that is an integral multiple of the packet length (= 204 bytes) of the packet encoded with the RS (204, 188) code. It is determined based on the packet length. Hereinafter, the number of packets when the code length N of the check matrix H is an integral multiple of 204 bytes is P _max . In this case, the code length N of the parity check matrix H is 204 × 8 × P _max bits.

  The information length of the parity check matrix H is represented by the product of the code length N and the coding rate R, and is a packet encoded with the RS (204, 188) code shown in the upper part of FIG. The packet length is determined based on the packet length so as to be an integral multiple of the packet length of a packet having a payload of 188 bytes and a parity of 16 bytes. If the number of packets at this time is P, the information length of the check matrix H is 204 × 8 × P bits. Note that the payload and parity shown in the upper part of FIG. 2 respectively correspond to the information part and the parity part of the first encoded packet described in the claims.

Further, the parity length of the parity check matrix H is N × (1−R) = 204 × 8 × (P _max −P) bits.

Parity part matrix _{H T} includes, for example, a matrix of LDGM structure shown in FIG. Note that the LDGM structure is sometimes called a lower triangular structure. As shown in FIG. 3, the parity part matrix H _T has a first diagonal section, consisting of the elements from the first row element of the first row to the last column of the last row, the first of the second row The second diagonal portion starting from the column is a square matrix composed of all “1” s and all other elements composed of “0” s.

As described above, the check matrix generating unit 113 generates a check matrix H containing information submatrix H _A and a parity part matrix H _T, the code length N, information length and parity length of the check matrix H, respectively, RS Since the length is set to a predetermined integer multiple of the packet length of the packet encoded with the (204,188) code, the packet length for the number of packets P encoded with the RS (204,188) code, Consistency with the number of columns of the information submatrix _HA can be obtained.

Further, the relationship between the coding rate R and the number of packets P is expressed by Expression (3).

Further, as described above, since the code length N of the check matrix H is 204 × 8 × P _max bits, the coding rate R is expressed by Equation (4).

From the equation (4), the coding rate R is calculated based on the number P of 204-byte packets encoded by the RS (204, 188) code and the number P _{max of} 204-byte packets corresponding to the code length N of the check matrix H. It can be expressed by the ratio. As a result, LDPC encoding is possible without destroying the code structure of the RS (204, 188) code during LDPC encoding, and the coding rate R can be expressed by the ratio between the number of packets P and _Pmax. Therefore, the parity check matrix generation unit 113 can easily generate the parity check matrix H according to the coding rate R.

  Based on the parity check matrix generated by parity check matrix generation section 113, LDPC encoding section 114 performs LDPC encoding on data encoded with RS (204, 188) code, and modulates the packet encoded with LDPC code. To output. The LDPC encoding unit 114 constitutes a second encoding unit of the present invention. The packet encoded with the LDPC code corresponds to the second encoded packet described in the claims.

  The modulation unit 102 includes, for example, a QPSK (Quadrature Phase Shift Keying) modulation circuit and an 8PSK modulation circuit, and modulates data encoded with the LDPC code by the QPSK method or the 8PSK method.

  The transmission unit 103 includes a transmission circuit and a transmission antenna, for example, and transmits data modulated by the QPSK method or the 8PSK method to a predetermined relay device or reception device.

  Next, the operation of transmitting apparatus 100 in the present embodiment will be described using FIG.

  First, MPEG2-TS is input by the TS input unit 101, and the input MPEG2-TS is output to the encoding device 110.

  Next, MPEG2-TS data is encoded by the encoding device 110 using the RS (204, 188) code and the LDPC code. Detailed operation of the encoding device 110 will be described later.

  Subsequently, the encoded MPEG2-TS data is modulated by, for example, the QPSK method by the modulation unit 102. The transmitter 103 transmits the modulated MPEG2-TS data.

  Next, the operation of encoding apparatus 110 in the present embodiment will be described using FIGS. FIG. 4 is a flowchart showing the operation of encoding apparatus 110 in the present embodiment.

First, as shown in steps S11 to S15 of FIG. 4, a check matrix H is generated in advance. Specifically, first, the code length N of the check matrix H and the number P _max of 204-byte packets corresponding to the code length N are set (step S11). Next, the coding rate R is set, and the number P of 204-byte packets corresponding to the information length is determined (step S12). Further, by setting the column weight of the information submatrix _HA (step S13), an information submatrix _HA composed of regular LDPC codes with a predetermined column weight is generated (step S14). Also, by adding a parity partial matrix H _T having an LDGM structure to the information sub matrix H _A (step S15), a check matrix H = [H _A | H _T ] is generated.

More specifically, for example, if P _max = 40, the code length N = 204 × 8 × 40 = 65280 bits. FIG. 5 shows the number of MPEG2-TS packets P and the row / column weight distribution of the parity check matrix H with respect to the coding rate R when a regular LDPC code is applied to the information submatrix _HA of the parity check matrix H. In FIG. 5, for example, when the coding rate R = 3/4, the number P of MPEG2-TS packets is 30. If the column weight is set to 3, for example, the parity check matrix H _T is added to obtain the parity check matrix H shown in FIG. That is, the parity check matrix H is a matrix having a code length N = 65280 bits, an information length = 48960 bits, a parity length = 16320 bits, and the number of rows = 16320 bits. Note that the procedure for generating the parity check matrix H is not limited to the order shown in steps S11 to S15. The code length N and the information length of the parity check matrix H are integer multiples of the packet length of the input packet. Any length is acceptable.

  Returning to FIG. 4, the description of the operation of the encoding device 110 is continued. A description will be given with reference to FIG. 7 conceptually showing the structure of a packet processed by the encoding device 110.

  After the check matrix H is generated, the RS encoding unit 111 inputs MPEG2-TS packets corresponding to the number P of packets from the TS input unit 101 (step S16). Each packet length of the MPEG2-TS input here is 188 bytes, and the packet length for the number of packets P is 188 × 8 × P bits (FIG. 7A).

  Further, the RS encoding unit 111 performs RS (204, 188) encoding of P-packet MPEG2-TS packets (step S17). More specifically, MPEG2-TS packets having a length of 188 bytes are RS (204, 188) encoded one by one, and are encoded P times in total. As a result, P packets having an information length of 188 bytes and an RS parity length of 16 bytes, which are RS (204, 188) encoded, are generated (FIG. 7B).

  Subsequently, the buffer unit 112 temporarily stores MPEG2-TS packets corresponding to the number P of RS (204, 188) encoded packets (step S18). Here, the bit length of the temporarily stored data is 204 × 8 × P bits (FIG. 7C).

  Next, the LDPC encoding unit 114 reads the parity check matrix H (FIG. 7D) from the parity check matrix generation unit 113, and the MPEG2-TS corresponding to the number P of packets stored in the buffer 112 is the parity check matrix H. Is used to perform LDPC encoding and parity calculation is performed (step S19). As a result, an LDPC code as shown in FIG. The LDPC code obtained here includes an information portion of information length N × R = 204 × 8 × P bits and an LDPC parity of parity length = N × (1-R) bits. Here, the information part and the LDPC parity correspond respectively to the information part and the parity part of the second encoded packet described in the claims.

  Further, the LDPC encoding unit 114 determines whether or not the encoding is completed (step S20). When it is determined that the encoding is completed, the encoding process ends. On the other hand, if it is not determined that the encoding is completed, the process returns to step S16, and the above-described encoding process is executed.

Next, frequency utilization efficiency will be described. When QPSK and 8PSK are used as modulation schemes, the frequency use efficiency e in the present embodiment is expressed by Equation (5). Here, r indicates a constant depending on the modulation method, r = 2 in QPSK, and r = 3 in 8PSK.

  FIG. 8 shows the relationship between the frequency utilization efficiency and the coding rate R when the QPSK and 8PSK modulation schemes are used. In FIG. 8, for example, when the coding rate R = 3/4, the frequency utilization efficiencies in QPSK and 8PSK are “1.38” and “2.07”, respectively. Therefore, transmitting apparatus 100 in the present embodiment can transmit a signal of 1.38 bits per phase point in QPSK modulation and 2.07 bits per phase point in 8PSK modulation.

  Next, the result of simulating the transmission characteristics when the QPSK and 8PSK modulation schemes are used will be described. FIG. 9 shows bit error rate versus C / N (Carrier) in an additive white Gaussian noise (AWGN) environment in QPSK and 8PSK when encoding is performed by encoding apparatus 110 in the present embodiment. / Noise) characteristics are simulated for coding rates R = 7/10 and 4/5. Note that the sum-product decoding method was used as a decoding algorithm.

In FIG. 9, the C / N at a desired bit error rate is compared for a QPSK modulation method without error correction indicated by a black triangle symbol or an 8PSK modulation method without error correction indicated by a black square symbol. Thus, the coding gain can be obtained. For example, in a QPSK modulation scheme with a coding rate R = 7/10 indicated by a white circle symbol, focusing on the point that the bit error rate is 1 × 10 ⁻⁶ , the C / C is higher than the QPSK modulation scheme without error correction. N is improved by 10 dB, and the coding gain in this case is 10 dB. Similarly, when the coding gain in the QPSK modulation method with the coding rate R = 4/5 and the 8PSK modulation method with the coding rate R = 7/10 and 4/5 is obtained, the result shown in FIG. 10 is obtained. It can be seen that the coding apparatus 110 in the embodiment can obtain a relatively high coding gain.

Next, FIG. 11 shows simulation results comparing the coding gains in the QPSK and 8PSK modulation schemes with those of the conventional ISDB-S modulation scheme when encoding is performed by the encoding apparatus 110 according to the present embodiment. Shown in In addition, the result shown by FIG. 11 is a thing with the same frequency utilization efficiency, and compared. In addition, since the bit error rate characteristic in the QPSK and 8PSK modulation schemes changes sharply after 1 × 10 ⁻⁶ (see FIG. 9), it becomes error-free when C / N is increased by 0.1 dB or more. Since it is not easy to calculate the bit error rate strictly when error free, the value obtained by adding 0.1 dB to C / N when the bit error rate is 1 × 10 ⁻⁶ is defined as required C / N. Similarly, in ISDB-S, the required C / N is a point where the bit error rate after Viterbi decoding becomes 2 × 10 ⁻⁴ when error-free by RS (204, 188) code which is an outer code. .

  As a result of the simulation, as shown in FIG. 11 (a), in the QPSK modulation method with the coding rate R = 7/10 in the present embodiment, the QPSK modulation method with the coding rate R = 2/3 in ISDB-S. It was found that the coding gain can be improved by 1.2 dB. Also, as shown in FIG. 11 (b), the 8PSK modulation scheme with coding rate R = 7/10 in the present embodiment is more than the TC8PSK modulation scheme with coding rate R = 2/3 in ISDB-S. It was found that the coding gain can be improved by 1.0 dB.

  As described above, according to transmitting apparatus 100 in the present embodiment, since it is configured to include encoding apparatus 110 having RS encoding section 111 and LDPC encoding section 114, the usage frequency is compared in the existing broadcasting system. It is possible to obtain a coding gain peculiar to an LDPC code that is extremely higher than that of other systems while matching with a high RS (204, 188) code.

  Further, according to transmitting apparatus 100 in the present embodiment, a configuration in which RS (204, 188) code, which is relatively frequently used in the existing broadcasting system, and LDPC code, which is a powerful error correction code, are concatenatedly encoded. Therefore, it is possible to use a coding device having a simpler structure and cheaper than the conventional one that concatenately codes a code other than the RS (204, 188) code and the LDPC code, thereby reducing the manufacturing cost. be able to.

  Also, according to coding apparatus 110 in the present embodiment, parity check matrix generation section 113 has a code length and an information length that are integral multiples of the packet length of an RS (204, 188) coded packet. The parity check matrix H is generated, and the LDPC encoding unit 114 is configured to encode the RS (204, 188) encoded packet with the LDPC code based on the generated check matrix H. As described above, it is possible to perform LDPC encoding on a packet basis without dividing the packet on a predetermined bit basis. Therefore, coding apparatus 110 in the present embodiment can perform concatenated coding of LDPC code and RS code without adding a new apparatus.

  In the above-described embodiment, the RS (204, 188) code has been described as an example of the RS code. However, the present invention is not limited to this, and a packet of a packet to be RS-encoded. The length and the parity length of RS encoding can be arbitrarily set.

  In the above-described embodiment, MPEG2-TS has been described as an example of encoding target data. However, the present invention is not limited to this, and the same applies to data other than MPEG2-TS. The effect is obtained.

  In the above-described embodiment, the example in which the encoding apparatus 110 according to the present invention is applied to the transmission apparatus 100 has been described. However, the present invention is not limited to this, and the LDPC code, the RS code, The same effect can be obtained by applying to the one that performs concatenated encoding. For example, even when the encoding device 110 according to the present invention is applied to a data transmission system that transmits data via the Internet or a storage device that stores predetermined data, the same effect as described above can be obtained.

(Second Embodiment)
First, the configuration of the decoding apparatus according to the present invention will be described. Note that a receiving apparatus including the decoding apparatus according to the present invention will be described as an example. This receiving apparatus receives and decodes the data transmitted by the transmitting apparatus 100 (see FIG. 1) in the first embodiment, and a description overlapping that in the first embodiment is omitted.

  As shown in FIG. 12, receiving apparatus 200 according to the present embodiment includes receiving section 201 that receives data concatenated by LDPC code and RS code, demodulating section 202 that demodulates received data, and demodulation. A decoding device 210 that decodes the decoded data, and an output unit 203 that outputs the decoded data.

  The receiving unit 201 includes, for example, a receiving antenna and a receiving circuit, and receives MPEG2-TS data transmitted from the transmitting apparatus 100 according to the first embodiment. The MPEG2-TS data is data that is concatenated and encoded by an LDPC code and an RS code in the transmission apparatus 100 and then modulated by a predetermined modulation method.

  The demodulating unit 202 includes, for example, a QPSK demodulating circuit or an 8PSK demodulating circuit, and demodulates data received by the receiving unit 201 and outputs the demodulated data to the decoding device 210.

  The decoding apparatus 210 includes a first buffer unit 211 that temporarily stores demodulated data, an encoded information storage unit 212 that stores information related to encoding in the transmission apparatus 100 according to the first embodiment, and , An LDPC decoding unit 213 for decoding with an LDPC code, a second buffer unit 214 for temporarily storing LDPC-decoded data, and an RS decoding unit 215 for decoding with an RS code. Note that the decryption apparatus 210 can be realized by a configuration that performs software operations using, for example, a DSP, or a hardware circuit that uses, for example, an LSI.

  The first buffer unit 211 and the second buffer unit 214 are configured by a semiconductor memory, for example.

  The encoded information storage unit 212 is configured by a semiconductor memory, for example, and stores information related to encoding when the received data is encoded in the transmission apparatus 100 (hereinafter referred to as “encoded information”). ing. The encoded information storage unit 212 constitutes encoded information storage means of the present invention.

Specifically, the coding information stored in coding information storage section 212 includes parity check matrix information, coding rate information, and packet number information. Here, the parity check matrix information refers to information related to the parity check matrix H for the LDPC code generated by the parity check matrix generation unit 113 in the first embodiment. Further, the coding rate information is information indicating the coding rate R in the first embodiment. The packet number information refers to information indicating the packet numbers P _max and P in the first embodiment. The encoded information storage unit 212 may store only information indicating the packet number P as the packet number information.

  The LDPC decoding unit 213 obtains check matrix information and coding rate information from the coding information storage unit 212. Also, the LDPC decoding unit 213 reads data of a predetermined number of bits from the first buffer unit 211, and decodes the read data based on the check matrix information and the coding rate information, for example, by the sum-product decoding method. It has become. Note that the LDPC decoding unit 213 constitutes the first decoding means of the present invention.

  The RS decoding unit 215 acquires packet number information from the encoded information storage unit 212. The RS decoding unit 215 reads data of a predetermined number of bits from the second buffer unit 214, and performs RS decoding of the read data based on the packet number information. Note that the RS decoding unit 215 constitutes the second decoding means of the present invention.

  The output unit 203 includes, for example, a video signal and audio signal processing device, a display, a speaker, and the like, and outputs video and audio based on the MPEG2-TS data decoded by the decoding device 210. .

  Next, the operation of receiving apparatus 200 in the present embodiment will be described using FIG.

  First, MPEG2-TS data is received by the reception unit 201 and output to the demodulation unit 202. Next, the demodulating unit 202 demodulates data received by, for example, QPSK demodulation, and outputs the demodulated data to the decoding device 210.

  Subsequently, LDPC decoding and RS decoding are performed by the decoding device 210 and output to the output unit 203. The detailed operation of the decryption apparatus 210 will be described later. Then, the output unit 203 outputs the decoded MPEG2-TS data as video and audio.

  Next, the operation of decoding apparatus 210 in the present embodiment will be described using FIGS. FIG. 13 is a flowchart showing the operation of the decoding apparatus 210 in the present embodiment.

First, the encoded information is stored in the encoded information storage unit 212 as shown in steps S31 and S32 of FIG. Specifically, parity check matrix information and coding rate information determined by coding apparatus 110 in the first embodiment, that is, information related to parity check matrix H and coding rate R are stored in coding information storage section 212. (Step S31). Similarly, packet number information, that is, information indicating the packet numbers P _max and P in the first embodiment is stored in the encoded information storage unit 212 (step S32).

  Subsequently, the parity check matrix information and the coding rate information are read by the LDPC decoding unit 213 (step S33). Further, the RS decoding unit 215 reads the packet number information (step S34).

  Next, the N-bit data from the demodulation unit 202 is temporarily stored by the first buffer unit 211 (step S35). Here, the N-bit data is data corresponding to the code length of the LDPC-encoded data in the transmission apparatus 100.

  Subsequently, the LDPC decoding unit 213 reads N-bit data from the first buffer unit 211, performs decoding calculation by, for example, the sum-product decoding method, and the decoded output N × R bit data is the second data. The data is stored in the buffer unit 214 (step S36).

  Next, the N × R bit data is read from the second buffer unit 214 by the RS decoding unit 215, and RS decoding is performed P times every 204 × 8 bits (step S37).

  Then, the RS decoding unit 215 determines whether or not the decoding is completed (step S38). When it is determined that the decoding is completed, the decoding process is ended. On the other hand, if it is not determined that the decoding has been completed, the process returns to step S35, and the above-described decoding process is executed.

  Next, the results of evaluating the decoding calculation amount will be described in order to compare the circuit scale when the decoding apparatus 210 according to the present embodiment is configured with hardware with the conventional one.

In decoding of an LDPC code, it is known that as the number of “1” included in a parity check matrix increases, the amount of decoding calculation per sum-product decoding increases. Since the increase in the amount of decoding calculation is in a trade-off relationship with the hardware scale, it is desirable that decoding can be performed with as few calculations as possible from the viewpoint of hardware implementation that requires a gigabit transmission rate. In addition, the LDPC decoding part is dominant in most of the decoding calculation amount in the concatenated encoding method including the LDPC code. Therefore, for the parity check matrix used in decoding apparatus 210 in the present embodiment and the parity check matrix used in conventional DVB-S2, the number of summations and multiplications required for one decoding calculation of sum-product decoding was evaluated. . Here, if the number of calculations C required for one decoding is defined as the sum of the number of additions and multiplications required for likelihood ratio calculation as an evaluation index, the number of calculations C can be calculated by Equation (6).

  Here, m and n indicate the number of rows and the number of columns of the parity check matrix, respectively. A (i) indicates the total number of “1” included in the i-th row of the parity check matrix, and B (j) indicates the total number of “1” included in the j-th column of the parity check matrix.

  FIG. 14 shows the calculation count C when the coding rate is 1/4, 1/2, 3/4, 4/5, and the calculation amount ratio r of the decoding apparatus 210 in the present embodiment for the DVB-S2 system. It is shown. As shown in FIG. 14, for example, when the coding rate R = 4/5, the decoding apparatus 210 according to the present embodiment can reduce the decoding calculation amount for one time to 55% or less of the DVB-S2 method. Therefore, decoding can be performed with a much smaller number of calculations than in the DVB-S2 system. Therefore, when the decoding apparatus 210 according to the present embodiment is configured by hardware, the circuit scale can be reduced as compared with the DVB-S2 system, and the manufacturing cost can be reduced.

  As described above, according to receiving apparatus 200 in the present embodiment, LDPC decoding section 213 performs LDPC decoding based on parity check matrix information and encoded information stored in encoded information storage section 212, and Since the RS decoding unit 215 is configured to perform RS decoding based on the packet number information stored in the encoded information storage unit 212, the LDPC code and the RS code are concatenated without adding a new device. Encoded data can be received and decoded.

  Further, according to receiving apparatus 200 in the present embodiment, RS (204, 188) code that is relatively frequently used in the existing broadcasting system and LDPC code that is a strong error correction code are concatenated. Since the data is configured to be decoded, a decoding device having a simpler structure and cheaper than the conventional one that decodes data in which a code other than the RS (204, 188) code and the LDPC code are concatenated-encoded is provided. The manufacturing cost can be reduced.

  Also, according to decoding apparatus 210 in the present embodiment, encoded information storage section 212 has a code length and information that is an integral multiple of the packet length of the RS (204, 188) encoded packet in transmitting apparatus 100. Since the parity check matrix information and the coding rate information related to the long parity check matrix H are stored, the LDPC decoding unit 213 is configured to decode with the LDPC code based on the parity check matrix information and the coding rate information. As in the prior art, it is possible to perform LDPC decoding on a packet basis without decoding a packet divided on a predetermined bit basis for each division unit. Therefore, decoding apparatus 210 according to the present embodiment can decode data in which the LDPC code and the RS code are concatenated and encoded without adding a new apparatus.

  In the above-described embodiment, an example in which data encoded with RS (204, 188) code is decoded has been described. However, the present invention is not limited to this, and RS encoding is not limited thereto. Even when the packet length of the target packet or the parity length of the RS encoding is arbitrarily set, the data can be decoded.

  In the above-described embodiment, MPEG2-TS has been described as an example of data to be decoded. However, the present invention is not limited to this, and the same applies to data other than MPEG2-TS. The effect is obtained.

  In the above-described embodiment, the decoding apparatus 210 according to the present invention is described as an example applied to the receiving apparatus 200. However, the present invention is not limited to this, and an LDPC code, an RS code, The same effect can be obtained if it is applied to data for decoding concatenated data. For example, even when the decoding device 210 according to the present invention is applied to a data transmission system that transmits data via the Internet or a storage device that stores predetermined data, the same effect as described above can be obtained.

  As described above, the encoding device and the decoding device according to the present invention have the effect that the LDPC code and the RS code can be concatenated and decoded without adding a new device. The present invention is useful as an encoding device that encodes data such as video and audio, and a decoding device that decodes data encoded by the encoding device.

The block diagram of the transmitter in the 1st Embodiment of this invention The figure which shows an example of the check matrix H which a check matrix production | generation part produces | generates in the 1st Embodiment of this invention. Diagram showing an example of a configuration of a parity part matrix H _T included in the check matrix H shown in FIG. 2 The flowchart which shows operation | movement of an encoding apparatus in the 1st Embodiment of this invention. In the first embodiment of the present invention, the number of MPEG2-TS packets and the row and column weights of the parity check matrix H with respect to the coding rate R when the regular LDPC code is applied to the information submatrix _HA of the parity check matrix H Diagram showing distribution The figure which shows an example of the check matrix H to which the regular LDPC code of the column weight 3 is applied in the 1st Embodiment of this invention. The figure which shows notionally the structure of the packet which the encoding apparatus processes in the 1st Embodiment of this invention. The figure which shows the relationship between the frequency utilization efficiency at the time of using the modulation system of QPSK and 8PSK, and the encoding rate R in the 1st Embodiment of this invention. The figure which shows the bit error rate versus C / N characteristic by the encoding apparatus in the 1st Embodiment of this invention. The figure which shows the encoding gain in the point which a bit error rate becomes ^1x10-6 in the 1st Embodiment of this invention. The figure which shows the simulation result which compared the coding gain in the modulation system of QPSK and 8PSK with the encoding system of ISDB-S at the time of encoding with the encoding apparatus in the 1st Embodiment of this invention. The block diagram of the receiver in the 2nd Embodiment of this invention The flowchart which shows operation | movement of a decoding apparatus in the 2nd Embodiment of this invention. The figure which shows the frequency | count C of calculation in each encoding rate in the 2nd Embodiment of this invention, and the computational complexity ratio r of the decoding apparatus of this invention with respect to DVB-S2 system. The figure which shows the error rate characteristic by the conventional RS (204,188) code | symbol The figure which shows an example of the check matrix for the conventional LDPC codes

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Transmission apparatus 101 TS input part 102 Modulation part 103 Transmission part 110 Encoding apparatus 111 RS encoding part (1st encoding means)
112 Buffer unit 113 Check matrix generation unit (Check matrix generation means)
114 LDPC encoding unit (second encoding means)
200 Receiving Device 201 Receiving Unit 202 Demodulating Unit 203 Outputting Unit 210 Decoding Device 211 First Buffer Unit 212 Encoded Information Storage Unit (Encoded Information Storage Unit)
213 LDPC decoding unit (first decoding means)
214 Second buffer unit 215 RS decoding unit (second decoding means)

Claims (4)

First encoding means for encoding an input packet with a Reed-Solomon code and outputting a first encoded packet, and generating a check matrix having a code length that is an integer multiple of the packet length of the first encoded packet A parity check matrix generation unit and a second encoding unit that encodes the first encoded packet with a low-density parity check code based on the parity check matrix and outputs a second encoded packet. Encoding device. The first encoded packet includes an information part to be encoded by the Reed-Solomon code and a parity part generated by encoding the Reed-Solomon code, and the bit length of the information part is 188 bytes, The encoding apparatus according to claim 1, wherein the bit length of the parity part is 16 bytes. The second encoded packet includes an information part to be encoded by the low density parity check code and a parity part generated by encoding the low density parity check code, and the information part and the bit of the parity part The encoding device according to claim 1 or 2, wherein each of the lengths is a predetermined integer multiple of a packet length of the first encoded packet. A decoding device for decoding data concatenated and encoded with a Reed-Solomon code and a low-density parity check code,
Information related to a check matrix having a code length that is an integer multiple of a packet length of a packet encoded with the Reed-Solomon code, information related to a coding rate in encoding using the low-density parity check code, and the code length The low-density parity check code based on the information on the parity check matrix and the information on the coding rate. A decoding apparatus comprising: a first decoding unit that performs decoding according to 1; and a second decoding unit that performs decoding by the Reed-Solomon code based on information relating to the number of packets.