JP2017005302A - Receiving apparatus and chip using concatenated code - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the measurement accuracy of packet error rate for evaluating the characteristics of mobile reception when performing inner code decoding and outer code decoding of concatenated coded data.SOLUTION: An inner code decoding unit 23 of a receiving apparatus 2 performs LDPC code decoding processing on the concatenated encoded data. An outer code decoding unit 24 determines whether error correction is possible for each data area of the concatenated encoded data LDPC code-decoded, and performs BCH code decoding processing on the divided data in the data area. The inner code decoding unit 23 and the outer code decoding unit 24 repeatedly perform decoding processing. An error presence/absence judgment unit 25 sets error information indicating whether there is an error in the divided data. A packet header editing unit 26 extracts TS packets from the divided data for each divided data, and on the basis of the error information, sets flags of error indicators in all the TS packets extracted from the corresponding divided data.SELECTED DRAWING: Figure 7

Description

  The present invention relates to a receiving apparatus and a chip for decoding data such as concatenated encoded video and audio.

  ISDB-T (Integrated Services Digital Broadcasting-Terrestrial), a Japanese terrestrial digital broadcasting system, realizes high-definition (registered trademark) broadcasting (or multiple standard-definition broadcasting) for fixed reception. In the next-generation terrestrial digital broadcasting system, instead of the conventional Hi-Vision (registered trademark), 3D Hi-Vision broadcasting or Super Hi-Vision with 16 times the resolution of Hi-Vision (registered trademark) will provide services with more information. Is required.

  In recent years, LDPC codes (Low Density Parity Check Codes) have been adopted in many transmission systems as high-performance error correction codes that approach the Shannon limit. It is also known that error correction capability is improved by using a concatenated code that combines an LDPC code and a BCH code (Bose Chaudhuri Hocquenghem Code). This concatenated code has already been standardized in DVB-T2 and ARIB STD-B44 (standard transmission system standard for advanced broadband satellite digital broadcasting) and the like.

  FIG. 16 is a diagram showing the configuration of conventional concatenated encoded data, and shows data of one code length combining an LDPC code and a BCH code. The concatenated encoded data is composed of data to be transmitted, a parity bit of a BCH code, and a parity bit of an LDPC code. From FIG. 16, it can be seen that in the conventional concatenated encoded data, the parity bit of the BCH code and the parity bit of the LDPC code are concatenated in the concatenated encoded data of one code length.

  When a concatenated code of LDPC code and BCH code is used as an error correction code, the code length of concatenated encoded data applied to a broadcasting system such as DVB-T2 is 10000 bits or more, so that data to be transmitted Stores a plurality of TS packets. The transmission target data includes a plurality of (n) TS packets and null data (null). n is an integer of 2 or more.

  On the other hand, in order to perform characteristic evaluation by mobile reception of terrestrial digital broadcasting, a technique for measuring whether or not an error has occurred in received data in units of TS packets is known. This is because the MPEG2-TS packet header includes one bit of an identifier called an error indicator, and this error indicator is used. The error indicator is an identifier indicating the presence / absence of a bit error in the TS packet. When an error is detected after error correction processing, the receiving apparatus sets an error indicator flag to ON for the packet header of the TS packet.

  FIG. 17 is a diagram for explaining a conventional concatenated encoding process, and shows a series of processes for performing LDPC encoding after BCH encoding. A transmitting apparatus that generates and transmits concatenated encoded data first generates BCH code parity bits by performing BCH encoding on transmission target data composed of a plurality of TS packets and null data, and generates BCH encoded data. Is generated (step S1801).

  The transmission apparatus performs LDPC encoding on the BCH encoded data to generate LDPC code parity bits, and generates LDPC encoded data (here, concatenated encoded data) (step S1802).

  The concatenated encoded data generated in this way has the configuration shown in FIG. 16, and is transmitted to the receiving device.

  FIG. 18 is a diagram for explaining conventional concatenated code decoding processing and packet header editing processing, and shows a series of processing for performing BCH code decoding after LDPC code decoding and further editing the packet header of a TS packet. A receiving apparatus that receives and decodes concatenated coded data first performs LDPC code decoding using LDPC code parity bits included in the concatenated coded data, corrects errors in the data and BCH code parity bits, and performs LDPC code decoding. Decoded data (decoded data and BCH code parity bits) is generated (step S1901).

  The receiving apparatus performs BCH code decoding using the BCH code parity bits included in the LDPC code decoded data in order to perform error correction on the bits that could not be error-corrected in the LDPC code decoding process in step S1901, thereby correcting the data error. It is corrected and restored to the original data (step S1902).

  Here, the receiving apparatus determines whether or not error correction is possible in the BCH code decoding process of step S1902 (step S1902-1), and determines that error correction is possible (step S1902-1). : Y), error correction by BCH code decoding is performed (step S1902-2), and data is determined (step S1902-3). The receiving apparatus sets the error indicator flag in the packet header to off for all TS packets included in the data (step S1902-4).

  On the other hand, if it is determined in step S1902-1 that error correction is not possible (step S1902-1: N), the receiving apparatus does not perform error correction by BCH code decoding and makes data indeterminate (step S1902-1). S1902-5). Then, the receiving apparatus sets the error indicator flag in the packet header to ON for all TS packets included in the data (step S1902-6).

  As described above, even if a bit that cannot be corrected by LDPC code decoding remains, data can be determined by correcting the bit of the error by BCH code decoding. Then, the error indicator flag is set to OFF for all TS packets. However, there are cases where the error bit cannot be corrected even by BCH code decoding. In this case, data cannot be determined, and the error indicator flag is set to ON for all TS packets. .

  By the way, although it is generally known that the error correction capability is improved by using the concatenated code, in order to further improve the error correction capability, a method of repeating the decoding process has been proposed (for example, non-patent). Reference 1).

  This technique is performed when the transmitting device performs concatenated coding using a concatenated code that combines a Reed-Solomon code and a convolutional code, and when the receiving device performs error correction by concatenated code decoding by Viterbi decoding and Reed-Solomon decoding. Error correction by code decoding is repeatedly performed. Specifically, definite bit information (information for partially determining the output of Viterbi decoding) is generated from error correction availability information generated by Viterbi decoding and Reed-Solomon decoding, and error correction by concatenated code decoding is performed according to the definite bit information Is repeated.

Saiya, 2 others, “Improvement of Viterbi decoding using RS decoding error correction information”, ITE Technical Report, Vol.35, No.31, BCT2011-53 Jul, 2011)

  As described above, a method of performing error correction using a concatenated code combining an LDPC code and a BCH code has already been put into practical use according to DVB-T2 and the like, and is known to have excellent error correction capability. .

  However, when error correction is performed using a concatenated code, an error in received data when performing characteristic evaluation by mobile reception of digital terrestrial broadcasting cannot be measured with high accuracy. This is because an error in received data can be detected only in data units constituting the concatenated encoded data. Of all TS packets included in the data constituting the concatenated encoded data, even if some TS packets have errors, all TS packets are regarded as having errors.

  For example, in the DVB-T2 standard, if the code length of the LDPC code is 64800 bits and the coding rate = 3/4, the data length is 48600 bits. Since the TS packet is composed of 188 bytes including a 4-byte header, it is 187 bytes (= 1496 bits) excluding the 1-byte header in which the same synchronization data is set. Then, the transmission target data includes 32 TS packets (48600/1496 = 32.48..., N = 32 in FIG. 16). If an error occurs, all 32 TS packets are included. Is considered wrong.

  Further, in the ARIB STD-B44 standard, if the code length of the LDPC code is 44880 bits and the coding rate is 2/3, the data length is 30102 bits. The data to be transmitted includes 20 TS packets (30102/1496 = 20.12..., N = 20 in FIG. 16). If an error occurs, all 20 TS packets are erroneous. It is considered to be.

  Actual errors may not occur in all TS packets, but may occur only in some TS packets. As described above, when error correction is performed using a concatenated code, there is a problem that the error rate of the TS packet is lower than the actual one and the measurement accuracy of the packet error rate is lowered. The packet error rate is an index used for, for example, performance evaluation of an in-vehicle receiver, and is desirably measured with high accuracy.

  Therefore, the present invention has been made to solve the above-described problems, and an object of the present invention is to improve the measurement accuracy of the packet error rate when performing inner code decoding and outer code decoding on concatenated encoded data. An object of the present invention is to provide a receiving device capable of performing the above and a chip mounted on the receiving device.

  In order to solve the above problem, the receiving apparatus according to claim 1 is a concatenated code in which a predetermined number of pieces of divided data including a plurality of packets are subjected to an outer code encoding process and an inner code encoding process. In the receiving device that receives the encoded data and performs the decoding process of the inner code and the outer code on the concatenated encoded data, the concatenated encoded data is obtained by using the inner code parity bit included in the concatenated encoded data. An inner code decoding unit that performs an inner code decoding process on the outer encoded data included in the outer encoded data, and the predetermined number of divided data and outer data included in the outer encoded data that has been decoded by the inner code decoding unit. The number of error bits is calculated for each data area of code parity bits, and the data area where the number of error bits is equal to or less than a predetermined number of bits is used by using the outer code parity bit of the data area. An outer code decoding unit that performs an outer code decoding process on the divided data of the data area, determines the data area on which the outer code decoding process has been performed, and extracts the predetermined number of divided data; and the outer code decoding When the data area including the divided data is determined for each divided data extracted by the section, it is determined that there is no error in the divided data, and the data area including the divided data is not fixed The error presence / absence determination unit that determines that there is an error in the divided data, and the packet is extracted from the predetermined number of pieces of divided data, A flag indicating that the error does not exist is set in all the packets extracted from the divided data, and an error is detected by the error existence determination unit. Then for the determined divided data, all packets extracted from the divided data, characterized in that it comprises, an error setting section for setting a flag indicating that the error is present.

  The receiving apparatus according to claim 2 is the receiving apparatus according to claim 1, wherein the inner code decoding unit inputs concatenated encoded data including the divided data subjected to decoding processing by the outer code decoding unit. The inner code decoding process is performed, and the outer code decoding unit inputs concatenated encoded data including the outer encoded data subjected to the decoding process by the inner code decoding unit, and performs the outer code decoding process. When the inner code decoding unit repeats the inner code decoding process by the inner code decoding unit and the outer code decoding unit by the outer code decoding unit, and the outer code decoding unit determines that all the data areas are fixed Alternatively, when it is determined that the number of decoding processes by the inner code decoding unit and the outer code decoding unit has reached a predetermined upper limit number, the predetermined number of divided data is extracted.

  The receiving apparatus according to claim 3 is the receiving apparatus according to claim 1 or 2, wherein the outer code is a BCH code and the inner code is an LDPC code.

  The receiving apparatus according to claim 4 is the receiving apparatus according to claim 1 or 2, wherein the outer code is a BCH code, the inner code is a spatially coupled LDPC code, the bit size of the divided data, and the space Each row size in a plurality of block matrices on a diagonal line in which parity bits included in a parity check matrix of a combined LDPC code are arranged has the same or an integer multiple relationship.

  Further, the chip of claim 5 receives the concatenated encoded data obtained by performing the encoding process of the outer code on the predetermined number of pieces of divided data and further performing the encoding process of the inner code, Outer encoded data included in the concatenated encoded data using a inner code parity bit included in the concatenated encoded data in a chip mounted on a receiving device that performs inner code decoding processing and outer code decoding processing In contrast, an inner code decoding unit that performs inner code decoding processing, and each data area of the predetermined number of divided data and outer code parity bits included in outer encoded data that has been decoded by the inner code decoding unit. Then, the number of error bits is calculated, and for the data area where the number of error bits is equal to or less than a predetermined number of bits, the outer code parity bit of the data area is used to convert the data area into divided data An outer code decoding unit that performs an outer code decoding process, determines the data area on which the outer code decoding process has been performed, and extracts the predetermined number of divided data; and the division extracted by the outer code decoding unit When the data area including the divided data is determined for each data, it is determined that there is no error in the divided data, and when the data area including the divided data is not determined, An error presence / absence determination unit that determines that an error exists, and a packet is extracted from the predetermined number of pieces of divided data, and the divided data that has been determined by the error presence / absence determination unit to have no error are all A flag indicating that the error does not exist is set in the packet, and the divided data determined to have an error by the error presence / absence determination unit. For, all packets extracted from the divided data, characterized in that it comprises, an error setting section for setting a flag indicating that the error is present.

  As described above, according to the present invention, it is possible to improve the measurement accuracy of the packet error rate when performing inner code decoding and outer code decoding on concatenated encoded data.

It is a block diagram which shows the structure of the transmitter by embodiment of this invention. It is a figure which shows the structure of concatenated encoding data. It is a figure explaining the process of an outer coding part. It is a figure explaining the process of an inner coding part. It is a figure which shows the specific example (1) of connection encoding data. It is a figure which shows the specific example (2) of connection coding data. It is a block diagram which shows the structure of the receiver by embodiment of this invention. It is a flowchart which shows the process of an inner code decoding part and an outer code decoding part. It is a flowchart which shows the detail of the BCH code decoding and definite bit conversion process (process of step S803) in an outer code decoding part. It is a figure explaining the process of an inner code decoding part and an outer code decoding part. It is a flowchart which shows the process of an error presence determination part and a packet header edit part. It is a figure explaining the process of an error presence determination part and a packet header edit part. It is a figure explaining the process of the error presence determination part and packet header edit part in case a TS packet straddles two division | segmentation data. (1) is a diagram showing a parity check matrix of an LDPC code. (2) is a diagram illustrating a parity check matrix of a spatially coupled LDPC code. It is a figure explaining the mode of likelihood propagation at the time of using a space coupling LDPC code. It is a figure which shows the structure of the conventional connection coding data. It is a figure explaining the conventional connection encoding process. It is a figure explaining the conventional concatenated code decoding process and a packet header edit process.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings. In the embodiment of the present invention, a BCH code is given as an example of an outer code, and an LDPC code is given as an example of an inner code. The LDPC code includes a new code system such as a spatially coupled LDPC code. The present invention is not limited to this example, and is also applicable to cases where other outer codes and inner codes are used.

[Transmitter]
First, a transmission device according to an embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a configuration of a transmission apparatus. The transmission device 1 includes an encoder 10, a modulation unit 13, and a transmission unit 14. The encoder 10 includes an outer encoding unit 11 and an inner encoding unit 12.

  The outer encoding unit 11 of the encoder 10 receives a plurality of TS packets and equally divides the transmission target data into a predetermined number of transmission target data obtained by adding a predetermined amount of null data to the plurality of TS packets. Then, a predetermined number of divided data is generated. Then, the outer encoding unit 11 performs an encoding process of a BCH code that is an outer code for each divided data, and generates a BCH code parity bit. Then, the outer encoding unit 11 generates encoded data by adding the BCH code parity bit to the divided data, and generates BCH encoded data (outer encoded data) by concatenating a predetermined number of encoded data. The BCH encoded data is output to the inner encoding unit 12. Details of the processing of the outer encoding unit 11 will be described later.

  The inner encoding unit 12 receives the BCH encoded data from the outer encoding unit 11, performs an encoding process on the BCH encoded data using a parity check matrix of an LDPC code that is an inner code, and LDPC code parity bits. Is generated. The inner encoding unit 12 adds LDPC code parity bits to the BCH encoded data to generate concatenated encoded data that is LDPC encoded data, and outputs the concatenated encoded data to the modulation unit 13. Details of the processing of the inner encoding unit 12 will be described later. In this way, concatenated encoded data is generated by the encoder 10.

  The modulation unit 13 receives the concatenated encoded data from the inner encoding unit 12, performs modulation processing on the concatenated encoded data by a predetermined modulation scheme such as QPSK (Quadrature Phase Shift Keying), and transmits the modulated signal to the transmission unit 14. Output to. The transmission unit 14 receives the modulation signal from the modulation unit 13, converts the modulation signal into a predetermined radio signal, and transmits the radio signal from the transmission antenna.

(Concatenated encoded data)
Next, the configuration of the concatenated encoded data generated by the encoder 10 of the transmission apparatus 1 shown in FIG. 1 will be described in detail. FIG. 2 is a diagram showing the configuration of concatenated encoded data, and shows the configuration of data of one code length that combines an LDPC code and a BCH code. The predetermined number by which the data to be transmitted is divided by the outer encoding unit 11 is set to 3.

  The concatenated encoded data includes the first data obtained by dividing the transmission target data into a predetermined number (3 in the case of FIG. 2), the BCH code parity bit for the first data, the second data divided, 2 BCH code parity bits for the second data, divided third data, BCH code parity bits for the third data, and LDPC code parity bits.

  As shown in FIG. 2, the concatenated coded data is obtained by adding the BCH code parity bit in units of divided data obtained by dividing the transmission target data, in which the BCH code parity bit and the LDPC code parity bit are not connected. I understand that. In this concatenated coded data, the code length, parity bit length (LDPC code parity bit length), and data length (data bit length) are the same as those of the conventional concatenated coded data shown in FIG. The coding rate is not different from the conventional one.

(Processing of outer encoding unit 11)
Next, the processing of the outer encoding unit 11 shown in FIG. 1 will be described in detail. FIG. 3 is a diagram for explaining the processing of the outer encoding unit 11. First, the outer encoding unit 11 receives a plurality of TS packets, adds a predetermined number of null data to the plurality of TS packets (step S301), and transmits a predetermined number of the transmission target data (this example). In this case, the data is equally divided into 3) data 1, 2, 3 (step S302).

  Outer encoding section 11 performs BCH encoding processing on data 1 and generates BCH code parity bits for data 1 (step S303). In addition, the outer encoding unit 11 performs BCH encoding processing on the data 2 and generates BCH code parity bits for the data 2 (step S304). In addition, the outer encoding unit 11 performs BCH encoding processing on the data 3, and generates BCH code parity bits for the data 3 (step S305).

  Outer encoding section 11 adds corresponding BCH code parity bits to data 1, 2, and 3, concatenates three encoded data, generates BCH encoded data, and converts BCH encoded data into The data is output to the inner encoding unit 12 (step S306).

  As a result, BCH code parity bits are added in units of each of the divided data 1, 2 and 3, and BCH encoded data is generated.

(Processing of inner encoding unit 12)
Next, the process of the inner encoding unit 12 shown in FIG. 1 will be described in detail. FIG. 4 is a diagram for explaining the processing of the inner encoding unit 12. First, the inner encoding unit 12 inputs BCH encoded data (step S401), performs LDPC encoding processing on the BCH encoded data, and generates LDPC code parity bits (step S402).

  The inner encoding unit 12 generates concatenated encoded data by adding LDPC code parity bits to the BCH encoded data, and outputs the concatenated encoded data to the modulating unit 13 (step S403).

(Specific example of concatenated encoded data)
Next, a specific example of concatenated encoded data generated by the encoder 10 of the transmission apparatus 1 shown in FIG. 1 will be described.

  FIG. 5 is a diagram illustrating a specific example (1) of concatenated encoded data, and FIG. 6 is a diagram illustrating a specific example (2) of concatenated encoded data. 5 and 6 show an example in which the code length of the concatenated coded data is 44880 bits, the coding rate (nominal) is 2/3, and the transmission target data is divided into two, and ARIB STD-B44 It conforms to the specified code length and coding rate.

  In the example of the conventional concatenated encoded data shown in FIG. 16, a BCH code (12 bits of error correction) using a 16th-order generator polynomial is used, whereas the specific example (1) shown in FIGS. In (2), a 14th-order generator polynomial is used twice. In the embodiment of the present invention, since the number of error corrections is 6 bits each, the error correction capability is not changed as compared with the prior art. In the embodiment of the present invention, since the order of the generator polynomial is reduced, the BCH code parity bit length (84 + 84 = 168 bits) is shorter than the conventional example (192 bits), and the scale of the decoding circuit can be reduced. it can.

  In general, a TS packet has a fixed length. For this reason, TS packets cannot always be stored so as to fit in the areas of data 1 and 2 shown in FIGS. In the specific example (1) in FIG. 5, the tenth TS packet straddles the two data 1 and 2 at the boundary of the divided data. The 0th to 9th TS packets and a part of the 10th TS packet are stored in the data 1 area, the remaining part of the 10th TS packet, the 11th to 19th TS packets and the null data are data 2 It is stored in the area. In the specific example (2) of FIG. 6, null data is stored in each of the data 1 and 2 areas. The 0th to 9th TS packets and null data are stored in the data 1 area, and the 10th to 19th TS packets and null data are stored in the data 2 area.

  That is, the outer encoding unit 11 and the inner encoding unit 12 perform processing in units of 20 TS packets, and connect the specific example (1) shown in FIG. 5 or the specific example (2) shown in FIG. Generate encoded data.

  In the example of FIG. 5, the outer encoding unit 11 inputs the 0th to 19th TS packets, adds 686-bit null data to the end of these TS packets, and generates data to be transmitted. The outer encoding unit 11 equally divides the transmission target data including the 0th to 19th TS packets and the null data into two. The outer encoding unit 11 sets the 0th to 9th TS packets and a part of the 10th TS packet as data 1, the remaining part of the 10th TS packet, the 11th to 19th TS packets and null data as data. 2, two divided data (data 1, 2) are generated. Then, the outer encoding unit 11 performs an encoding process of a BCH code that is an outer code for each divided data, and generates BCH encoded data. By performing the LDPC code encoding process by the inner encoding unit 12, the concatenated encoded data shown in FIG. 5 is generated.

  In the example of FIG. 6, the outer encoding unit 11 inputs the 0th to 19th TS packets, adds 343-bit null data to the end of the 0th to 9th TS packets, and also adds the 10th to 19th TS packets. Is appended with 343-bit null data to generate data to be transmitted. The outer encoding unit 11 equally divides the transmission target data including the 0th to 9th TS packets, the null data, the 10th to 19th TS packets, and the null data into two. The outer encoding unit 11 generates two pieces of divided data (data 1 and 2) using the 0th to 9th TS packets and null data as data 1, and the 10th to 19th TS packets and null data as data 2. Then, the outer encoding unit 11 performs encoding processing of the BCH code that is the outer code on the divided data for each divided data, and generates BCH encoded data. By performing the LDPC code encoding process by the inner encoding unit 12, the concatenated encoded data shown in FIG. 6 is generated.

  In FIG. 5 and FIG. 6, null data is added to the TS packet. However, a header or stuffing defined by ARIB STD-B44 may be added instead of the null data.

  As described above, according to the transmission device 1 of the embodiment of the present invention, the outer encoding unit 11 divides data to be transmitted including a plurality of TS packets into a predetermined number, and each of the predetermined number of divided data. A BCH encoding process is performed on the divided data, and BCH code parity bits are added to the divided data to generate BCH encoded data. Then, the inner encoding unit 12 performs LDPC encoding processing on the BCH encoded data, adds LDPC code parity bits to the BCH encoded data, and generates concatenated encoded data.

  As a result, when the concatenated code decoding process of LDPC code decoding and BCH code decoding is performed by the receiving apparatus that receives the concatenated encoded data from the transmitting apparatus 1, error correction in units of divided data is performed in the BCH code decoding process. Therefore, it is possible to set an error of the TS packet for each divided data.

  Therefore, conventionally, an error of a TS packet is set for each piece of concatenated encoded data. However, in the embodiment of the present invention, since an error of a TS packet can be set for each divided data, the packet error rate is measured. The accuracy can be improved.

  In addition, it is possible to restore the original data with high accuracy by repeatedly using the BCH code decoding result again in the LDPC code decoding for the data subjected to the concatenated coding using the BCH code and the LDPC code. . Since the error correction capability is improved as compared with the conventional case where the data can be indeterminate, the decoding performance of the concatenated encoded data can be further improved, and the required C / N can be reduced.

[Receiver]
Next, a receiving apparatus according to an embodiment of the present invention will be described. FIG. 7 is a block diagram illustrating a configuration of the receiving device. The receiving device 2 includes a receiving unit 21, a demodulating unit 22, and a decoder 20. The decoder 20 includes an inner code decoding unit 23, an outer code decoding unit 24, an error presence / absence determination unit 25, and a packet header editing unit (error setting unit) 26.

  The receiving unit 21 receives a radio signal transmitted from the transmitting apparatus 1 shown in FIG. 1 by a receiving antenna, converts the radio signal into a modulated signal, and outputs the modulated signal to the demodulating unit 22. The demodulation unit 22 receives the modulation signal from the reception unit 21, performs demodulation processing corresponding to a predetermined modulation method in the modulation unit 13 of the transmission device 1 on the modulation signal, and generates demodulated concatenated encoded data Output to the decoder 20.

  The inner code decoding unit 23 of the decoder 20 inputs the concatenated coded data demodulated from the demodulating unit 22 or the concatenated coded data (concatenated code-decoded concatenated data) BCH code-decoded from the outer code decoding unit 24. (Encoded data) is input.

  The inner code decoding unit 23 uses the LDPC code parity bits included in the input concatenated encoded data and the parity check matrix of the LDPC code to convert the BCH encoded data (outer encoded data) included in the input concatenated encoded data. On the other hand, decoding processing of the LDPC code which is an inner code is performed. As a result, the BCH encoded data is subjected to LDPC code decoding, and errors in the BCH encoded data are corrected. Then, the inner code decoding unit 23 outputs concatenated encoded data (concatenated encoded data subjected to LDPC code decoding) including BCH encoded data subjected to LDPC code decoding to the outer code decoding unit 24. Details of the processing of the inner code decoding unit 23 will be described later.

  The outer code decoding unit 24 receives the concatenated encoded data that has been subjected to LDPC code decoding from the inner code decoding unit 23, and generates a BCH code for each divided data and BCH code parity bit data area included in the input concatenated encoded data. Using the parity bits, the division data is subjected to a decoding process of a BCH code that is an outer code. As a result, the divided data in the data area is BCH code-decoded, and errors in the divided data are corrected.

  Here, the outer code decoding unit 24 determines how many errors exist in the data to be corrected during the BCH code decoding process. That is, the outer code decoding unit 24 calculates the number of error bits for each data area, and determines whether or not the error of the divided data can be corrected based on the number of error bits.

  The outer code decoding unit 24 determines, for each data area, whether or not an error in the data area can be corrected, performs a decoding process on the divided data determined to be error-correctable, and determines the data area Bitify (determine the data area). The outer code decoding unit 24 does not perform decoding processing on the divided data determined to be uncorrectable.

  Until the outer code decoding unit 24 determines that error correction is possible for all data areas, or until the number of decoding processes by the inner code decoding unit 23 and the outer code decoding unit 24 reaches a predetermined upper limit number of times, the BCH The concatenated encoded data that has been code-decoded is output to the inner code decoding unit 23. As a result, the inner code decoding unit 23 performs LDPC code decoding on the BCH encoded data including the data area that has been made into definite bits.

  In LDPC code decoding, since decoding of a certain data area is performed using bits of a plurality of data areas, the error-corrected high-accuracy bit in the data area that has been made into a definite bit is converted to other data that has not been made into a definite bit. It has the property of propagating to a region. Therefore, when the BCH encoded data including the data area that is definite bit and the data area that is not definite bit is LDPC code decoded, the bit in the data area that is not definite bit is the bit of the data area that is definite bit The accuracy is increased under the influence of. Thereby, in the BCH code decoding process in the outer code decoding unit 24 in the subsequent stage, there is a high possibility that it is determined that error correction is possible for a data area that has not been converted into definite bits.

  The outer code decoding unit 24 determines that error correction is possible for all the data areas, and if all the data areas are determined as bits, or if it is determined that the number of decoding processes has reached a predetermined upper limit number, For each data region, the divided data is extracted from the concatenated encoded data that has been BCH code decoded (outer encoded data that has been BCH encoded). Further, the outer code decoding unit 24 sets confirmed bit information indicating whether or not the extracted divided data is data that has been confirmed bit.

  The divided data extracted from the concatenated encoded data corresponds to the divided data generated by the outer encoding unit 11 of the transmission device 1. Also, the divided data extracted from the concatenated encoded data is data decoded as being error-correctable (data that has been confirmed bit), or data that has not been decoded as being uncorrectable (deterministic bit) Data).

  The outer code decoding unit 24 outputs to the error presence / absence determination unit 25 the plurality of pieces of divided data and the determined bit information for each of the plurality of pieces of divided data. Details of the processing of the outer code decoding unit 24 will be described later.

  The error presence / absence determination unit 25 receives a plurality of pieces of divided data and confirmed bit information from the outer code decoding unit 24 and, based on the confirmed bit information, error information indicating whether or not there is an error (error) for the divided data. Set. Then, the error presence / absence determination unit 25 outputs the plurality of pieces of divided data input from the outer code decoding unit 24 and error information about each of the plurality of pieces of divided data to the packet header editing unit 26. Details of the processing of the error presence / absence determination unit 25 will be described later.

  The packet header editing unit 26 inputs a plurality of divided data and error information from the error presence / absence determining unit 25, and extracts a TS packet from the plurality of divided data. Then, the packet header editing unit 26 sets the error indicator flag by editing the packet headers of all TS packets extracted from the corresponding divided data based on the error information, and outputs the TS packets.

  As a result, TS packet errors are set not for each piece of concatenated encoded data but for each piece of divided data.

(Processing of inner code decoding unit 23 and outer code decoding unit 24)
Next, processes of the inner code decoding unit 23 and the outer code decoding unit 24 will be described in detail. FIG. 8 is a flowchart showing processing of the inner code decoding unit 23 and the outer code decoding unit 24. 8, steps S801 and S802 are processes by the inner code decoding unit 23, and steps S803 to S806 are processes by the outer code decoding unit 24.

  First, the inner code decoding unit 23 inputs demodulated concatenated encoded data or concatenated encoded data subjected to concatenated code decoding (step S801), and performs LDPC code decoding (step S802).

  The outer code decoding unit 24 determines whether or not error correction is possible for each data area of the concatenated encoded data that has been LDPC code decoded by the inner code decoding unit 23. If error correction is possible, the outer code decoding unit 24 performs BCH code decoding. To make a definite bit (step S803). Thereby, when error correction is possible, the data area is determined.

  FIG. 9 is a flowchart showing details of the BCH code decoding and definite bit conversion processing (processing in step S803) in the outer code decoding unit 24. The outer code decoding unit 24 calculates, for each data area of the concatenated encoded data, the number of bits with errors (number of error bits) for the divided data in the data area (step S901). Then, the outer code decoding unit 24 compares the number of error bits with a preset number of error correctable bits for each data area, and determines whether or not the error bit number can be corrected (step S902). ).

  When the outer code decoding unit 24 determines in step S902 that the number of error bits is equal to or less than the number of error correctable bits and that error correction is possible (step S902: Y), the BCH in the data area is determined for the data area. Error correction is performed by performing BCH code decoding processing on the divided data in the data area using the code parity bits (step S903). The outer code decoding unit 24 converts the data area into a definite bit (step S904).

  On the other hand, when the outer code decoding unit 24 determines in step S902 that the number of error bits is larger than the number of error correctable bits and cannot be corrected (step S902: N), the outer code decoding unit 24 does not perform BCH code decoding, The data area is determined to be non-determined because the data area cannot be confirmed.

  In this way, it is determined whether or not error correction is possible based on the number of error bits calculated during the BCH code decoding process, and when the error correction is possible, the data area is determined.

  Returning to FIG. 8, after the process of step S803, the outer code decoding unit 24 determines whether or not all data areas have been determined (step S804). If the outer code decoding unit 24 determines in step S804 that any one of the data regions has not been determined (step S804: N), the outer code decoding unit 23 performs the LDPC code in step S802. Whether the number of decoding processes and the number of BCH code decoding and definite bit conversion processes (decoding process number) in step S803 by the outer code decoding unit 24 is equal to or less than a predetermined upper limit number, that is, the number of decoding processes has not reached the upper limit number Whether or not (step S805).

  If the outer code decoding unit 24 determines in step S805 that the number of decoding processes is equal to or less than the upper limit number (has not reached the upper limit number) (step S805: Y), the outer code decoding unit 24 proceeds to step S802, and all data areas are stored. The processes in steps S802 to S804 are repeated until it is confirmed or the number of decoding processes reaches the upper limit.

  On the other hand, when the outer code decoding unit 24 determines in step S804 that all data areas have been determined (step S804: Y), or in step S805, the number of decoding processes is not less than or equal to the upper limit number (upper limit number). (Step S805: N), the divided data is extracted from all data areas. Further, the outer code decoding unit 24 sets definite bit information indicating whether or not the data is definite bit for each divided data.

  The outer code decoding unit 24 outputs the plurality of pieces of divided data and the determined bit information for each of the plurality of pieces of divided data to the error presence / absence determination unit 25 (step S806).

  FIG. 10 is a diagram for explaining the processing of the inner code decoding unit 23 and the outer code decoding unit 24 shown in FIGS. 8 and 9, and an example in which the predetermined number of divided data shown in FIGS. It is. Data 1, 2, and 3 are each divided data.

  In step S802, the inner code decoding unit 23 uses the LDPC code parity bits and LDPC code check matrix included in the concatenated encoded data to perform LDPC code decoding processing on the BCH encoded data included in the concatenated encoded data. Apply.

  If the outer code decoding unit 24 determines in step S803 that error correction is possible for data 1 included in the concatenated encoded data, the outer code decoding unit 24 uses the BCH code parity bit corresponding to data 1 to A code decoding process is performed to make the data area 1 (data 1 and BCH code parity bit) a definite bit.

  When the outer code decoding unit 24 determines that the error correction is possible for the data 2 included in the concatenated encoded data, the outer code decoding unit 24 performs a BCH code decoding process on the data 2 using the BCH code parity bit corresponding to the data 2, Data area 2 (data 2 and BCH code parity bit) is converted into a definite bit.

  If the outer code decoding unit 24 determines that the error correction is not possible for the data 3 included in the concatenated encoded data, the outer code decoding unit 24 does not perform the BCH code decoding and converts the data area 3 (data 3 and the BCH code parity bit) into a definite bit. Since it is not possible, the data area 3 is determined as uncertain.

  As a result, the data areas 1 and 2 are fixed, and the data area 3 is not fixed. Error bits remain in the data area 3.

  In step S802, the inner code decoding unit 23 uses the LDPC code parity bits and the LDPC code check matrix included in the concatenated encoded data, and uses the data region 1 included in the concatenated encoded data after the processing in step S803. The LDPC code decoding process is performed again on a few BCH encoded data.

  In this case, the data areas 1 and 2 are determined bits, and the data area 3 is not determined bits and error bits remain. However, by using the accurate likelihood of the data areas 1 and 2, the data areas 1 and 2 are used. 3 is also expected to be a definite bit. That is, by the LDPC code decoding process, it is possible to propagate the likelihood of the correct bits in the data areas 1 and 2 converted into definite bits to another data area 3 that is not converted into definite bits.

  Then, when the LDPC code decoding process in step S802 and the BCH code decoding process in step S803 are repeated, the outer code decoding unit 24 determines that all the data areas 1, 2, and 3 have been converted into definite bits. In S806, the data 1, 2, 3 as the divided data is extracted for each of the data areas 1, 2, 3. Then, the outer code decoding unit 24 outputs the data 1, 2 and 3, and generates and outputs definite bit information n1, n2 and n3 indicating that the data 1, 2 and 3 are the data obtained as definite bits. To do.

  In step S805, after the LDPC code decoding process in step S802 and the BCH code decoding process in step S803 are repeated a predetermined upper limit number of times, the outer code decoding unit 24 performs data region 1, 2, and 3 in step S806. The data 1, 2, and 3, which are divided data, are extracted. The outer code decoding unit 24 outputs data 1, 2, 3 when the data areas 1, 2 are converted into definite bits but the data area 3 is not determined bits. Further, the outer code decoding unit 24 generates and outputs definite bit information n1, n2, and n3 indicating that the data 1 and 2 are data that is definite bit and the data 3 is data that is not definite bit. .

(Processing of error presence / absence determination unit 25 and packet header editing unit 26)
Next, processing of the error presence / absence determination unit 25 and the packet header editing unit 26 will be described in detail. FIG. 11 is a flowchart showing processing of the error presence / absence determination unit 25 and the packet header editing unit 26. In FIG. 11, steps S1101 and S1102 are processing by the error presence / absence determination unit 25, and steps S1103 to S1107 are processing by the packet header editing unit 26.

  First, the error presence / absence determination unit 25 inputs a plurality of pieces of divided data and confirmed bit information (step S1101), and sets error information based on the confirmed bit information (step S1102).

  Specifically, the error presence / absence determination unit 25 sets error information indicating that there is no error for the divided data when the confirmed bit information indicates data that has been confirmed bit. In addition, when the determined bit information indicates that the data is not the determined bit, the error presence / absence determination unit 25 sets error information indicating that there is an error for the divided data.

  The packet header editing unit 26 extracts TS packets from the plurality of divided data (step S1103), and determines whether the error information indicates that there is an error or no error (step S1104).

  If the packet header editing unit 26 determines in step S1104 that the error information indicates that there is an error (step S1104: there is an error), for all TS packets extracted from the divided data corresponding to the error information, The error indicator flag in the packet header is set to ON (step S1105). On the other hand, when the packet header editing unit 26 determines in step S1104 that the error information indicates no error (step S1104: no error), the packet header editing unit 26 adds all TS packets extracted from the divided data corresponding to the error information. On the other hand, an error indicator flag in the packet header is set to OFF (step S1106).

  The packet header editing unit 26 outputs the TS packet after performing the processing of step S1104 to step S1106 for each divided data (step S1107).

  FIG. 12 is a diagram for explaining the processing of the error presence / absence determination unit 25 and the packet header editing unit 26 shown in FIG. 11. As in FIG. 10, the predetermined number of the divided data shown in FIGS. It is an example. Data 1, 2, and 3 are each divided data.

  In step S1102, the error presence / absence determination unit 25 sets error information for each of the data 1, 2, and 3 based on the confirmed bit information. For example, when the confirmed bit information n1 and n2 of the data 1 and 2 indicate that it is a confirmed bit, error-free information is set in the error information e1 and e2 of the data 1 and 2. Further, when the confirmed bit information n3 of the data 3 indicates that it is not a confirmed bit, the error information e3 of the data 3 is set to information with an error.

  In step S1103, the packet header editing unit 26 extracts TS packets from the data 1, 2, and 3. In step S1104, the packet header editing unit 26 determines whether the error information e1, e2, e3 of the data 1, 2, 3 indicates that there is an error or no error.

  In step S1104, the packet header editing unit 26 determines that the error information e1 and e2 of the data 1 and 2 indicates no error. In step S1106, for all TS packets extracted from the data 1 and 2, Set the error indicator flag in the packet header to off. Further, the packet header editing unit 26 determines in step S1104 that the error information e3 of the data 3 indicates that there is an error, and in step S1105, for all TS packets extracted from the data 3, the packet header error Set the indicator flag on.

  FIG. 13 is a diagram for explaining processing of the error presence / absence determination unit 25 and the packet header editing unit 26 illustrated in FIG. 11, and is an example in the case where a TS packet straddles two pieces of divided data. This corresponds to the specific example (1) shown in FIG.

  In the specific example (1) shown in FIG. 5, the tenth TS packet straddles the two data 1 and 2 at the boundary between the data 1 and 2 that are the divided data. The 0th to 9th TS packets and a part of the 10th TS packet are stored in the data 1 area, the remaining part of the 10th TS packet, the 11th to 19th TS packets and the null data are data 2 It is stored in the area. Information with no error is set in the error information e1 of data 1, and information with an error is set in the error information e2 of data 2.

  The packet header editing unit 26 extracts the 0th to 9th TS packets and a part of the 10th TS packet from the data 1, and the remaining part of the 10th TS packet from the data 2 and the 11th to 19th TS packets are extracted. Then, the packet header editing unit 26 combines a part of the 10th TS packet and the remaining part of the 10th TS packet to generate a 10th TS packet.

  The packet header editing unit 26 determines that the error information e1 of the data 1 indicates no error, and among the 0th to 9th TS packets extracted from the data 1 and a part of the 10th TS packet, 0 is output. The error indicator flag in the packet header is set to off for the -9th TS packet.

  Further, the packet header editing unit 26 determines that the error information of the data 2 indicates that there is an error, and among the remaining part of the 10th TS packet extracted from the data 2 and the 11th to 19th TS packets In addition to the 11th to 19th TS packets, the error indicator flag in the packet header is set to ON for the 10th TS packet from which the remaining portion of the TS packet is extracted. For the 10th TS packet, the error indicator flag in the packet header is set to ON because there is no error in a part of the 10th TS packet extracted from data 1, but 10 extracted from data 2 This is because an error may exist in the remaining part of the second TS packet.

  As described above, according to the receiving device 2 of the embodiment of the present invention, the inner code decoding unit 23 performs the LDPC code decoding process on the BCH encoded data included in the concatenated encoded data demodulated by the demodulation unit 22. The outer code decoding unit 24 determines whether or not error correction is possible for each data area of the concatenated encoded data that has been LDPC code decoded by the inner code decoding unit 23, and is capable of error correction. When the determination is made, the BCH code decoding process is performed on the divided data in the data area, and the data area is converted into a fixed bit and fixed.

  Further, the inner code decoding unit 23 inputs the concatenated encoded data (concatenated encoded data subjected to the concatenated code decoding) that has been BCH code decoded by the outer code decoding unit 24, and the BCH encoded data included in the concatenated encoded data. Then, the LDPC code decoding process is performed again.

  By this LDPC code decoding process, the exact bit likelihood in the data area that has been definite bit propagates to other data areas that have not been determinized bit, so in the BCH code decoding process of the outer code decoding unit 24 in the subsequent stage, Other data areas that are not defined bits are easily determined to be error-correctable.

  Then, after the LDPC code decoding process of the inner code decoding unit 23 and the BCH code decoding process of the outer code decoding unit 24 are repeated, the outer code decoding unit 24 can perform error correction on all data areas. If it is determined, or if it is determined that the number of decoding processes has reached the upper limit, divided data is extracted for each data area. Further, the outer code decoding unit 24 sets confirmed bit information indicating whether or not the extracted divided data is data that has been confirmed bit.

  The error presence / absence determination unit 25 sets error information indicating whether or not there is an error (error) in the divided data based on the confirmed bit information. Then, the packet header editing unit 26 extracts TS packets from the divided data, sets error indicator flags for the packet headers of all TS packets extracted from the corresponding divided data based on the error information, and sets the TS Output the packet.

  As described above, conventionally, an error of a TS packet is set for each concatenated encoded data. However, in the embodiment of the present invention, an error of a TS packet can be set for each divided data. It is possible to improve the measurement accuracy.

  In addition, after making a definite bit for each data area of the BCH encoded data, LDPC code decoding and BCH code decoding are repeatedly performed, so that the bit of the definite bit data area is propagated with likelihood and is not made into a definite bit. The error correction of the data area was performed and all the data areas were fixed. As a result, since the concatenated code decoding process is repeated until all the divided data are determined or until the upper limit number is reached, the original data can be restored with high accuracy.

  Therefore, when data such as video and audio is concatenated using a BCH code and an LDPC code, and the LDPC code decoding and the BCH code decoding in which the likelihood propagates are repeatedly performed on the concatenated encoded data, the data is not Since the error correction capability is improved as compared with the conventional case that can be confirmed, the decoding performance of the concatenated encoded data can be further improved, and the required C / N can be reduced.

[When inner code is spatially coupled LDPC code]
Next, a case where the inner code is a spatially coupled LDPC code will be described. The inner encoding unit 12 of the transmission apparatus 1 performs spatially coupled LDPC coding using a parity check matrix of the spatially coupled LDPC code instead of the LDPC code. In addition, the inner code decoding unit 23 of the reception device 2 performs spatially coupled LDPC code decoding using a parity check matrix of the spatially coupled LDPC code instead of the LDPC code.

  FIG. 14 (1) is a diagram illustrating a parity check matrix of an LDPC code, and FIG. 14 (2) is a diagram illustrating a parity check matrix of a spatially coupled LDPC code. In the parity check matrix of FIGS. 14 (1) and 14 (2), a parity bit indicating the position where the likelihood propagates is arranged at a black pattern portion. In the decoding process using the parity check matrix in FIGS. 14 (1) and 14 (2), the decoding target data (BCH encoded data) included in the concatenated encoded data corresponds to the row portion (horizontal width portion) of the parity check matrix, The likelihood of each bit of the decoding target data is propagated to the likelihood of the parity bit position in the parity check matrix corresponding to the bit position by the decoding process.

  In the parity check matrix of the LDPC code shown in FIG. 14 (1), parity bits are randomly arranged in the entire parity check matrix, whereas in the parity check matrix of the spatially coupled LDPC code shown in FIG. It is arranged only on the diagonal of the check matrix.

  In the LDPC code decoding process using the parity check matrix of the LDPC code shown in FIG. 14 (1), in the example of FIG. 10, the likelihood of the predetermined bits in the data area 1 is determined according to the parity bits arranged at random. Propagate to a predetermined bit position in 2 and 3. On the other hand, in the spatially coupled LDPC code decoding process using the parity check matrix of the spatially coupled LDPC code shown in FIG. 14 (2), the likelihood of the predetermined bits in the data area 1 is within the range of the parity bits arranged on the diagonal line. Then, for example, it propagates to a predetermined bit position in the neighboring data area 2.

  FIG. 15 is a diagram for explaining the likelihood propagation when the spatially coupled LDPC code is used, and shows a case where the parity check matrix of the spatially coupled LDPC code shown in FIG. 14 (2) is used. In the spatially coupled LDPC code decoding process, for example, when the leftmost data area is a definite bit, the exact bit likelihood is within a range of parity bits arranged on a diagonal line within a predetermined bit position of a neighboring data area. And sequentially propagate from the upper left to the lower right on the diagonal.

  In this way, when the inner code is a spatially coupled LDPC code, the data in the data region that has been made into a definite bit by the spatially coupled LDPC code decoding process using the parity check matrix of the spatially coupled LDPC code shown in FIG. Therefore, the correct bit likelihood is reliably propagated only to a predetermined bit position in the neighboring data area, so that the error data in the code is corrected from the end of the code. On the other hand, when the inner code is an LDPC code, in the LDPC code decoding process using the LDPC code check matrix shown in FIG. Since it propagates only to the data area corresponding to the randomly arranged parity bits, when all the data areas are determined, the error data in the code is corrected without being biased to the position in the code. As a result, when the spatially coupled LDPC code is used, the data area is surely converted into a definite bit in order from the neighborhood, so that iterative decoding using the decoding result of the BCH code is performed as compared with the case of using the LDPC code. Can be realized more efficiently.

  The present invention has been described with reference to the embodiment. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the technical idea thereof. For example, in the above-described embodiment, the inner code decoding unit 23 and the outer code decoding unit 24 of the reception device 2 illustrated in FIG. 7 are configured to repeatedly perform the decoding process. On the other hand, the inner code decoding unit 23 and the outer code decoding unit 24 may perform the decoding process only once.

  In the above embodiment, the BCH code is used as the outer code, and the LDPC code that realizes the BP method in which the likelihood is propagated is used as the inner code. However, this is an example, and other codes are used. Can do. For example, a Reed-Solomon code may be used as the outer code, or an LDPC code may be used as the outer code and the inner code. When an LDPC code is used as the outer code, the outer code decoding unit 24 of the receiving device 2 determines whether or not there are error bits for each data area. If no error bits remain, the data area is determined. Bitize.

  In short, the outer code only needs to be a code that can determine whether or not the data area is determined for each data area at the time of decoding, and the inner code has a likelihood propagation at the time of decoding. Any code may be used.

  2 to 4, 10, and 12 of the embodiment show an example in which the outer encoding unit 11 of the transmission device 1 divides data to be transmitted into three, and FIGS. 5, 6, and 6. 13 shows an example in which the transmission target data is divided into two. The present invention is not limited to this number, and can be applied to the case where the number is divided into four or more.

  Moreover, although the example which arrange | positions a BCH code parity bit equally in the outer coding part 11 of the transmitter 1 in the said embodiment was shown, you may make it arrange | position unevenly. Specifically, in FIG. 2, the region size of the BCH code parity bit is variable, the region size of the BCH code parity bit corresponding to the left divided data is increased, and the BCH code parity corresponding to the right divided data is set. The bit area size may be reduced. Also, the area size of the BCH code parity bit is fixed, a larger parity is arranged in the BCH code parity bit area corresponding to the left divided data, and the parity is assigned to the BCH code parity bit area corresponding to the right divided data. You may make it arrange | position little.

  In the above embodiment, the transmission apparatus 1 encodes and transmits the TS packet, and the reception apparatus 2 decodes the TS packet. However, the present invention describes the encoding and decoding and the transmission / reception target as the TS. The present invention is not limited to a packet, but can be applied to other packets such as a TLV (Type Length Value) packet. In short, it applies to packets that can define an error indicator in the packet header.

  In the embodiment, the processing of each component from the outer encoding unit 11 to the modulation unit 13 of the transmission device 1 illustrated in FIG. 1 is realized by an LSI chip that is an integrated circuit mounted on the transmission device 1. You may be made to do. These may be individually made into one chip, or a part or all of them may be made into one chip.

  Further, instead of the LSI, it may be realized by a chip such as a VLSI or ULSI having a different degree of integration. Furthermore, the present invention is not limited to a chip such as an LSI, and a dedicated circuit or a general-purpose processor may be used, or an FPGA (Field Programmable Gate Array) may be used. The same applies to the processing of each component from the demodulation unit 22 to the packet header editing unit 26 of the reception device 2 illustrated in FIG. 7, and is realized by a chip mounted on the reception device 2.

DESCRIPTION OF SYMBOLS 1 Transmitter 2 Receiver 10 Encoder 11 Outer encoder 12 Inner encoder 13 Modulator 14 Transmitter 20 Decoder 21 Receiver 22 Demodulator 23 Inner code decoder 24 Outer code decoder 25 Error presence / absence determiner 26 Packet header editing part (error setting part)

Claims (5)

A predetermined number of pieces of divided data including a plurality of packets are subjected to outer code encoding processing, further receiving inner encoded data, and receiving inner encoded data. In the receiving device that performs processing and decoding of the outer code,
Using an inner code parity bit included in the concatenated encoded data, an inner code decoding unit that performs an inner code decoding process on outer encoded data included in the concatenated encoded data;
The number of error bits is calculated for each data area of the predetermined number of divided data and outer code parity bits included in the outer encoded data subjected to the decoding process by the inner code decoding unit, and the number of error bits is equal to the predetermined number of bits. For the data area of a few or less, the outer code parity bit of the data area is used to perform the outer code decoding process on the divided data of the data area, and the data area subjected to the outer code decoding process is determined. An outer code decoding unit for extracting the predetermined number of divided data;
For each divided data extracted by the outer code decoding unit, when the data area including the divided data is fixed, it is determined that there is no error in the divided data, and the data area including the divided data is If not determined, an error presence / absence determination unit that determines that an error exists in the divided data; and
The packet is extracted from the predetermined number of pieces of divided data, and the divided data determined to have no error by the error presence / absence determining unit indicates that the error does not exist in all the packets extracted from the divided data. An error setting unit for setting a flag and setting a flag indicating that the error exists in all packets extracted from the divided data for the divided data determined to have an error by the error presence determination unit;
A receiving apparatus comprising: The receiving device according to claim 1,
The inner code decoding unit inputs concatenated encoded data including the divided data subjected to decoding processing by the outer code decoding unit, performs decoding processing of the inner code,
The outer code decoding unit inputs concatenated encoded data including outer encoded data subjected to decoding processing by the inner code decoding unit, performs decoding processing of the outer code,
Repeating the decoding process of the inner code by the inner code decoding unit and the decoding process of the outer code by the outer code decoding unit,
The outer code decoding unit determines that all the data areas are fixed, or determines that the number of decoding processes by the inner code decoding unit and the outer code decoding unit has reached a predetermined upper limit number If so, the receiving apparatus extracts the predetermined number of pieces of divided data. The receiving apparatus according to claim 1 or 2,
The receiving apparatus, wherein the outer code is a BCH code and the inner code is an LDPC code. The receiving apparatus according to claim 1 or 2,
The outer code is a BCH code, the inner code is a spatially coupled LDPC code,
The bit size of the divided data and each row size in a plurality of diagonal block matrices in which parity bits included in the parity check matrix of the spatially coupled LDPC code are arranged have the same or an integer multiple relationship. A receiving device. An outer code encoding process is performed on a predetermined number of pieces of divided data, and further, concatenated encoded data that has been subjected to an inner code encoding process is received, and an inner code decoding process and an outer code decoding process are performed on the concatenated encoded data. In a chip mounted on a receiving device that performs decoding processing,
Using an inner code parity bit included in the concatenated encoded data, an inner code decoding unit that performs an inner code decoding process on outer encoded data included in the concatenated encoded data;
The number of error bits is calculated for each data area of the predetermined number of divided data and outer code parity bits included in the outer encoded data subjected to the decoding process by the inner code decoding unit, and the number of error bits is equal to the predetermined number of bits. For the data area of a few or less, the outer code parity bit of the data area is used to perform the outer code decoding process on the divided data of the data area, and the data area subjected to the outer code decoding process is determined. An outer code decoding unit for extracting the predetermined number of divided data;
For each divided data extracted by the outer code decoding unit, when the data area including the divided data is fixed, it is determined that there is no error in the divided data, and the data area including the divided data is If not determined, an error presence / absence determination unit that determines that an error exists in the divided data; and
A flag indicating that the error does not exist in all the packets extracted from the divided data with respect to the divided data determined by the error presence / absence determination unit that the packet is extracted from the predetermined number of pieces of the divided data. An error setting unit that sets a flag indicating that the error exists in all packets extracted from the divided data for the divided data determined to have an error by the error presence determination unit;
A chip comprising:

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