JP2009225153A - Glitch elimination circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a glitch elimination circuit capable of eliminating glitches to be a cause of a malfunction and performing communication without deteriorating transfer throughput. <P>SOLUTION: The glitch elimination circuit which eliminates the glitches of signals for performing communication using a bus includes: a first flip-flop 5 in which the signals are input and which outputs the signals by being synchronized with a clock signal; a second flip-flop 6 in which output of the first flip-flop is input, and which outputs the output of the first flip-flop by being synchronized with the clock signal; a coincidence detection circuit 7 which detects that each output of the first and second flip-flops is at a high level or a low level to validate an enable signal; and a third flip-flop which outputs the output of the second flip-flop by being synchronized with the clock signal when the enable signal is valid, and holds the output when the enable signal is invalid. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a glitch removal circuit that removes glitches from signals that are communicated using a bus, and more particularly to a glitch removal circuit that can communicate without deteriorating transfer throughput.

  FIG. 6 is a block diagram showing a conventional inter-card communication using a parallel bus. Here, the card means a card type module having a specific function. Such a configuration is used, for example, in a semiconductor test apparatus.

  Cards used in semiconductor test equipment include pattern generation cards that generate signals called patterns, pin electronics cards that generate signals to be applied to the device under test, power supply to the device under test, and voltage / current, etc. There are a DC card to be measured, an I / F card that distributes / relays data to these cards, a CPU card that has an operation control unit (CPU: Central Processing Unit) and controls the test centrally.

  In FIG. 6, the master card 1 has a bus control right and controls the slave cards 2 to 4. The parallel bus shown in FIG. 6 includes an address / data, a control signal A, a control signal B, and a clock signal. The address / data has a width of 32 bits, and the control signal A is an address strobe signal, a data strobe signal, a write / read signal, etc. output from the master card 1 to each slave card.

  The control signal B is a data acknowledge signal or the like output from each slave card to the master card 1. The clock signal is output from the master card 1 to each slave card, and the signal on the bus operates in synchronization with this clock signal.

  Prior art documents related to the conventional deglitch circuit include the following.

JP 2002-208844 A

  As shown in FIG. 6, when communication is performed using a parallel bus in which address / data, control signals, and clock signals are configured on separate lines, glitches occur due to crosstalk between signals. There was a problem that it might cause malfunction.

In recent years, the transfer speed of buses used for such inter-card communication has been increasing. For this reason, there is a strong demand for not deteriorating transfer throughput when removing glitches.
Accordingly, the problem to be solved by the present invention is to realize a glitch removal circuit capable of removing a glitch causing a malfunction and communicating without deteriorating the transfer throughput.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a glitch removal circuit that removes glitches from signals that communicate using a bus,
A first flip-flop that receives the signal and outputs it in synchronization with the clock signal; a second flip-flop that receives the output of the first flip-flop and outputs the signal in synchronization with the clock signal; And a coincidence detection circuit that validates the enable signal by detecting that the output of each of the flip-flops and the second flip-flop is at a high level or a low level, and when the enable signal is valid, And a third flip-flop for outputting the output of the flip-flop in synchronization with the clock signal and holding the output when the enable signal is invalid.

The invention according to claim 2
The deglitch circuit of claim 1, wherein
The second flip-flop
There are n (n is an integer of 2 or more), the output of the first flip-flop is connected to the input of the first flip-flop, and the output of the n-th flip-flop is connected to the input of the third flip-flop The output of the (n−1) th flip-flop is connected to the input of the nth flip-flop.

The invention described in claim 3
In the deglitch circuit according to claim 1 or 2,
It is used for a semiconductor test apparatus.

  According to the present invention, in a glitch removal circuit that removes glitches from a signal that communicates using a bus, the first flip-flop that receives the signal and outputs the signal in synchronization with the clock signal, and the first flip-flop A second flip-flop that receives the output of the clock and outputs in synchronization with the clock signal, and detects that the output of each of the first flip-flop and the second flip-flop is at a high level or a low level A coincidence detection circuit for validating the enable signal, and outputting the output of the second flip-flop in synchronization with the clock signal when the enable signal is valid, and outputting the output when the enable signal is invalid. A third flip-flop for holding the glitch that causes a malfunction and removing the transfer It is possible to communicate without degrading the put.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of a deglitch circuit according to the present invention.

  In FIG. 1, the flip-flop 5 and the flip-flop 6 output the level of the input signal at the timing of the rising edge of the clock signal. The coincidence detection circuit 7 outputs an enable signal when the levels of the plurality of input signals all become high levels or all low levels. The flip-flop 8 has an enable terminal. When the signal input to the enable terminal is valid, the level of the input signal is output at the timing of the rising edge of the clock signal. When the signal input to the enable terminal is invalid, the output is held as it is even if the clock signal is input.

  The input signal is connected to the data input terminal of the flip-flop 5, and the data output terminal of the flip-flop 5 is connected to the data input terminal of the flip-flop 6 and one input terminal of the coincidence detection circuit 7. The data output terminal of the flip-flop 6 is connected to the data input terminal of the flip-flop 8 and the other input terminal of the coincidence detection circuit 7, and the data output of the flip-flop 8 is output as an output signal.

  The clock signal is connected to the clock terminal of the flip-flop 5, the clock terminal of the flip-flop 6, and the clock terminal of the flip-flop 8, and the enable signal output terminal of the coincidence detection circuit 7 is connected to the enable terminal of the flip-flop 8. The flip-flop 5, the flip-flop 6, the coincidence detection circuit 7, and the flip-flop 8 constitute a glitch detection circuit 50.

  The operation of the embodiment shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a timing chart showing the operation when a glitch is detected.

  As shown in FIG. 2, when a glitch occurs in the input signal IN and it is accidentally picked up at the rising edge of the clock signal, it is sequentially output to the output Q1 of the flip-flop 5 and the output Q2 of the flip-flop 6.

  The coincidence detection circuit 7 sets the enable signal to a high level when the output Q1 of the flip-flop 5 and the output Q2 of the flip-flop 6 are high or low, respectively, and the output Q1 of the flip-flop 5 and the output Q2 of the flip-flop 6 are different. When the level is set, the enable signal is set to a low level.

  The flip-flop 8 outputs the level of the input signal, that is, the level output by the flip-flop 6 at the timing of the rising edge of the clock signal when the enable signal is at a high level (valid). On the other hand, the output of the flip-flop 8 is held as it is even if a clock signal is input when the enable signal is at a low level (invalid).

  Since the enable signal is at the low level at the timing T2 and the timing T3 in FIG. 2, the output of the flip-flop 8 holds the previous state, that is, the high level state, so that no glitch appears in the output signal OUT. Has been removed.

  Further, when the clock signal is sufficiently higher than the operating frequency of the input signal, communication can be performed without deteriorating the transfer throughput of the input signal. For example, when the input signal has a parallel bus structure, if the operating frequency of the parallel bus is 15.625 MHz and the frequency of the clock signal of the glitch removal circuit 50 of the present invention is 125 MHz, the latency in the glitch removal circuit 50 is Is equivalent to 3 clocks, that is, 24 ns, and the clock of the parallel bus is shorter than one period of 64 ns, so that communication can be performed without greatly affecting the transfer throughput.

  As a result, the coincidence detection circuit 7 monitors the outputs of the flip-flop 5 and the flip-flop 6, respectively, and enables the enable signal when the outputs are at the high level and the low level, and outputs the enable signal when the outputs are at different levels. To disable. The flip-flop 8 outputs the level of the input signal at the timing of the rising edge of the clock signal when the enable signal is valid, and holds the output when the enable signal is low (invalid). It is possible to perform communication without removing the glitch that becomes and without deteriorating the transfer throughput.

  In the embodiment shown in FIG. 1, the outputs of the two flip-flops are monitored by the coincidence detection circuit 7. However, the present invention is not necessarily limited to this, and the outputs of three or more flip-flops are coincident detected. You may make it monitor with the circuit 7. FIG.

  A block diagram of the configuration in this case is shown in FIG. The difference from the embodiment shown in FIG. 1 is that there are a plurality of flip-flops 6 (n: n is an integer of 2 or more), and the coincidence detection circuit 7 monitors the outputs of the plurality of flip-flops 61 to 6n. Is. The flip-flop 5, the flip-flops 61 to 6 n, the coincidence detection circuit 7 and the flip-flop 8 constitute a glitch detection circuit 51.

  By using a plurality of flip-flops 6, it is possible to remove a wide glitch. This will be described with reference to FIGS. 4 and 5 are timing charts showing operations when a glitch is detected.

  FIG. 4 shows the operation when the glitch width is two clocks in the embodiment of FIG. In this case, the glitch removal circuit 50 outputs a glitch waveform without completely removing the glitch. On the other hand, FIG. 5 shows a case where there are two flip-flops 6, and Q2 in FIG. 5 shows the output of the flip-flop 62 shown in FIG.

  As shown in FIG. 5, by using two flip-flops 6 and monitoring the output of each flip-flop by the coincidence detection circuit 7, it becomes possible to remove a glitch having a 2-clock width. Thus, as the number of flip-flops monitored by the coincidence detection circuit 7 increases, it becomes possible to remove a glitch having a longer width.

  In the embodiment shown in FIG. 1, the enable signal output from the coincidence detection circuit 7 validates the high level and invalidates the low level. However, it is not necessarily limited to this, and the high level is invalidated. The low level may be valid.

It is a block diagram showing the configuration of an embodiment of a deglitch circuit according to the present invention. It is a timing chart which shows operation when a glitch is detected. It is a block diagram showing the configuration of another embodiment of the deglitch circuit according to the present invention. It is a timing chart which shows operation when a glitch is detected. It is a timing chart which shows operation when a glitch is detected. It is a block diagram which shows the communication between cards in the conventional parallel bus.

Explanation of symbols

1 Master card 2, 3, 4 Slave card 5, 6, 8, 61, 62, 6n Flip-flop 7 Match detection circuit 50, 51 Glitch removal circuit

Claims (3)

In a glitch removal circuit that removes glitches from signals that communicate using a bus,
A first flip-flop that receives the signal and outputs the signal in synchronization with a clock signal;
A second flip-flop that receives the output of the first flip-flop and outputs it in synchronization with the clock signal;
A coincidence detection circuit for validating an enable signal by detecting that the output of each of the first flip-flop and the second flip-flop is at a high level or a low level;
A third flip-flop that outputs the output of the second flip-flop in synchronization with the clock signal when the enable signal is valid, and holds the output when the enable signal is invalid. A characteristic deglitch circuit. The second flip-flop
There are n (n is an integer of 2 or more), the output of the first flip-flop is connected to the input of the first flip-flop, and the output of the n-th flip-flop is connected to the input of the third flip-flop 2. The deglitch circuit according to claim 1, wherein an output of the (n-1) th flip-flop is connected to an input of the nth flip-flop. 3. The deglitch circuit according to claim 1, wherein the deglitch circuit is used in a semiconductor test apparatus.

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