CN106896754B - Device for generating trigger signal in PXIe bus - Google Patents
Device for generating trigger signal in PXIe bus Download PDFInfo
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- CN106896754B CN106896754B CN201510958033.1A CN201510958033A CN106896754B CN 106896754 B CN106896754 B CN 106896754B CN 201510958033 A CN201510958033 A CN 201510958033A CN 106896754 B CN106896754 B CN 106896754B
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- trigger
- triggering
- cpld chip
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- software
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/25—Pc structure of the system
- G05B2219/25314—Modular structure, modules
Abstract
The invention provides a device for generating a trigger signal in a PXIe bus, which comprises an upper computer, a CPLD chip and an input/output connector, wherein the upper computer passes through I2The C bus is connected with the CPLD chip, the CPLD chip is connected with the input/output connector, and the CPLD chip realizesAnd software triggering, wherein the upper computer routes the software triggering realized by the CPLD chip to a triggering target through the input/output connector without adding a peripheral module to generate a triggering signal, so that the occupied space of a PXIe controller circuit board and the number of chip pins are reduced, and the interconnection cost is reduced.
Description
Technical Field
The invention relates to the technical field of PXIe systems, in particular to a device for generating a trigger signal in a PXIe bus.
Background
The trigger signal in the PXIe system is mainly used for synchronous triggering and clock transmission among multiple modules, and defines some standard trigger protocols to facilitate interoperability, such as TTL bus triggering, star triggering, differential triggering and many other common trigger modes, it should be noted that the trigger routing is a very important function of the PXIe embedded control system, and the trigger source signal is routed to the trigger terminal to realize the transmission among events, which is particularly important for the synchronization among multiple modules. At present, the common trigger modes require a separate PXI/PXIe peripheral module to generate a trigger signal, which increases the design cost of the PXIe system and occupies an extra space of the PXIe system, and among the common trigger modes, the trigger route is mostly realized in a mode that an upper computer controls one FPGA chip through a PCI bus, and the mode occupies a lot of space of the PXIe system and has high interconnection cost. Therefore, there is a need for a device for generating a trigger signal in a PXIe bus to solve the above-mentioned technical problems in the prior art.
Disclosure of Invention
The invention provides a device for generating a trigger signal in a PXIe bus, which does not need to increase peripheral modules to generate the trigger signal, reduces the occupied space of a PXIe controller circuit board and the number of chip pins, and reduces the interconnection cost.
The technical scheme adopted by the invention is as follows:
a device for generating a trigger signal in a PXIe bus comprises an upper computer, a CPLD chip and an input/output connector, wherein the upper computer is connected to the CPLD chip through an I2C bus, and the CPLD chip is connected with the input/output connector, wherein the CPLD chip generates a software trigger signal, and the upper computer routes the software trigger signal generated and realized by the CPLD chip to a trigger target through the input/output connector.
Preferably, the input/output connector includes an SMB connector and an IEC connector, the SMB connector realizes input and output of external trigger, the IEC connector realizes input and output of TTL trigger, and the upper computer controls the CPLD chip to realize that the external trigger is triggered to the TTL trigger, the TTL trigger is triggered to the external trigger, the software trigger is triggered to the external trigger, and the software trigger is triggered to the TTL trigger.
Preferably, the CPLD chip passes through the I2And the C bus acquires configuration information corresponding to the software trigger signal on the upper computer so as to adjust the pulse width and the polarity of the software trigger signal according to the configuration information.
Preferably, the CPLD chip passes through the I2And C, acquiring trigger configuration information corresponding to the external trigger and the TTL trigger respectively on the upper computer by the bus C so as to configure trigger routing information of the external trigger and the TTL trigger according to the trigger configuration information.
Preferably, the generating device further includes a crystal oscillator source, and the crystal oscillator source is connected to the CPLD chip, so that the clock reference of the CPLD chip is synchronized with the crystal oscillator source.
By adopting the technical scheme, the invention at least has the following effects:
the invention provides a device for generating a trigger signal in a PXIe bus, which is characterized in that an upper computer in an embedded controller of a PXIe system passes through I2The C bus controls one CPLD chip to realize the control, so that the occupied space of a PXIe controller circuit board and the number of chip pins are reduced, the interconnection cost is reduced, and the triggering is realized without adding a peripheral module.
Drawings
Fig. 1 is a schematic block diagram illustrating trigger generation of a PXIe bus controller in a PXIe bus trigger signal generating apparatus according to a first embodiment of the present invention;
fig. 2 is a schematic block diagram of a PXIe bus controller trigger route in a device for generating a trigger signal in a PXIe bus according to a second embodiment of the present invention;
fig. 3 is a schematic block diagram of a backplane segment trigger route of the PXIe bus in the apparatus for generating a trigger signal in the PXIe bus according to the third embodiment of the present invention.
Detailed Description
To further explain the technical means and effects of the present invention adopted to achieve the intended purpose, the present invention will be described in detail with reference to the accompanying drawings and preferred embodiments.
The apparatus for generating a trigger signal in a PXIe bus according to the present invention can simply implement trigger routing, and the apparatus for generating a trigger signal in a PXIe bus and the steps thereof according to the present invention will be described in detail below.
First embodiment
As shown in fig. 1, the apparatus for generating a trigger signal in a PXIe bus of this embodiment includes an upper computer 1 as a computer control module, a CPLD chip 2 and an input/output connector 4, where the upper computer 1 passes through I2The C bus is connected to the CPLD chip 2, the CPLD chip 2 is connected with the input/output connector 4, the CPLD chip 2 realizes software triggering, and the upper computer 1 routes the software triggering realized by the CPLD chip 2 to a triggering target through the input/output connector 4.
Preferably, the CPLD chip 2 passes through I2And the C bus acquires configuration information corresponding to software trigger on the upper computer 1 so as to adjust the pulse width and polarity of the software trigger signal according to the configuration information.
Further, as shown in fig. 1, the trigger signal generating device of this embodiment further includes a crystal oscillator source, and the crystal oscillator source is connected to the CPLD chip 2, so that the clock reference of the CPLD chip is synchronized with the crystal oscillator source.
As shown in fig. 1, the trigger signal generating apparatus in the PXIe bus provided in this embodiment is based on I provided by COM-E module2The C bus controls the realization of a CPLD chip 2. The software trigger signal can be generated by writing the software program of the CPLD chip 2, and then the CPLD chip 2 passes through the I2C bus reads the configuration information corresponding to the software trigger on the upper computer 1So as to adjust the pulse width and polarity of the software trigger signal through the configuration information.
Second embodiment
As shown in fig. 2, in the present embodiment, based on the first embodiment, in the apparatus for generating a trigger signal in a PXIe bus of the present embodiment, the input/output connector 4 includes an SMB connector 41 (disposed on a front panel of a PXIe controller) and an IEC connector 40 (disposed in the PXIe controller), the SMB connector 41 implements input and output of external trigger, the IEC connector 40 implements input and output of TTL trigger, and the host 1 controls register configuration of the CPLD chip 2 to implement the following trigger routing manner: external trigger to TTL trigger, TTL trigger to external trigger, software trigger to external trigger, and software trigger to TTL trigger. The backplane on the PXIe bus has 8 TTL trigger signal lines, and 1 TTL trigger signal line is externally triggered, so that an external trigger connector (SMB connector 41) which is triggered to the PXIe bus through a certain selected backplane trigger bus (through the TTL trigger of the IEC connector 40) is triggered, namely, the TTL trigger signal generated by the TTL trigger source is routed to a trigger target connected with the SMB connector 41 through the IEC connector 40, the CPLD chip 2 and the SMB connector 41; triggering to a certain selected backplane trigger bus (triggered by TTL of IEC connector) through an external trigger connector (SMB connector 41) of the PXIe bus, namely, routing an external trigger signal generated by an external trigger source to a trigger target connected with the IEC connector 40 through the SMB connector 41, the CPLD chip 2 and the IEC connector 40; the software is triggered to a certain selected backboard trigger bus (triggered by the TTL of the IEC connector 40), that is, a software trigger signal generated by the CPLD chip 2 is routed to a trigger target connected to the IEC connector 40 through the IEC connector 40; an external trigger connector to the PXIe bus via software trigger (external trigger via the SMB connector 41), that is, a software trigger signal generated by the CPLD chip is routed to the trigger target connected to the SMB connector 41 via the SMB connector 41.
The software triggering is realized by configuring a CPLD chip 2 by the upper computer 1, the external triggering is input and output by an SMB connector 41 on the front panel of the controller, and the TTL triggering is input and output by an IEC connector 40 of the PXIe controller. Through verification, the CPLD chip on the PXIe controller carrier plate2, the pulse width and polarity of the generated software trigger signal can be accurately configured, and external trigger to TTL trigger, TTL trigger to external trigger, software trigger to external trigger, and software trigger to TTL trigger can be accurately realized. From the upper computer 1 through I2The C bus routes the software trigger signal generated by the CPLD chip 2 and other two trigger source signals to the trigger target.
Further, the CPLD chip passes through I2And the C bus acquires trigger configuration information respectively corresponding to external trigger and TTL trigger on the upper computer 1 so as to configure trigger routing information of the external trigger and the TTL trigger according to the trigger configuration information.
Third embodiment
As shown in fig. 3, the upper computer 1 controls the CPLD through the FPGA chip 5, the CPLD chip 2 is connected to the PXIe bus segment of the backplane of the PXIe system through the IEC connector 4, and the FPGA chip 5 sets a trigger route through the CPLD chip 2. This embodiment is applied to a PXIe backplane design, where a component 3 is 18 slots on a backplane, and is divided into 3 PXI bus segments: the slots 1-6 are PXI bus 1, the slots 7-12 are PXI bus segment2, and the slots 13-18 are PXI bus segment3, wherein TTL trigger sources can be inserted into the slots, the CPLD chip 2 is the EPM240F100 to realize trigger routing, and the FPGA chip 5 and the CPLD chip 2 are connected through a serial bus I2C, communication is carried out, a control command is sent to the CPLD chip 2, and trigger routing information is set. The default among different PXI bus segments is physical isolation, and if triggering among different PXI bus segments is needed, the configuration of a trigger route is needed to be realized through software control of the upper computer 1.
While the invention has been described in connection with specific embodiments thereof, it is to be understood that it is intended by the appended drawings and description that the invention may be embodied in other specific forms without departing from the spirit or scope of the invention.
Claims (4)
1. The device for generating the trigger signal in the PXIe bus is characterized by comprising an upper computer, a CPLD chip and an input/output connector, wherein the upper computer passes through I2C bus connected to the CPThe CPLD chip is connected with the input/output connector, the CPLD chip realizes software triggering, the upper computer routes the software triggering realized by the CPLD chip to a triggering target through the input/output connector, the input/output connector comprises an SMB connector and an IEC connector, the SMB connector realizes the input and the output of external triggering, the IEC connector realizes the input and the output of TTL triggering, and the upper computer controls the CPLD chip to realize the external triggering from the external triggering to the TTL triggering, from the TTL triggering to the external triggering, from the software triggering to the external triggering, and from the software triggering to the TTL triggering.
2. The generation apparatus as claimed in claim 1, wherein the CPLD chip passes through the I2And the C bus acquires configuration information corresponding to the software trigger on the upper computer so as to adjust the pulse width and the polarity of the software trigger according to the configuration information.
3. The generation apparatus as claimed in claim 1, wherein the CPLD chip passes through the I2And C, acquiring trigger configuration information corresponding to the external trigger and the TTL trigger respectively on the upper computer by the bus C so as to configure trigger routing information of the external trigger and the TTL trigger according to the trigger configuration information.
4. The generating device according to claim 1, further comprising a crystal oscillator source connected to the CPLD chip for synchronizing a clock reference of the CPLD chip with the crystal oscillator source.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510958033.1A CN106896754B (en) | 2015-12-18 | 2015-12-18 | Device for generating trigger signal in PXIe bus |
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| CN201510958033.1A CN106896754B (en) | 2015-12-18 | 2015-12-18 | Device for generating trigger signal in PXIe bus |
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| CN106896754A CN106896754A (en) | 2017-06-27 |
| CN106896754B true CN106896754B (en) | 2020-07-03 |
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| CN108303916A (en) * | 2017-12-18 | 2018-07-20 | 中国航空工业集团公司洛阳电光设备研究所 | A kind of high-precise synchronization triggering board based on PXI bus testing systems |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7437588B2 (en) * | 2005-08-03 | 2008-10-14 | Advantest Corporation | Circuit card synchronization within a standardized test instrumentation chassis |
| CN102141939B (en) * | 2010-02-01 | 2013-03-27 | 杭州华三通信技术有限公司 | Device capable of recording restart reason of whole machine |
| CN202008657U (en) * | 2011-01-31 | 2011-10-12 | 杭州士兰微电子股份有限公司 | Vector generation device for simulation test of integrated circuit |
| CN102929365B (en) * | 2012-10-29 | 2015-06-24 | 北京航天测控技术有限公司 | PXI/PXIe (Pedpherd Component Interconnect eXtensions for Instrumentation/Pedpherd Component Interconnect eXtensions for Instrumentation Express) bus-based panel instrument platform |
| CN102929758B (en) * | 2012-10-29 | 2014-09-03 | 北京航天测控技术有限公司 | Integrated triggering route device for PXI intelligent testing platform equipment |
| CN103678238B (en) * | 2013-12-30 | 2016-06-01 | 北京航天测控技术有限公司 | A kind of LXI-PXI PXIe adaption system |
| CN204347827U (en) * | 2014-12-11 | 2015-05-20 | 沃易升科技（北京）有限公司 | A kind of external high-speed memory system of expansion with PXI e interface adapter |
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