JP2009223583A - Abnormal state detection device for voltage driving element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an abnormal state detection device for a voltage driving element, capable of appropriately detecting, particularly, the abnormality of a connecting state of a terminal to which driving voltage is input as the abnormality of a voltage driving element. <P>SOLUTION: The abnormality detection device for the voltage driving element 1 for detecting the abnormality of an MOS-FET 10 comprises an abnormality detection means 6 which detects waveform of a gate voltage applied to the MOS-FET 10 in pulses through a resistor 3 at both sides of the resistor 3, and detects the abnormality of the MOS-FET 10 based on the detected waveforms. Concretely, the abnormality detection means 6 detects, based on the detected waveforms, a delay time of the waveform of the gate voltage detected after input to the resistor 3 to the waveform of the gate voltage detected before input to the resistor 3, and detects the abnormality of the MOS-FET 10 based on the detected delay time. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an abnormal state detection device for a voltage driving element.

MOS-FETs (corresponding to voltage drive elements) are widely used as switching elements because of their characteristics, and their use ranges are wide ranging from switching power supplies to motor control and audio amplifiers.
FIG. 5 is a diagram showing an equivalent circuit of a MOS-FET. The MOS-FET has a capacitance (Qgd, Qgs, and Qds) between each terminal (Drain terminal, Gate terminal, and Source terminal), and a body diode is provided between the Source-Drain.

Conventionally, when confirming whether or not this MOS-FET is normal, for example, by confirming the voltage Vf generated by the body diode, the connection state of the MOS-FET and the presence or absence of breakdown may be confirmed. . In addition, it is possible to confirm whether or not the MOS-FET is normal by applying a voltage between the gate and the source to operate the MOS-FET and observing a change in the voltage between the drain and the source or a change in the resistance value. there were.
For example, Patent Document 1 proposes a technique that is considered to be related to the present invention regarding abnormality detection of a voltage driving element.

JP 2000-78703 A

By the way, since the Gate terminal of the MOS-FET has a high input impedance, it is difficult to confirm the connection of the Gate terminal alone. For this reason, conventionally, the connection to the gate terminal of the MOS-FET is indirectly determined by applying electrodes to all the terminals of the MOS-FET. However, in this method, when the Gate terminal is disconnected, the Gate terminal becomes indeterminate, and it is determined whether the operation is disabled due to an abnormality of the element itself such as destruction, or whether the operation is disabled due to a simple connection error. could not. Therefore, in this case, it is determined whether or not the element is normal by performing further normal operation. However, if the Gate terminal is disconnected, the Gate terminal becomes indefinite and the Source− There was a situation in which a large current flowed between drains and the device was destroyed due to an abnormality check.
The MOS-FET is an element that is sensitive to static electricity. In this method, the element may be destroyed due to static electricity if the element is inadvertently touched directly.

  Therefore, the present invention has been made in view of the above problems, and provides a voltage drive element abnormality detection device capable of suitably detecting an abnormality in a connection state of a Gate terminal as an abnormality of a voltage drive element. With the goal.

  In order to solve the above problems, the present invention provides a voltage drive element abnormality detection device for detecting an abnormality of a voltage drive element, wherein the drive voltage applied in a pulse form to the voltage drive element via a resistor is provided. Is detected on both sides of the resistor, and an abnormality detecting means for detecting an abnormality of the voltage driving element based on the detected waveform is provided.

  Further, the present invention specifically relates to the waveform of the driving voltage detected after the input to the resistor with respect to the waveform of the driving voltage detected before the input to the resistor based on the detected waveform. The delay time may be detected, and the abnormality of the voltage driving element may be detected based on the detected delay time.

  Further, in the present invention, specifically, the abnormality detection unit detects an abnormality of the voltage drive element by determining that the voltage drive element is abnormal when the delay time is smaller than a predetermined value. It may be.

  Further, the present invention may be configured such that the driving voltage forms a rectangular wave.

  ADVANTAGE OF THE INVENTION According to this invention, the abnormality detection apparatus of the voltage drive element which can detect suitably the abnormality of the connection state of the terminal into which the drive voltage is input especially as abnormality of a voltage drive element can be provided.

  Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a diagram schematically showing a voltage drive element abnormality detection device (hereinafter simply referred to as an abnormality detection device) 1 according to this embodiment together with a MOS-FET (voltage drive element) 10. The abnormality detection apparatus 1 according to the present embodiment is configured to include a detection waveform generation means 2, a resistor 3, a delay detection signal generation means 4, and a connection confirmation means 5. The abnormality detection device 1 is configured as a control device including a microcomputer (not shown) composed of a CPU, a ROM, a RAM, and the like.

  The detection waveform generation means 2 has a configuration for generating and applying a gate voltage (drive voltage) in a pulse form. In the present embodiment, the detection waveform generation means 2 is specifically realized by a switching circuit, and a DC voltage is applied to the detection waveform generation means 2 from a power source (not shown). However, the present invention is not limited to this, and the detection waveform generating means 2 may be realized by, for example, a microcomputer configured to generate a clock. The detection waveform generating means 2 generates a gate voltage in a pulse form from the DC voltage applied by the switching operation, and also applies the gate voltage generated through the resistor 3 in a pulse form. The switching operation of the detection waveform generating means 2 is performed based on an input of operation means (not shown) such as a button or microcomputer control. The gate voltage generated in this way forms a rectangular wave.

  The detection waveform generating means 2 can be provided as a separate structure from the control device, instead of being incorporated in the control device. In this embodiment, the detection waveform generating means 2 generates a voltage waveform for inspection, but a voltage waveform used in normal operation may be used for inspection.

  The resistor 3 is connected in series to the Gate terminal of the MOS-FET 10 which is a terminal to which a driving voltage is input. A gate voltage generated by the detection waveform generating means 2 is input to the resistor 3 in a pulse shape. The resistor 3 can be provided as a separate structure from the control device instead of being incorporated in the control device. The resistor 3 may be an existing one in the circuit.

  The delay detection signal generation unit 4 detects the waveform of the gate voltage applied by the detection waveform generation unit 2 on both sides of the resistor 3 in accordance with the operation of the detection waveform generation unit 2, and based on the detected waveform, 3 is a configuration for detecting the delay time of the waveform of the gate voltage detected after input to the resistor 3 with respect to the waveform of the gate voltage detected before input to the resistor 3. In this regard, the delay detection signal generating means 4 is configured to detect a delay time by generating a delay detection signal as will be described later.

  The delay detection signal generating means 4 is realized by a microcomputer in this embodiment. That is, the delay detection signal generation means 4 is functionally realized by the microcomputer by the CPU executing processing based on the program stored in the ROM. However, the present invention is not limited to this, and the delay detection signal generation means 4 may be realized by dedicated hardware such as a circuit. In this case, the delay detection signal generation means 4 can be provided as a separate structure from the control device instead of being incorporated in the control device.

  The connection confirmation unit 5 is configured to detect an abnormality of the MOS-FET 10 based on the waveform detected by the delay detection signal generation unit 4. In this regard, the connection confirmation unit 5 is configured to detect abnormality of the MOS-FET 10 based on the delay time detected by the delay detection signal generation unit 4 based on the detected waveform. More specifically, the connection confirmation unit 5 is configured to detect an abnormality of the MOS-FET 10 by determining that the MOS-FET 10 is abnormal when the delay time is smaller than the predetermined value α. Yes. For example, a different value may be applied to the predetermined value α depending on the operating state of the MOS-FET 10 (for example, whether or not a potential is generated at the drain terminal). This is because, for example, whether or not the capacitor Qgd shown in FIG. 5 functions varies depending on whether or not a potential is generated at the drain terminal, and the bluntness of the waveform after the resistor 3 also changes accordingly.

  When the connection confirmation unit 5 determines that the MOS-FET 10 has an abnormality, it can be detected that the connection state of the Gate terminal is abnormal. As an abnormality in the connection state of the Gate terminal, specifically, for example, it can be detected that the Gate terminal is disconnected. However, the present invention is not limited to this, and an abnormality in the connection state of the Gate terminal includes, for example, a state in which a crack is generated in the solder connecting the Gate terminal, resulting in poor conduction. In addition, when the connection state of the Gate terminal is normal, for example, when the connection state of the Source terminal is abnormal, the connection confirmation unit 5 similarly determines that the MOS-FET 10 is abnormal, but the Source terminal or the Drain terminal The connection confirmation means 5 can determine the connection state of the Gate terminal by determining the connection state in FIG.

  In this embodiment, the connection confirmation means 5 is realized by a microcomputer. That is, the CPU executes the processing based on the program stored in the ROM, so that the connection confirmation unit 5 is functionally realized by the microcomputer. However, the present invention is not limited to this, and the connection confirmation unit 5 may be realized by dedicated hardware such as a circuit. In this case, the connection confirmation means 5 can be provided as a separate structure from the control device instead of being incorporated in the control device. In this embodiment, the abnormality detection means 6 is realized by the delay detection signal generation means 4 and the connection confirmation means 5.

  Next, a change in the gate voltage of the rectangular wave applied to the Gate terminal will be described in detail with reference to FIG. The gate voltage is input to the resistor 3 as a rectangular wave signal. The waveform of this signal is greatly dull after input to the resistor 3 by the resistor 3 and the capacitor C (corresponding to the Gate capacitance of the MOS-FET 10). For this reason, when the Gate terminal is normally connected, a delay occurs in signal propagation.

  Next, a method for generating a delay detection signal performed by the delay detection signal generating means 4 will be described in detail with reference to FIG. The delay detection signal generation means 4 reads the time corresponding to a predetermined potential (here, V1) for each of the waveforms detected before and after the resistor 3. Thereby, a delay detection signal as shown in the figure can be generated. The delay detection signal has a larger pulse width (time width) as the delay time increases. Therefore, the delay time can be detected by measuring the pulse width. In addition, since the delay time can be detected as a time constant depending on the potential at the time of reading, it is a parameter having a correlation that the gate capacitance of the MOS-FET 10 can be detected together with the known resistance value of the resistor 3. ing. Therefore, it is possible to determine whether or not the Gate terminal of the MOS-FET 10 is normally connected based on this delay time.

According to this abnormality detection device 1, by connecting to the Gate terminal, it is possible to determine an abnormality with the MOS-FET 10 mounted on the substrate. For this reason, with the recent miniaturization of products, it is possible to easily determine an abnormality in the connection state of the Gate terminal even for a MOS-FET having a shape and structure in which the solder state cannot be directly visually confirmed during manufacture.
Moreover, according to this abnormality detection apparatus 1, automatic judgment can also be performed by microcomputer control. For this reason, the abnormality detection apparatus 1 can be applied to a self-diagnosis function inside a product such as a pre-startup test in addition to a quality inspection at the time of manufacture. Next, an example of control when automatic determination is performed in the pre-startup test will be described in detail with reference to the flowchart of FIG.

  The CPU executes processing for generating a rectangular-wave gate voltage when the power of the product in which the abnormality detection device 1 is incorporated is turned on and the power is supplied (step S11). At this time, the CPU specifically executes processing for switching the detection waveform generating means 2. Thereby, a rectangular wave gate voltage is generated, and the generated gate voltage is applied to the Gate terminal via the resistor 3. At this time, the CPU executes a process of detecting the waveform of the gate voltage around the resistor 3 (step S12), and executes a process of detecting a delay time based on the detected waveform (step S13).

Further, the CPU executes a process of determining whether or not the delay time is smaller than the predetermined value α based on the detected delay time (step S14). If the determination is negative, the CPU executes a process for determining that the MOS-FET 10 is normal (step S16), and ends the process of this flowchart. On the other hand, if an affirmative determination is made in step S14, the CPU executes a process for determining that there is an abnormality in the MOS-FET 10 (step S15), and ends the process of this flowchart. Thereby, an abnormality in the connection state of the Gate terminal can be automatically determined by the pre-startup test.
As described above, the abnormality detection device 1 can suitably detect an abnormality of the connection state of the Gate terminal as an abnormality of the MOS-FET 10 in particular.

  The embodiment described above is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, the voltage driving element only needs to have a capacitance at a terminal to which a driving voltage is input, and may be a junction type FET or the like.

1 is a diagram schematically showing an abnormality detection device 1 together with a MOS-FET 10. FIG. It is explanatory drawing for demonstrating the change of the gate voltage of the rectangular wave applied to a Gate terminal. It is explanatory drawing which illustrates typically the generation method of the delay detection signal which the delay detection signal generation means 4 performs. It is a figure which shows an example of the control in the case of performing automatic judgment by the test before starting in the product incorporating the abnormality detection apparatus 1. It is a figure which shows the equivalent circuit of MOS-FET.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Abnormality detection apparatus 2 Detection waveform generation means 3 Resistance 4 Delay detection signal generation means 5 Connection confirmation means 6 Abnormality detection means 10 MOS-FET

Claims (4)

An apparatus for detecting an abnormality of a voltage driving element for detecting an abnormality of the voltage driving element,
An abnormality detecting means for detecting a waveform of a driving voltage applied in a pulse form to the voltage driving element via a resistor on both sides of the resistor and detecting an abnormality of the voltage driving element based on the detected waveform An abnormality detection device for a voltage drive element, comprising: An apparatus for detecting an abnormality of a voltage driving element according to claim 1,
The abnormality detecting means detects a delay time of the waveform of the driving voltage detected after input to the resistor with respect to the waveform of the driving voltage detected before input to the resistor based on the detected waveform; An abnormality detection apparatus for a voltage driving element, wherein an abnormality of the voltage driving element is detected based on the detected delay time. An apparatus for detecting an abnormality of a voltage-driven element according to claim 2,
The abnormality detecting means detects an abnormality of the voltage driving element by determining that the voltage driving element is abnormal when the delay time is smaller than a predetermined value. Anomaly detection device. An apparatus for detecting an abnormality of a voltage driving element according to any one of claims 1 to 3,
An abnormality detecting device for a voltage driving element, wherein the driving voltage forms a rectangular wave.

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