JP5213489B2 - Abnormal state detection device for voltage drive element - Google Patents

Abnormal state detection device for voltage drive element Download PDF

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JP5213489B2
JP5213489B2 JP2008066789A JP2008066789A JP5213489B2 JP 5213489 B2 JP5213489 B2 JP 5213489B2 JP 2008066789 A JP2008066789 A JP 2008066789A JP 2008066789 A JP2008066789 A JP 2008066789A JP 5213489 B2 JP5213489 B2 JP 5213489B2
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清志 中村
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Alpine Electronics Inc
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Description

本発明は電圧駆動素子の異常状態検出装置に関する。   The present invention relates to an abnormal state detection device for a voltage driving element.

MOS−FET(電圧駆動素子に相当)は、その特性からスイッチング素子として広く利用されており、その利用範囲は例えばスイッチング電源のほかモータ制御やオーディオアンプなど多岐に亘っている。
図5はMOS−FETの等価回路を示す図である。MOS−FETは各端子(Drain端子、Gate端子およびSource端子)間に容量(Qgd、QgsおよびQds)を有しており、且つSource−Drain間にはボディダイオードを備えている。
MOS-FETs (corresponding to voltage drive elements) are widely used as switching elements because of their characteristics, and their use ranges are wide ranging from switching power supplies to motor control and audio amplifiers.
FIG. 5 is a diagram showing an equivalent circuit of a MOS-FET. The MOS-FET has a capacitance (Qgd, Qgs, and Qds) between each terminal (Drain terminal, Gate terminal, and Source terminal), and a body diode is provided between the Source-Drain.

従来、このMOS−FETが正常であるか否かを確認するにあたっては、例えばボディダイオードによって発生する電圧Vfを確認することで、MOS−FETの接続状態や破壊の有無を確認することがあった。また、Gate−Source間に電圧を加えてMOS−FETを動作させ、Drain−Source間の電圧変化や抵抗値の変化を見ることで、MOS−FETが正常であるか否かを確認することがあった。
電圧駆動素子の異常検出に関し、本発明と関連性があると考えられる技術が例えば特許文献1で提案されている。
Conventionally, when confirming whether or not this MOS-FET is normal, for example, by confirming the voltage Vf generated by the body diode, the connection state of the MOS-FET and the presence or absence of breakdown may be confirmed. . In addition, it is possible to confirm whether or not the MOS-FET is normal by applying a voltage between the gate and the source to operate the MOS-FET and observing a voltage change between the drain and the source and a change in the resistance value. there were.
For example, Patent Document 1 proposes a technique that is considered to be related to the present invention regarding abnormality detection of a voltage driving element.

特開2000−78703号公報JP 2000-78703 A

ところで、MOS−FETのGate端子は入力インピーダンスが高いため、Gate端子の接続確認は単独では難しい。このため従来は、MOS−FETの全ての端子に電極を当てることで、MOS−FETのGate端子の接続を間接的に判断することになっていた。しなしながら、この方法ではGate端子が外れていた場合にGate端子が不定となり、破壊など素子そのものの異常によって動作不能となっているのか、単純な接続ミスによって動作不能になっているのかが判断できなかった。このためこの場合には、さらに通常の動作を行うことで素子が正常であるか否かを判断していたが、Gate端子が外れている場合には、Gate端子が不定となることでSource−Drain間に大電流が流れ、異常確認により素子を破壊してしまうという事態が起こっていた。
またMOS−FETは静電気に弱い素子であり、この方法では不用意に素子に直接触れたりすることで、静電気により素子を破壊してしまうこともあった。
By the way, since the Gate terminal of the MOS-FET has a high input impedance, it is difficult to confirm the connection of the Gate terminal alone. For this reason, conventionally, the connection of the gate terminal of the MOS-FET is indirectly determined by applying electrodes to all the terminals of the MOS-FET. However, in this method, when the Gate terminal is disconnected, the Gate terminal becomes indeterminate, and it is determined whether the operation is disabled due to an abnormality of the element itself such as destruction, or whether the operation is disabled due to a simple connection error. could not. Therefore, in this case, it is determined whether or not the element is normal by performing further normal operation. However, if the Gate terminal is disconnected, the Gate terminal becomes indefinite and the Source− There was a situation in which a large current flowed between drains and the device was destroyed due to an abnormality check.
The MOS-FET is an element that is sensitive to static electricity. In this method, the element may be destroyed due to static electricity if the element is inadvertently touched directly.

そこで本発明は上記の課題に鑑みてなされたものであり、電圧駆動素子の異常として、特にGate端子の接続状態の異常を好適に検出することができる電圧駆動素子の異常検出装置を提供することを目的とする。   Therefore, the present invention has been made in view of the above problems, and provides a voltage drive element abnormality detection device capable of suitably detecting an abnormality in a connection state of a Gate terminal as an abnormality of a voltage drive element. With the goal.

上記課題を解決するために、本発明は電圧駆動素子の異常を検出するための電圧駆動素子の異常検出装置であって、前記電圧駆動素子に抵抗を介してパルス状に印加された駆動用電圧の波形を前記抵抗の両側でそれぞれ検出するとともに、検出した波形に基づき、前記電圧駆動素子の異常を検出する異常検出手段を備えることを特徴とする。   In order to solve the above problems, the present invention provides a voltage drive element abnormality detection device for detecting an abnormality of a voltage drive element, wherein the drive voltage applied in a pulse form to the voltage drive element via a resistor is provided. Is detected on both sides of the resistor, and an abnormality detecting means for detecting an abnormality of the voltage driving element based on the detected waveform is provided.

また本発明は具体的には前記異常検出手段が、検出した波形に基づき、前記抵抗への入力前に検出した前記駆動用電圧の波形に対する前記抵抗への入力後に検出した前記駆動用電圧の波形の遅延時間を検出するとともに、検出した遅延時間に基づいて、前記電圧駆動素子の異常を検出する構成であってもよい。   Further, the present invention specifically relates to the waveform of the driving voltage detected after the input to the resistor with respect to the waveform of the driving voltage detected before the input to the resistor based on the detected waveform. The delay time may be detected, and the abnormality of the voltage driving element may be detected based on the detected delay time.

また本発明は具体的には前記異常検出手段が、前記遅延時間が所定値よりも小さい場合に、前記電圧駆動素子に異常があると判断することで、前記電圧駆動素子の異常を検出する構成であってもよい。   Further, in the present invention, specifically, the abnormality detection unit detects an abnormality of the voltage drive element by determining that the voltage drive element is abnormal when the delay time is smaller than a predetermined value. It may be.

また本発明は前記駆動用電圧が矩形波を形成する構成であってもよい。   Further, the present invention may be configured such that the driving voltage forms a rectangular wave.

本発明によれば、電圧駆動素子の異常として、特に駆動用電圧が入力される端子の接続状態の異常を好適に検出することができる電圧駆動素子の異常検出装置を提供できる。   ADVANTAGE OF THE INVENTION According to this invention, the abnormality detection apparatus of the voltage drive element which can detect suitably the abnormality of the connection state of the terminal into which the drive voltage is input especially as abnormality of a voltage drive element can be provided.

以下、本発明を実施するための最良の形態を図面と共に詳細に説明する。   Hereinafter, the best mode for carrying out the present invention will be described in detail with reference to the drawings.

図1は本実施例に係る電圧駆動素子の異常検出装置(以下、単に異常検出装置と称す)1をMOS−FET(電圧駆動素子)10とともに模式的に示す図である。本実施例に係る異常検出装置1は検出用波形生成手段2と、抵抗3と、遅延検出信号生成手段4と、接続確認手段5とを有して構成されている。異常検出装置1はCPU、ROM、RAMなどで構成される図示しないマイコンを含む制御装置として構成されている。   FIG. 1 is a diagram schematically showing a voltage drive element abnormality detection device (hereinafter simply referred to as an abnormality detection device) 1 according to this embodiment together with a MOS-FET (voltage drive element) 10. The abnormality detection apparatus 1 according to the present embodiment is configured to include a detection waveform generation unit 2, a resistor 3, a delay detection signal generation unit 4, and a connection confirmation unit 5. The abnormality detection device 1 is configured as a control device including a microcomputer (not shown) composed of a CPU, a ROM, a RAM, and the like.

検出用波形生成手段2はゲート電圧(駆動用電圧)をパルス状に生成および印加するための構成である。検出用波形生成手段2は本実施例では具体的にはスイッチング回路で実現されており、検出用波形生成手段2には図示しない電源から直流電圧が印加されている。但しこれに限られず、検出用波形生成手段2は例えばクロックを発生させるように構成されたマイコン等によって実現されてもよい。検出用波形生成手段2はスイッチング動作によって印加された直流電圧からゲート電圧をパルス状に生成するとともに、抵抗3を介して生成したゲート電圧をパルス状に印加する。検出用波形生成手段2のスイッチング動作は例えば釦等の図示しない操作手段の入力やマイコン制御に基づき行われる。このようにして生成されたゲート電圧は矩形波を形成する。   The detection waveform generation means 2 has a configuration for generating and applying a gate voltage (drive voltage) in a pulse form. In the present embodiment, the detection waveform generation means 2 is specifically realized by a switching circuit, and a DC voltage is applied to the detection waveform generation means 2 from a power source (not shown). However, the present invention is not limited to this, and the detection waveform generating means 2 may be realized by, for example, a microcomputer configured to generate a clock. The detection waveform generating means 2 generates a gate voltage in a pulse form from the DC voltage applied by the switching operation, and also applies the gate voltage generated through the resistor 3 in a pulse form. The switching operation of the detection waveform generating means 2 is performed based on an input of operation means (not shown) such as a button or microcomputer control. The gate voltage generated in this way forms a rectangular wave.

なお、検出用波形生成手段2は制御装置に組み込む代わりに、制御装置とは別体の構成として備えることもできる。また本実施例では検出用波形生成手段2が検査用に電圧波形を生成しているが、通常の動作で利用する電圧の波形が検査用に用いられてもよい。   The detection waveform generating means 2 can be provided as a separate structure from the control device, instead of being incorporated in the control device. In this embodiment, the detection waveform generating means 2 generates a voltage waveform for inspection, but a voltage waveform used in normal operation may be used for inspection.

抵抗3は駆動用電圧が入力される端子であるMOS−FET10のGate端子に直列接続されている。抵抗3には検出用波形生成手段2が生成したゲート電圧がパルス状に入力される。なお、抵抗3は制御装置に組み込む代わりに、制御装置とは別体の構成として備えることもできる。また抵抗3は回路に既設のものであってもよい。   The resistor 3 is connected in series to the Gate terminal of the MOS-FET 10 which is a terminal to which a driving voltage is input. A gate voltage generated by the detection waveform generating means 2 is input to the resistor 3 in a pulse shape. The resistor 3 can be provided as a separate structure from the control device instead of being incorporated in the control device. The resistor 3 may be an existing one in the circuit.

遅延検出信号生成手段4は検出用波形生成手段2の作動に応じて、検出用波形生成手段2が印加したゲート電圧の波形を抵抗3の両側でそれぞれ検出するとともに、検出した波形に基づき、抵抗3への入力前に検出したゲート電圧の波形に対する抵抗3への入力後に検出したゲート電圧の波形の遅延時間を検出するための構成である。この点、遅延検出信号生成手段4は後述するように遅延検出信号を生成することによって、遅延時間を検出するように構成されている。   The delay detection signal generation unit 4 detects the waveform of the gate voltage applied by the detection waveform generation unit 2 on both sides of the resistor 3 in accordance with the operation of the detection waveform generation unit 2, and based on the detected waveform, 3 is a configuration for detecting the delay time of the waveform of the gate voltage detected after input to the resistor 3 with respect to the waveform of the gate voltage detected before input to the resistor 3. In this regard, the delay detection signal generating means 4 is configured to detect a delay time by generating a delay detection signal as will be described later.

遅延検出信号生成手段4は本実施例ではマイコンで実現されている。すなわちROMに格納されたプログラムに基づきCPUが処理を実行することで、遅延検出信号生成手段4がマイコンによって機能的に実現されている。但しこれに限られず、遅延検出信号生成手段4は回路など専用のハードウェアによって実現されてもよい。この場合、遅延検出信号生成手段4は制御装置に組み込む代わりに、制御装置とは別体の構成として備えることもできる。   The delay detection signal generating means 4 is realized by a microcomputer in this embodiment. That is, the delay detection signal generation means 4 is functionally realized by the microcomputer by the CPU executing processing based on the program stored in the ROM. However, the present invention is not limited to this, and the delay detection signal generation means 4 may be realized by dedicated hardware such as a circuit. In this case, the delay detection signal generation means 4 can be provided as a separate structure from the control device instead of being incorporated in the control device.

接続確認手段5は遅延検出信号生成手段4が検出した波形に基づき、MOS−FET10の異常を検出するように構成されている。この点、接続確認手段5は具体的には検出した波形に基づいて遅延検出信号生成手段4が検出した遅延時間に基づき、MOS−FET10の異常を検出するように構成されている。また接続確認手段5はさらに具体的には、遅延時間が所定値αよりも小さい場合に、MOS−FET10に異常があると判断することで、MOS−FET10の異常を検出するように構成されている。なお、所定値αは例えばMOS−FET10の動作状態(例えばDrain端子に電位が発生しているか否かなど)によって異なる値が適用されてもよい。これは例えばDrain端子に電位が発生しているか否かによって図5に示す容量Qgdが機能するか否かが変化し、これにより抵抗3後の波形の鈍り具合も変化するためである。   The connection confirmation unit 5 is configured to detect an abnormality of the MOS-FET 10 based on the waveform detected by the delay detection signal generation unit 4. In this regard, the connection confirmation unit 5 is configured to detect abnormality of the MOS-FET 10 based on the delay time detected by the delay detection signal generation unit 4 based on the detected waveform. More specifically, the connection confirmation unit 5 is configured to detect an abnormality of the MOS-FET 10 by determining that the MOS-FET 10 is abnormal when the delay time is smaller than the predetermined value α. Yes. For example, a different value may be applied to the predetermined value α depending on the operating state of the MOS-FET 10 (for example, whether or not a potential is generated at the drain terminal). This is because, for example, whether or not the capacitor Qgd shown in FIG. 5 functions varies depending on whether or not a potential is generated at the drain terminal, and the bluntness of the waveform after the resistor 3 also changes accordingly.

接続確認手段5がMOS−FET10に異常があると判断した場合には、Gate端子の接続状態に異常があることを検出することができる。またGate端子の接続状態の異常としては、具体的には例えばGate端子が外れていることを検出できる。但しこれに限られず、Gate端子の接続状態の異常には、例えばGate端子を接続する半田にクラックが発生し、導通不良になっている状態なども含まれる。またGate端子の接続状態が正常である代わりに、例えばSource端子の接続状態が異常である場合にも接続確認手段5は同様にMOS−FET10に異常があると判断するが、Source端子やDrain端子の接続状態については従来技術等で判断することで、接続確認手段5でGate端子の接続状態を判断することができる。   When the connection confirmation unit 5 determines that the MOS-FET 10 has an abnormality, it can be detected that the connection state of the Gate terminal is abnormal. As an abnormality in the connection state of the Gate terminal, specifically, for example, it can be detected that the Gate terminal is disconnected. However, the present invention is not limited to this, and abnormalities in the connection state of the Gate terminal include, for example, a state in which a crack is generated in the solder connecting the Gate terminal, resulting in poor conduction. In addition, when the connection state of the Gate terminal is normal, for example, when the connection state of the Source terminal is abnormal, the connection confirmation unit 5 similarly determines that the MOS-FET 10 is abnormal, but the Source terminal or the Drain terminal The connection confirmation means 5 can determine the connection state of the Gate terminal by determining the connection state in FIG.

接続確認手段5は本実施例ではマイコンで実現されている。すなわち、ROMに格納されたプログラムに基づきCPUが処理を実行することで、接続確認手段5がマイコンによって機能的に実現されている。但しこれに限られず、接続確認手段5は回路など専用のハードウェアによって実現されてもよい。この場合、接続確認手段5は制御装置に組み込む代わりに、制御装置とは別体の構成として備えることもできる。本実施例では遅延検出信号生成手段4と接続確認手段5とで異常検出手段6が実現されている。   In this embodiment, the connection confirmation means 5 is realized by a microcomputer. That is, the CPU executes the processing based on the program stored in the ROM, so that the connection confirmation unit 5 is functionally realized by the microcomputer. However, the present invention is not limited to this, and the connection confirmation unit 5 may be realized by dedicated hardware such as a circuit. In this case, the connection confirmation means 5 can be provided as a separate structure from the control device instead of being incorporated in the control device. In this embodiment, the abnormality detection means 6 is realized by the delay detection signal generation means 4 and the connection confirmation means 5.

次にGate端子に印加する矩形波のゲート電圧の変化について図2を用いて詳述する。ゲート電圧は抵抗3に矩形波信号として入力される。この信号は抵抗3およびコンデンサC(MOS−FET10のGate容量に相当)によって、抵抗3への入力後に波形が大きく鈍る。このためGate端子が正常に接続されている場合には、信号の伝播に遅延が発生することになる。   Next, a change in the gate voltage of the rectangular wave applied to the Gate terminal will be described in detail with reference to FIG. The gate voltage is input to the resistor 3 as a rectangular wave signal. The waveform of this signal is greatly dull after input to the resistor 3 by the resistor 3 and the capacitor C (corresponding to the Gate capacitance of the MOS-FET 10). For this reason, when the Gate terminal is normally connected, a delay occurs in signal propagation.

次に遅延検出信号生成手段4が行う遅延検出信号の生成方法について図3を用いて詳述する。遅延検出信号生成手段4は、抵抗3の前後で検出した波形それぞれにつき、所定の電位(ここではV1)に対応する時間を読み取る。これにより、図示のような遅延検出信号を生成することができる。この遅延検出信号は遅延時間が大きいほど、パルス幅(時間幅)が大きくなる。したがってこのパルス幅を測定することで、遅延時間を検出することができる。また遅延時間は時間を読み取る際の電位によって時定数として検出できるものであることから、抵抗3の既知の抵抗値とともにMOS−FET10のゲート容量を検出することもできるという相関関係を有するパラメータとなっている。このためこの遅延時間によってMOS−FET10のGate端子が正常に接続されているか否かを判断することができる。   Next, a method for generating a delay detection signal performed by the delay detection signal generating means 4 will be described in detail with reference to FIG. The delay detection signal generation means 4 reads the time corresponding to a predetermined potential (here, V1) for each of the waveforms detected before and after the resistor 3. Thereby, a delay detection signal as shown in the figure can be generated. The delay detection signal has a larger pulse width (time width) as the delay time increases. Therefore, the delay time can be detected by measuring the pulse width. In addition, since the delay time can be detected as a time constant depending on the potential at the time of reading, it is a parameter having a correlation that the gate capacitance of the MOS-FET 10 can be detected together with the known resistance value of the resistor 3. ing. Therefore, it is possible to determine whether or not the Gate terminal of the MOS-FET 10 is normally connected based on this delay time.

この異常検出装置1によれば、Gate端子に接続することで、MOS−FET10を基板に搭載した状態で異常を判断することができる。このため昨今の製品小型化に伴い、製造時に半田状態を直接目視で確認できないような形状や構造のMOS−FETについても、Gate端子の接続状態の異常を容易に判断することができる。
またこの異常検出装置1によれば、マイコン制御で自動判断を行うこともできる。このためこの異常検出装置1は製造時の品質検査のほか、例えば起動前テストなど製品内部での自己診断機能に応用することもできる。次に起動前テストで自動判断を行う場合の制御の一例を図4にフローチャートを用いて詳述する。
According to this abnormality detection device 1, by connecting to the Gate terminal, it is possible to determine an abnormality with the MOS-FET 10 mounted on the substrate. For this reason, with the recent miniaturization of products, it is possible to easily determine an abnormality in the connection state of the Gate terminal even for a MOS-FET having a shape and structure in which the solder state cannot be directly visually confirmed during manufacture.
Moreover, according to this abnormality detection apparatus 1, automatic judgment can also be performed by microcomputer control. For this reason, the abnormality detection apparatus 1 can be applied to a self-diagnosis function inside a product such as a pre-startup test in addition to a quality inspection at the time of manufacture. Next, an example of control when automatic determination is performed in the pre-startup test will be described in detail with reference to the flowchart of FIG.

CPUは異常検出装置1が組み込まれた製品の電源がONになり、電源が供給されたときに、矩形波のゲート電圧を生成する処理を実行する(ステップS11)。このときCPUは具体的には検出用波形生成手段2をスイッチング動作させるための処理を実行する。これにより矩形波のゲート電圧が生成されるとともに、生成されたゲート電圧が抵抗3を介してGate端子に印加される。このときCPUは抵抗3前後のゲート電圧の波形を検出する処理を実行するとともに(ステップS12)、検出した波形に基づいて、遅延時間を検出する処理を実行する(ステップS13)。   The CPU executes processing for generating a rectangular-wave gate voltage when the power of the product in which the abnormality detection device 1 is incorporated is turned on and the power is supplied (step S11). At this time, the CPU specifically executes processing for switching the detection waveform generating means 2. Thereby, a rectangular wave gate voltage is generated, and the generated gate voltage is applied to the Gate terminal via the resistor 3. At this time, the CPU executes a process of detecting the waveform of the gate voltage around the resistor 3 (step S12), and executes a process of detecting a delay time based on the detected waveform (step S13).

さらにCPUは検出した遅延時間に基づいて、遅延時間が所定値αよりも小さいか否かを判定する処理を実行する(ステップS14)。否定判定であれば、CPUはMOS−FET10が正常であると判断する処理を実行し(ステップS16)、本フローチャートの処理を終了する。一方、ステップS14で肯定判定であれば、CPUはMOS−FET10に異常があると判断する処理を実行し(ステップS15)、本フローチャートの処理を終了する。これにより、Gate端子の接続状態の異常を起動前テストで自動判断できる。
このように異常検出装置1はMOS−FET10の異常として、特にGate端子の接続状態の異常を好適に検出することができる。
Further, the CPU executes a process of determining whether or not the delay time is smaller than the predetermined value α based on the detected delay time (step S14). If the determination is negative, the CPU executes processing for determining that the MOS-FET 10 is normal (step S16), and ends the processing of this flowchart. On the other hand, if an affirmative determination is made in step S14, the CPU executes a process for determining that there is an abnormality in the MOS-FET 10 (step S15), and ends the process of this flowchart. Thereby, an abnormality in the connection state of the Gate terminal can be automatically determined by the pre-startup test.
As described above, the abnormality detection apparatus 1 can suitably detect an abnormality in the connection state of the Gate terminal as an abnormality in the MOS-FET 10 in particular.

上述した実施例は本発明の好適な実施の例である。但し、これに限定されるものではなく、本発明の要旨を逸脱しない範囲内において種々変形実施可能である。例えば電圧駆動素子は駆動用電圧が入力される端子に容量を有するものであればよく、接合タイプのFETなどであってもよい。   The embodiment described above is a preferred embodiment of the present invention. However, the present invention is not limited to this, and various modifications can be made without departing from the scope of the present invention. For example, the voltage driving element only needs to have a capacitance at a terminal to which a driving voltage is input, and may be a junction type FET or the like.

異常検出装置1をMOS−FET10とともに模式的に示す図である。1 is a diagram schematically showing an abnormality detection device 1 together with a MOS-FET 10. FIG. Gate端子に印加する矩形波のゲート電圧の変化を説明するための説明図である。It is explanatory drawing for demonstrating the change of the gate voltage of the rectangular wave applied to a Gate terminal. 遅延検出信号生成手段4が行う遅延検出信号の生成方法を模式的に説明する説明図である。It is explanatory drawing which illustrates typically the generation method of the delay detection signal which the delay detection signal generation means 4 performs. 異常検出装置1を組み込んだ製品において、起動前テストで自動判断を行う場合の制御の一例を示す図である。It is a figure which shows an example of the control in the case of performing automatic judgment by the test before starting in the product incorporating the abnormality detection apparatus 1. MOS−FETの等価回路を示す図である。It is a figure which shows the equivalent circuit of MOS-FET.

符号の説明Explanation of symbols

1 異常検出装置
2 検出用波形生成手段
3 抵抗
4 遅延検出信号生成手段
5 接続確認手段
6 異常検出手段
10 MOS−FET
DESCRIPTION OF SYMBOLS 1 Abnormality detection apparatus 2 Detection waveform generation means 3 Resistance 4 Delay detection signal generation means 5 Connection confirmation means 6 Abnormality detection means 10 MOS-FET

Claims (4)

電圧駆動素子の異常を検出するための電圧駆動素子の異常検出装置であって、
前記電圧駆動素子に抵抗を介してパルス状に印加された駆動用電圧の波形を前記抵抗の両側でそれぞれ検出するとともに、検出した波形に基づき、前記電圧駆動素子の異常を検出する異常検出手段を備えることを特徴とする電圧駆動素子の異常検出装置。
An apparatus for detecting an abnormality of a voltage driving element for detecting an abnormality of the voltage driving element,
An abnormality detecting means for detecting a waveform of a driving voltage applied in a pulse form to the voltage driving element via a resistor on both sides of the resistor and detecting an abnormality of the voltage driving element based on the detected waveform An abnormality detection device for a voltage drive element, comprising:
請求項1記載の電圧駆動素子の異常検出装置であって、
前記異常検出手段が、検出した波形に基づき、前記抵抗への入力前に検出した前記駆動用電圧の波形に対する前記抵抗への入力後に検出した前記駆動用電圧の波形の遅延時間を検出するとともに、検出した遅延時間に基づいて、前記電圧駆動素子の異常を検出することを特徴とする電圧駆動素子の異常検出装置。
An apparatus for detecting an abnormality of a voltage driving element according to claim 1,
Based on the detected waveform, the abnormality detecting means detects a delay time of the waveform of the driving voltage detected after input to the resistor with respect to the waveform of the driving voltage detected before input to the resistor, An abnormality detection device for a voltage driving element, wherein an abnormality of the voltage driving element is detected based on the detected delay time.
請求項2記載の電圧駆動素子の異常検出装置であって、
前記異常検出手段が、前記遅延時間が所定値よりも小さい場合に、前記電圧駆動素子に異常があると判断することで、前記電圧駆動素子の異常を検出することを特徴とする電圧駆動素子の異常検出装置。
An apparatus for detecting an abnormality of a voltage-driven element according to claim 2,
The abnormality detecting means detects an abnormality of the voltage driving element by determining that the voltage driving element is abnormal when the delay time is smaller than a predetermined value. Anomaly detection device.
請求項1から3いずれか1項記載の電圧駆動素子の異常検出装置であって、
前記駆動用電圧が矩形波を形成することを特徴とする電圧駆動素子の異常検出装置。
An apparatus for detecting an abnormality of a voltage driving element according to any one of claims 1 to 3,
The voltage drive element abnormality detection device, wherein the drive voltage forms a rectangular wave.
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