JP2009218413A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device such that the channel width of a MOSFET diode is efficiently widened and that use efficiency of a layout is improved, and a method of manufacturing the same. <P>SOLUTION: The semiconductor device has a Si layer 5 formed on a Si substrate 1 with an insulating layer 3 interposed, a gate insulating film 13 formed on the Si layer 5, a gate electrode 15 formed on the gate insulating film 13, S/D layers 17 and 18 formed on the Si layer 5 on both sides of the gate electrode 15, and wiring 31 connecting the S/D layer 18 and gate electrode 15 to each other, the gate electrode 15 being extended zigzag to the right and the left in an X direction in plan view. In such constitution, a channel region in a zigzag shape is formed on an Si layer 5 in an active region, for example, in a square or rectangular shape, and the channel width of the MOSFET diode is efficiently widened. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MOSFET diode formed by SOI technology and a manufacturing method thereof.

  Technology (ie, SOI technology) for forming a semiconductor device on a thin semiconductor film formed on an insulating film has been developed and put into practical use as a low power semiconductor device for the next generation. On the other hand, Spring Drive (registered trademark) is a new power source that generates power using the power that the mainspring can dissolve, and this is also expected to be applied to the next-generation low-power system in consideration of the environment. .

When a spring drive (hereinafter referred to as SD) is used as power for driving an integrated circuit formed by SOI technology, the output of SD is an AC voltage, and therefore a power supply circuit for converting it into a DC voltage is required. In particular, diodes are indispensable for power supply circuits, but at present, discrete components that are attached to the outside of the IC chip are used as such rectifier diodes, which is one factor that hinders system miniaturization. It has become. Therefore, if the rectifier diode can be built in the IC chip, the system can be made more compact, and the cost can be reduced and the yield can be improved by reducing the number of components.
JP 2000-58826 A JP-A-6-13574

  By the way, when the rectifier diode built in the IC chip is manufactured by the SOI technology, it is considered that it is difficult to manufacture a PN junction diode unlike the case of Bulk silicon because the SOI layer is thin. Therefore, it is conceivable to use a MOS field effect transistor (MOS transistor) as a diode. In order to obtain a necessary forward current in this type of diode (hereinafter referred to as a MOSFET diode), a channel length is required. Is required to be shortened or the channel width is increased.

However, the shortening of the channel length has a limit in processing by the photolithography technique. Therefore, widening the channel width is a realistic solution for increasing the forward current. In this case, however, as shown in FIG. 9, for example, the gate electrode 91 of the MOSFET diode 90 is extremely extreme in one direction. However, there is a problem that the use efficiency of the layout is lowered.
Accordingly, the present invention has been made in view of such circumstances, and provides a semiconductor device and a manufacturing method thereof that can efficiently increase the channel width of the MOSFET diode and improve the utilization efficiency of the layout. With the goal.

[Invention 1-3] The semiconductor device of Invention 1 is formed on a semiconductor layer formed on a substrate via an insulating layer, a gate insulating film formed on the semiconductor layer, and the gate insulating film. A gate electrode; a source or drain formed in each of the semiconductor layers on both sides of the gate electrode; and a wiring connecting one of the source or drain and the gate electrode. It has a shape that is stretched while swinging left and right in one direction. Here, the “substrate” is, for example, a silicon substrate, the “insulating layer” is, for example, a silicon oxide film (SiO ₂ ), and the “semiconductor layer” is, for example, a silicon layer.
A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the gate electrode includes a first portion along the one direction in plan view and a first portion along the other direction perpendicular to the one direction in plan view. The first portion and the second portion are alternately connected to each other.

A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the second aspect, comprising: an element isolation film formed on the insulating layer so as to surround the second semiconductor layer in a plan view; and a region surrounded by the element isolation film The first portion and the second portion are respectively formed on the semiconductor layer via the gate insulating film. Here, the “region surrounded by the element isolation film” is also referred to as an active region.
According to the semiconductor devices of the first to third aspects, a meandering channel region can be formed in a semiconductor layer of a square or rectangular active region, for example, in plan view, and the channel width can be efficiently increased. A MOSFET diode having a smaller channel area and a wider channel width W can be realized, and the utilization efficiency of the layout can be improved.

[Invention 4] The semiconductor device of Invention 4 is characterized in that, in the semiconductor device of Invention 2 or 3, the corner portion of the portion where the first portion and the second portion intersect is rounded in plan view. It is what. With such a configuration, the electric field concentration at the corner can be relaxed.
[Invention 5] A method of manufacturing a semiconductor device of Invention 5 includes a step of forming a gate insulating film on a semiconductor layer formed on a substrate via an insulating layer, and a step of forming a gate electrode on the gate insulating film. And a step of forming a source or drain in each of the semiconductor layers on both sides of the gate electrode, and a step of forming a wiring connecting one of the source or drain and the gate electrode, It has a shape that is stretched while swinging left and right in one direction in a plan view.
According to such a method, the channel width of the MOSFET diode can be increased efficiently, and the utilization efficiency of the layout can be increased.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
1A and 1B are diagrams illustrating a configuration example of a semiconductor device according to an embodiment of the present invention. FIG. 1A is a plan view, and FIG. 1B is a line X1-X′1 in FIG. It is sectional drawing when cut | disconnecting. In FIG. 1A, the interlayer insulating film is not shown in order to avoid complication of the drawing.

As shown in FIGS. 1A and 1B, this semiconductor device includes an SOI substrate 10, an element isolation film 11 formed on the SOI substrate 10, and a region surrounded by the element isolation film 11 in plan view ( That is, a MOSFET diode 50 formed on the Si layer 5 in the active region) is provided. Here, the SOI substrate 10 includes, for example, a bulk Si substrate 1, an insulating layer 3 formed on the Si substrate 1, and an Si layer 5 (that is, an SOI layer) formed on the insulating layer 3. The insulating layer 3 is made of, for example, a SiO ₂ film and is also called a BOX layer. The element isolation film 11 is made of, for example, a silicon SiO ₂ film. As shown in FIG. 1B, the lower surface of the element isolation film 11 is in contact with the upper surface of the insulating layer 3, and the Si layer 5 in the active region is completely removed from the periphery by the element isolation film 11 and the insulating layer 3. The elements are isolated.

  The MOSFET diode 50 is formed on the gate insulating film 13 formed on the Si layer 5 in the active region, the gate electrode 15 formed on the gate insulating film 13, and the Si layer 5 on both sides of the gate electrode 15, respectively. Source or drain (hereinafter referred to as S / D layer) 17, 18, plug electrode 23 formed on gate electrode 15, plug electrode 25 formed on S / D layer 17, S / D A plug electrode 27 formed on the D layer 18; a wiring 31 that is electrically connected to the plug electrode 23 and the plug electrode 27 to short-circuit them; and a wiring 33 that is electrically connected to the plug electrode 25. Prepare. The wirings 31 and 33 are respectively formed on the interlayer insulating film 21.

  When the MOSFET diode 50 shown in FIGS. 1A and 1B is an n-type, the S / D layers 17 and 18 are formed of an n-type impurity diffusion layer. In the n-type MOSFET diode 50, when the wiring 31 is connected to the cathode potential and the wiring 33 is connected to the anode potential, the channel region immediately below the gate electrode 15 is inverted to the n-type, and the S / D layers 17, 18 Current flows between them. When the MOSFET diode 50 is p-type, the S / D layers 17 and 18 are p-type impurity diffusion layers. In the p-type MOSFET diode 50, when the wiring 31 is connected to the anode potential and the wiring 33 is connected to the cathode potential, the channel region immediately below the gate electrode 15 is inverted to the p-type, and the S / D layers 17, 18 Current flows between them. The S / D layer 17 is, for example, a source, and the S / D layer 18 is, for example, a drain.

By the way, as shown in FIG. 1A, the gate electrode 15 has a shape extended while swinging left and right in the X direction in a plan view. For example, as shown in FIG. 6, the gate electrode 15 has a first part 15a along the X direction in a plan view and a second part 15b along the Y direction in a plan view, and the first part 15a. And the second portion 15b are alternately connected. The Y direction is a direction perpendicular to the X direction in plan view. The first portion 15a and the second portion 15b are formed on the Si layer in the region surrounded by the element isolation film 11 (that is, the active region) via the gate insulating film.
As described above, the gate electrode 15 has the first portion 15a and the second portion 15b, thereby forming a meandering shape in plan view. As a result, a meandering channel region can be formed in the Si layer 5 of the rectangular or square active region in plan view, and the channel width W can be increased efficiently.

Next, a method for manufacturing the semiconductor device shown in FIGS. 1A and 1B will be described.
2 to 5 are process diagrams showing the method of manufacturing the semiconductor device according to the first embodiment of the present invention, where (a) is a plan view and (b) is a cross-sectional view. In FIG. 5A, the interlayer insulating film is not shown in order to avoid complication of the drawing.
As shown in FIGS. 2A and 2B, first, an SOI substrate 10 is prepared. As described above, the SOI substrate 10 includes, for example, the bulk Si substrate 1, the insulating layer 3 formed on the Si substrate 1, and the Si layer 5 formed on the insulating layer 3. Such an SOI substrate 10 is formed by, for example, a SIMOX method (Separation by IMplantation of Oxygen) or a bonding technique.

Next, as illustrated in FIGS. 2A and 2B, an element isolation film 11 is formed on the SOI substrate 10. As described above, the element isolation film 11 is made of, for example, a SiO ₂ film, and is formed by, for example, the LOCOS method or the STI method. As shown in FIGS. 2A and 2B, the formation of the element isolation film 11 completely isolates the Si layer 5 in the active region from its periphery.
Next, in FIGS. 2A and 2B, in order to adjust the threshold value of the MOSFET diode 50, n-type impurities or p-type impurities are ion-implanted into the Si layer 5 in the active region. Here, when the n-type MOSFET diode 50 is formed, for example, a p-type impurity is ion-implanted into the Si layer 5. Further, when the p-type MOSFET diode 50 is formed, for example, n-type impurities are ion-implanted into the Si layer 5. The n-type impurity is, for example, phosphorus or arsenic, and the p-type impurity is, for example, boron. Such ion implantation is also referred to as channel doping or Vth controlled ion implantation, for example.

Next, as shown in FIGS. 3A and 3B, a gate insulating film 13 is formed on the surface of the Si layer 5. The gate insulating film 13 is, for example, a SiO ₂ film or a silicon oxynitride film (SiON) formed by thermal oxidation, or a High-k material film. Next, a polysilicon (poly-Si) film is formed all over the SOI substrate 10 on which the gate insulating film 13 is formed. The polysilicon film is formed by, for example, a CVD method. Here, impurities are introduced into the polysilicon film by ion implantation or in-situ to make the polysilicon film conductive.

  Next, the polysilicon film is partially etched by photolithography technique and etching technique to form the gate electrode 15. Here, for example, as shown in FIG. 6, the gate electrode 15 having the first portion 15 a and the second portion 15 b is formed on the Si layer 5 in the active region via the gate insulating film 13. As shown in FIG. 3A, the length of the long side of the gate electrode 15 (that is, the long side of the second portion 15b) is L1, and the short side of the gate electrode 15 (that is, the first portion 15a) When the length of the long side) is L2, the channel width (that is, the gate width) W is represented by, for example, L1 × 5 + L2 × 6.

As an example, if L1 = 400 μm and L2 = 50 μm, the gate width W = 400 μm × 5 + 50 μm × 6 = 2.3 mm. At this time, the size of the active region can be set such that, for example, the length L _{X of} one side along the X direction is 300 μm and the length L _{Y of} one side along the Y direction is 420 μm. That is, the gate electrode 15 having a gate width W = 2.3 mm can be formed in an active region having an area S = 300 μm × 420 μm.

  Next, as shown in FIG. 4A, impurities are ion-implanted into the Si layer 5 using the gate electrode 15 as a mask and heat treatment is performed to form S / D layers 17 and 18. For example, when the n-type MOSFET diode 50 is formed, n-type impurities are ion-implanted into the Si layer 5 and heat treatment is performed to form the n-type S / D layers 17 and 18. When the p-type MOSFET diode 50 is formed, p-type impurities are ion-implanted into the Si layer 5 and subjected to a heat treatment to form the p-type S / D layers 17 and 18. The n-type impurity is, for example, phosphorus or arsenic, and the p-type impurity is, for example, boron. In this way, S / D layers 17 and 18 are formed on both sides of the gate electrode 15, respectively.

  Next, as shown in FIGS. 5A and 5B, an interlayer insulating film 21 is formed over the entire Si substrate 1. Then, the interlayer insulating film 21 is partially etched by photolithography technique and etching technique to form contact holes on the gate electrode 15 and the S / D layers 17 and 18, respectively. Further, plug electrodes 23, 25, 27 are formed in these contact holes, respectively, and the gate electrode 15 and the S / D layers 17, 18 are respectively drawn out on the interlayer insulating film 21.

  Thereafter, a conductive film such as aluminum is formed on the interlayer insulating film 21 by, for example, a sputtering technique. Then, the conductive film is partially etched by the photolithography technique and the etching technique, so that the S / D layer (for example, the drain) 18 and the gate electrode 15 are formed as shown in FIGS. A wiring 31 that is electrically connected to short-circuit them and a wiring 33 that is electrically connected to the S / D layer (for example, source) 17 are formed. As a result, the MOSFET diode 50 shown in FIGS. 1A and 1B is completed.

  As described above, according to the embodiment of the present invention, a meandering channel region can be formed in the Si layer 5 of, for example, a square or rectangular active region in plan view, and the channel width W is efficiently widened. be able to. For example, as shown in FIG. 3A, when the length (L1) of the long side of the gate electrode 15 having a meandering shape is 400 μm and the length (L2) of the short side is 50 μm, the channel width W is 2 3 mm. A channel region having such a wide channel width W can be formed in an active region having an area S = 300 μm × 420 μm. A MOSFET diode having a smaller channel area and a wider channel width W can be realized, and the utilization efficiency of the layout can be improved. Therefore, the size of the IC chip incorporating the MOSFET diode can be reduced.

  In this embodiment, the Si substrate 1 corresponds to the “substrate” of the present invention, and the Si layer 5 corresponds to the “semiconductor layer” of the present invention. Further, the S / D layer 18 corresponds to “one of the source or drain” of the present invention, and the wiring 31 corresponds to “wiring for connecting one of the source or drain and the gate electrode” of the present invention. Further, the X direction corresponds to “one direction” of the present invention, and the Y direction corresponds to “other direction” of the present invention.

  In the first embodiment described above, for example, as shown in FIG. 6, the case where the corner portion of the intersecting portion where the first portion 15a and the second portion 15b intersect is squared is illustrated. The shape of 15 in plan view (hereinafter referred to as a planar shape) is not limited to this. For example, as shown in FIG. 7, the corner portion of the intersection where the first portion 15a and the second portion 15b intersect may be rounded. With such a configuration, the electric field concentration at the corner can be relaxed. Further, in the present invention, for example, as shown in FIG. 7, the first portion 15a and the second portion 15b are not perpendicular (that is, perpendicular) in a plan view, but form a meandering shape by crossing at a wide angle. Also good. Even with such a configuration, the gate electrode 15 has a shape that is extended while swinging left and right in the X direction, so that the channel width W can be efficiently increased.

1 is a diagram showing a configuration example of a semiconductor device according to an embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to the embodiment (part 1); FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor device according to the embodiment (part 2); FIG. 3 is a view showing a method for manufacturing a semiconductor device according to the embodiment (part 3); FIG. 4 is a diagram (part 4) illustrating a method for manufacturing a semiconductor device according to the embodiment. FIG. 4 is a diagram illustrating an example of a gate electrode 15. The figure which shows the other example of the gate electrode 15 (the 1). The figure which shows the other example of the gate electrode 15 (the 2). The figure which shows a prior art example.

Explanation of symbols

  1 Si substrate, 3 Insulating layer (BOX layer), 5 Si layer (SOI layer), 10 SOI substrate, 11 Element isolation film, 13 Gate insulating film, 15 Gate electrode, 15a First part, 15b Second part, 17, 18 S / D layer, 21 interlayer insulating film, 23, 25, 27 plug electrode, 31, 33 wiring

Claims (5)

A semiconductor layer formed on a substrate via an insulating layer;
A gate insulating film formed on the semiconductor layer;
A gate electrode formed on the gate insulating film;
A source or drain formed in each of the semiconductor layers on both sides of the gate electrode;
A wiring connecting one of the source and drain and the gate electrode,
The semiconductor device according to claim 1, wherein the gate electrode has a shape extended while swinging left and right in one direction in a plan view. The gate electrode has a first portion along the one direction in a plan view and a second portion along another direction perpendicular to the one direction in a plan view,
The semiconductor device according to claim 1, wherein the first part and the second part are alternately connected. An element isolation film formed on the insulating layer so as to surround the second semiconductor layer in plan view,
3. The first part and the second part are formed on the semiconductor layer in a region surrounded by the element isolation film via the gate insulating film, respectively. Semiconductor device.   4. The semiconductor device according to claim 2, wherein a corner portion of a portion where the first portion and the second portion intersect has a roundness in plan view. Forming a gate insulating film on the semiconductor layer formed on the substrate via the insulating layer;
Forming a gate electrode on the gate insulating film;
Forming a source or a drain in each of the semiconductor layers on both sides of the gate electrode;
Forming a wiring connecting one of the source or drain and the gate electrode,
The method of manufacturing a semiconductor device, wherein the gate electrode has a shape extended while swinging left and right in one direction in a plan view.

Images